CN112582008A - Monotonic counter and method of operating the same - Google Patents
Monotonic counter and method of operating the same Download PDFInfo
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- CN112582008A CN112582008A CN202011456260.1A CN202011456260A CN112582008A CN 112582008 A CN112582008 A CN 112582008A CN 202011456260 A CN202011456260 A CN 202011456260A CN 112582008 A CN112582008 A CN 112582008A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
- G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
- G11C16/345—Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification
Abstract
The invention provides a monotonic counter which comprises a controller and a plurality of storage blocks, wherein each storage block comprises a counting base bit, an identification bit, a check bit and a data bit for storing counting data, wherein: the controller is used for determining the storage block with the effective identification bit and the effective check bit as the current storage block when the identification bit and the effective check bit of only one storage block are effective, and determining the current storage block from the plurality of storage blocks by comparing the size of the counting base bit when the identification bit and the effective check bit of the plurality of storage blocks are effective, so that the monotonic counter can find the current storage block which counts at the current moment when an abnormal condition occurs without additionally introducing an additional storage block into the monotonic counter, and the operation method of the monotonic counter is simplified.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a monotonic counter and an operation method thereof.
Background
The Replay Protection Monotonic Counter (RPMC) is a Counter having a Monotonic counting function, and the Replay Protection Monotonic Counter is only monotonically increased along with a change in a count value after data counted in the Replay Protection Monotonic Counter is replied. Usually, the response protection monotonic counter is combined with FLASH (FLASH memory) to ensure confidentiality and integrity of read and write data during data storage. For example, the response protection monotonic counter is combined with the FLASH to determine the storage times of the memory, and when the FLASH reads and writes data once, a count value is added to the monotonic counter, so that a complete data record is provided for the read and write data times of the FLASH; for another example, in the data sending process, the data is counted monotonously, so that the non-repeatability of the data is ensured, and the confidentiality of data sending can be improved.
In the prior art, a response protection monotonic counter usually adopts a mode of adding an additional storage block to process an abnormal power-down condition and some special conditions of the counter, so that when the abnormal condition occurs, the response protection monotonic counter can determine a current storage block by reading data of an identification bit in the additional storage block. However, in this way, the flag of the additional memory block in the response protection monotonic counter needs to be updated from time to time, and the operation method is complicated.
Disclosure of Invention
The invention provides a monotonic counter and an operation method thereof, which effectively solve the problem that when an abnormal condition occurs, the operation method of the monotonic counter for determining a current storage block is complex.
In order to solve the above problem, the present invention provides a monotonic counter comprising a controller and a plurality of memory blocks including a count base bit, an identification bit, a check bit, and a data bit for storing count data, wherein:
the controller is configured to determine that the memory block with the valid identification bit and valid check bit is a current memory block when the identification bit and the valid check bit of only one memory block are valid, and determine the current memory block from the plurality of memory blocks by comparing the size of the count base bit when the identification bit and the valid check bit of a plurality of memory blocks are valid.
Further preferably, when there are a plurality of the identification bits and the check bits of the storage block valid, the controller is further configured to:
when each storage block is written in a negation mode, determining the storage block corresponding to the counting base bit with small recording data as a current storage block; and/or the presence of a catalyst in the reaction mixture,
and when each storage block is not written in a negation mode, determining that the storage block corresponding to the counting base bit with large recording data is a current storage block.
Further preferably, the controller is further configured to read a count value of the current storage block, where the count value is a sum of data bits of the current storage block and data recorded by a count base bit.
Further preferably, the controller is further configured to:
when the current storage block is not fully written, writing data into a first data bit which does not store counting data in the current storage block for counting; and/or the presence of a catalyst in the reaction mixture,
and when the current storage block is full, switching the storage block of which the data bit does not store the counting data into the current storage block, and writing data.
In another aspect, the present invention further provides an operation method of a monotonic counter, where the monotonic counter includes a plurality of memory blocks, and the operation method includes:
reading, namely reading the counting base bit, the identification bit and the check bit of each storage block;
a first determination step of determining, when the identification bit and the check bit of only one of the storage blocks are valid, that the storage block in which the identification bit and the check bit are valid is a current storage block;
a second determination step of determining a current memory block from among the plurality of memory blocks by comparing sizes of the count base bits when the identification bits and the check bits of the plurality of memory blocks are valid.
Further preferably, the second determining step may specifically include:
a negation judgment substep, which is used for judging whether each storage block is negation write-in or not; and a process for the preparation of a coating,
a first sub-determination step of determining, if the negation is determined to be yes, that the memory block corresponding to the count base bit having small recording data is a current memory block; and/or the presence of a catalyst in the reaction mixture,
and a second sub-determination step of determining that the storage block corresponding to the counting base bit with large recording data is the current storage block if the negation judgment is negative.
Further preferably, after the first determining step and/or the second determining step, the method may further include:
reading a count value of the current storage block, wherein the count value is the sum of the data bit of the current storage block and the data recorded by the count base bit.
Further preferably, after the first determining step and/or the second determining step, the operating method further includes a counting step, the counting step including:
a full-writing judging step, namely judging whether the current storage block is full; and a process for the preparation of a coating,
a first writing step of switching the memory block in which the data bit does not store the count data to the current memory block and writing data if the full writing judgment is yes; and/or the presence of a catalyst in the reaction mixture,
and a second writing step, if the full writing judgment is no, writing data into the first data bit which does not store counting data in the current storage block for counting.
Further preferably, the first writing step may specifically include:
a count base bit writing sub-step of writing the count value into the count base bit of the current memory block;
an identification bit writing sub-step, writing the identification bit of the current storage block;
a check bit writing sub-step, writing the check bit of the current storage block;
and a data bit writing sub-step, writing data in the first data bit which does not store counting data in the current storage block for counting.
Further preferably, after the first writing step, the method may further include:
and an erasing step, namely erasing the storage blocks except the current storage block.
The invention has the beneficial effects that: the invention provides a monotonic counter which comprises a controller and a plurality of storage blocks, wherein each storage block comprises a counting base bit, an identification bit, a check bit and a data bit for storing counting data, wherein: the controller is used for determining the storage block with the effective identification bit and the effective check bit as the current storage block when the identification bit and the effective check bit of only one storage block are effective, and determining the current storage block from the plurality of storage blocks by comparing the size of the counting base bit when the identification bit and the effective check bit of the plurality of storage blocks are effective, so that the monotonic counter can find the current storage block which counts at the current moment when an abnormal condition occurs without additionally introducing an additional storage block into the monotonic counter, and the operation method of the monotonic counter is simplified.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the description of the embodiments according to the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without inventive effort.
Fig. 1 is a schematic structural diagram of a monotonic counter according to an embodiment of the present invention.
Fig. 2 is a flow chart illustrating an operation method of the monotonic counter according to an embodiment of the present invention.
Fig. 3 is a schematic flow chart of a further method for operating a monotonic counter according to an embodiment of the present invention.
Fig. 4 is a flow chart illustrating a counting step in an operation method of the monotonic counter according to the embodiment of the present invention.
Fig. 5 is a schematic diagram illustrating a further flow of counting steps in the method for operating the monotonic counter according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention is used for solving the problem that the response protection monotonic counter in the prior art is complex in operation method when the response protection monotonic counter determines the current storage block when an abnormal condition occurs.
Specifically, the abnormality of the answer protection monotonic counter refers to the occurrence of abnormal power down, reset, unstable voltage, and the like of the counter.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a monotonic counter 100 according to an embodiment of the present invention, and it can be seen from fig. 1 that each component and the relative position relationship of each component according to the embodiment of the present invention are shown.
As shown in fig. 1, the monotonic counter 100 includes a controller 110 and a plurality of memory blocks 120, and each memory block 120 includes a count base bit 121, an identification bit 122, a check bit 123, and a plurality of data bits 124 for storing count data, wherein:
the controller 110 is configured to determine the memory block 120 with the valid flag bit 122 and the valid check bit 123 as a current memory block when the flag bit 122 and the valid check bit 123 of only one memory block 120 are valid, and determine the current memory block from the plurality of memory blocks 120 by comparing the sizes of the count base bit 121 when the flag bit 122 and the valid check bit 123 of the plurality of memory blocks 120 are valid.
It should be noted that the monotonic counter 100 is used to ensure confidentiality and integrity of the corresponding memory read/write data, the count data in the monotonic counter 100 can be monotonically incremented, and since the data bits 124 of each memory block 120 in the monotonic counter 100 have a finite value, when the count value in one memory block 120 in the monotonic counter 100 reaches the upper limit, the counting is continued by switching to a memory block 120 that has not been counted or has been counted but has been erased. When the memory block 120 is switched to count, the count data of the memory block 120 before switching must be stored in the memory block 120 after switching to serve as the basis for counting the memory block 120 after switching, the memory block 120 after switching will continue to count on the basis of the count, and the count base bit 121 is used for recording the count data counted when the previous memory block is fully written;
the data recorded in the flag bit 122 is used to indicate whether the memory block 120 needs to be erased and programmed, and specifically, the flag bit 122 has only two data states, one data state indicates that the memory block 120 needs to be erased and programmed (e.g., 00), and one data state indicates that the memory block 120 has been erased and programmed and does not need to be erased and programmed (e.g., FF);
the validity of check bit 123 is used to characterize the count base bit 121 of memory block 120 and whether the data in identification bit 122 is valid. Specifically, the count base 121 and the flag 122 generate a value through some check operation (such as an addition operation, a parity operation, an exclusive-or operation, or a cyclic redundancy check (cyclic redundancy check) operation), and then compare the value with the value in the check bit 123, if the two values are equal, the check bit 123 is represented to be valid, that is, the data in the memory block 120 corresponding to the check bit 123 is valid, no exception occurs, and the memory block is also indicated as the current memory block; if the two values are not equal, the check bit 123 is represented to be invalid, that is, the data in the storage block 120 corresponding to the check bit 123 is invalid or abnormal, which also indicates that the storage block is not the current storage block;
therefore, when the identification bit 122 and the check bit 123 of only one memory block 120 are valid, the memory block 120 with the valid identification bit 122 and the valid check bit 123 can be determined as the current memory block;
the data bit 124 is a unit for storing count data, and generally, in order to increase the storage amount of the storage block 120 and reduce the number of times of erasing, each storage block 120 includes a plurality of data bits 124, and each time Flash corresponding to the monotonic counter 100 performs one data read/write operation, one data bit 124 of the storage block 120 in the monotonic counter 100 is written to be 1.
Further, when the identification bits 122 and the check bits 123 of the plurality of memory blocks 120 are valid, the controller 110 is further configured to:
when each storage block 120 is written in a negation mode, determining the storage block 120 corresponding to the counting base bit 121 with small recording data as a current storage block; or the like, or, alternatively,
when each memory block 120 is not written for negation, the memory block 120 corresponding to the count base bit 121 with large record data is determined as the current memory block.
It should be noted that there are three ways to express the signed number of the computer system: original code, inverse code, and complement code. The original code includes a numerical bit and a sign bit, the numerical bit is an absolute value of a true value represented by the original code, the sign bit represents a positive number when the sign bit is "0", and represents a negative number when the sign bit is "1", for example, the true value represented by four-bit binary data of the original code "10101" is-5. The inverse code of the original code is obtained by inverting all bits of the original code except the sign bit (inverting "0" in binary data to "1" and "1" to "0" at the same time). For negative numbers, their complement equals the negation of all the bits of their original code except the sign bit, plus 1, and for positive numbers, their original code equals the negation of their complement.
For example, the original code of the decimal true value-12 is represented by four-bit binary data with sign bit as 11100, and the inverse code thereof is 10011, and the inverse code represents the decimal value of-3; the original code of the decimal true value-13 is represented by four-bit binary data with sign bit as 11101, and the inverse code thereof is 10010, and the inverse code represents the decimal value of-2. Therefore, when the memory block 120 is written in the inverted state, the smaller the value of the inverted code in the count base 121 is, the larger the value of the corresponding original code is, and the larger the value of the inverted code in the count base 121 is, the smaller the value of the corresponding original code is. Since the count base bit 121 is the total number of count data for recording the monotonic counter 100, when the memory block 120 is write-backed, the memory block 120 corresponding to the count base bit 121 having a small recording data is the current memory block. When the memory block 120 is not written for negation, the binary data on the count base bit 121 is the true code of the true value that it is to represent, and the value of the true code corresponds to the true value, so when the memory block 120 is not written for negation, the memory block 120 corresponding to the count base bit 121 with the large record data is the current memory block.
Further, the controller 110 is also used to control the current memory block of the monotonic counter 100 to count, such as:
when the current storage block is not fully written, writing data into a data bit 124 which is the first data in the current storage block and does not store counting data for counting; or the like, or, alternatively,
when the current memory block is full, the memory block 120 in which the data bits 124 do not store the count data is switched to the current memory block, and data writing is performed.
Further, the controller 110 is further configured to read a count value of the current memory block, where the count value is a sum of data recorded by the data bits 124 and the count base bit 121 of the current memory block, and the count value is a sum of data recorded by the data bits 124 and the count base bit 121 of the current memory block, which is obtained by summing values of the data bits 124 and all data bits of the previous memory block.
In practical applications, the monotonic counter 100 is often used with a flash memory, and each time the flash memory reads and writes data, a 1 is written into a data bit in the current memory block of the monotonic counter 100, so that the value of all data bits 124 plus the count base bit 121 in one memory block 120 is equal to the count value at the current time. For example, the data bits 124 may represent n 0's for adding 1 to the count value of the monotonic counter 100 (n is an integer greater than or equal to 1), and when the count base bit 121 of the monotonic counter 100 is 1000, n is 8, and the data bits 124 have 0's of 3 bytes, then the count value of the monotonic counter 100 is 1003 at the current time.
Different from the prior art, the present invention provides a monotonic counter 100, which includes a controller 110 and a plurality of memory blocks 120, and each memory block 120 includes a count base bit 121, an identification bit 122, a check bit 123, and a data bit 124 for storing count data, wherein: the controller 110 is configured to determine the memory block 120 with the valid flag bit 122 and the valid check bit 123 as a current memory block when the flag bit 122 and the valid check bit 123 of only one memory block 120 are valid, and determine the current memory block from the plurality of memory blocks 120 by comparing the size of the count base bit 121 when the flag bit 122 and the valid check bit 123 of the plurality of memory blocks 120 are valid, so that the monotonic counter 100 can find the current memory block that counts at the current time when an abnormal condition occurs without additionally introducing an additional memory block into the monotonic counter 100, thereby simplifying the operation method of the monotonic counter 100.
Referring to fig. 2, fig. 2 is a schematic flow chart illustrating an operation method of the monotonic counter 100 according to an embodiment of the present invention, the operation method is applied to the monotonic counter 100, and the monotonic counter 100 includes a plurality of memory blocks, and the specific flow of the operation method can be as follows:
reading step S1O1, reading the counting base bit, the identification bit and the check bit of each storage block.
It should be noted that the monotonic counter 100 is used to ensure confidentiality and integrity of the read/write data of the corresponding memory, the count data in the monotonic counter 100 can be monotonically incremented, and since the data bits of each memory block in the monotonic counter 100 have a finite value, when the count value in one memory block in the monotonic counter 100 reaches the upper limit, the count is switched to a memory block that is not counted or that has been counted but has been erased. When the storage block is switched for counting, the counting data of the storage block before switching must be stored in the storage block after switching to serve as the basis of the counting of the storage block after switching, the storage block after switching can continue to count on the basis of the counting, and the counting base bit is used for recording the counting data counted when the previous storage block is fully written and switched;
the data recorded in the identification bit is used for representing whether the memory block needs to be subjected to erasing and programming operations, and specifically, the identification bit only has two data states, one data state represents that the memory block needs to be subjected to erasing and programming operations (such as 00), and the other data state represents that the memory block is subjected to erasing and programming operations and does not need to be subjected to erasing and programming operations (such as FF);
the validity of the check bit is used to characterize the count base bit of the memory block and whether the data in the identification bit is valid. Specifically, the count base bit and the flag bit generate a value through some kind of check operation (such as addition operation, parity operation, exclusive-or operation, or cyclic redundancy check (cyclic redundancy check) operation), and then the value is compared with the value in the check bit, and if the two values are equal, the check bit is valid, that is, the data in the storage block corresponding to the check bit is valid, no exception occurs, and the storage block is also indicated as the current storage block; if the two values are not equal, the representation check bit is invalid, that is, the data in the storage block corresponding to the check bit is invalid or abnormal, indicating that the storage block is not the current storage block;
the data bit is a unit for storing count data, and generally, in order to increase the storage amount of the memory block and reduce the number of times of erasing, each memory block includes a plurality of data bits, and each time Flash corresponding to the monotonic counter 100 performs a data read/write operation, one data bit of the memory block in the monotonic counter 100 is written to be 1.
A first determining step s1o2, when the identification bit and the check bit of only one storage block are valid, determining the storage block with the valid identification bit and check bit as the current storage block.
Specifically, when only the identification bit and the check bit of one memory block are valid, the current memory block which is counted at the current time does not need to be searched through extra judgment, and the monotonic counter determines the memory block corresponding to the identification bit and the check bit which are in the valid state as the current memory block.
A second determination step s1o3. when the identification bits and the check bits of the plurality of memory blocks are valid, the current memory block is determined from the plurality of memory blocks by comparing the sizes of the count base bits.
Specifically, when the identification bits and the check bits of the plurality of memory blocks are valid, the monotonic counter 100 has the identification bits of the plurality of memory blocks in a valid state due to an abnormal condition (such as abnormal power down, reset, unstable voltage, etc.), and at this time, the current memory block needs to be determined by determining the size of the data stored in the count base bit.
Further, with reference to fig. 2, after the first determining step S102 and/or the second determining step S103, the method may further include:
and a counting value reading step S104, reading the counting value of the current storage block, wherein the counting value is the sum of the data bit of the current storage block and the data recorded by the counting base bit.
The count value is the sum of the data bits of the current memory block and the data recorded by the count base bit, and the count value is the sum of the data bits of the current memory block and the data recorded by the count base bit, which means that the value of the data bits of the previous memory block and the value in all the data bits are summed.
In practical applications, the monotonic counter 100 is often used with a flash memory, and each time the flash memory reads and writes data, a 1 is written in a data bit in a current memory block of the monotonic counter 100, so that the value of all data bits in a memory block plus a count base bit is equal to the count value at the current time. For example, the data bits may represent n 0's by adding 1 to the count value of the monotonic counter 100 (n is an integer greater than or equal to 1), and when the count base bit of the monotonic counter 100 is 1000, n is 8, and the data bit has 0 of 3 bytes, then the count value of the monotonic counter 100 is 1003 at the current time.
Referring to fig. 3, fig. 3 is a schematic flow chart of an operation method of the monotonic counter 100 according to an embodiment of the present invention, and as shown in fig. 3, the second determining step S103 specifically includes:
negation judgment substep S1031, when the identification bits and the check bits of the plurality of storage blocks are valid, judging whether each storage block is negation write-in; and a process for the preparation of a coating,
a first sub-determination step S1032. if the negation is judged to be yes, determining that the storage block corresponding to the counting base bit with small recording data is the current storage block; or the like, or, alternatively,
and a second sub-determination step S1033, if the negation judgment is negative, determining that the storage block corresponding to the counting base bit with large recording data is the current storage block.
It should be noted that there are three ways to express the signed number of the computer system: original code, inverse code, and complement code. The original code includes a numerical bit and a sign bit, the numerical bit is an absolute value of a true value represented by the original code, the sign bit represents a positive number when the sign bit is "0", and represents a negative number when the sign bit is "1", for example, the true value represented by four-bit binary data of the original code "10101" is-5. The inverse code of the original code is obtained by inverting all bits of the original code except the sign bit (inverting "0" in binary data to "1" and "1" to "0" at the same time). For negative numbers, their complement equals the negation of all the bits of their original code except the sign bit, plus 1, and for positive numbers, their original code equals the negation of their complement.
For example, the original code of the decimal true value-12 is represented by four-bit binary data with sign bit as 11100, and the inverse code thereof is 10011, and the inverse code represents the decimal value of-3; the original code of the decimal true value-13 is represented by four-bit binary data with sign bit as 11101, and the inverse code thereof is 10010, and the inverse code represents the decimal value of-2. Therefore, when the memory block is written in the inverted state, the smaller the value of the inverted code at the count base is, the larger the value of the corresponding original code is, and the larger the value of the inverted code at the count base is, the smaller the value of the corresponding original code is. Since the count base bit is the total number of count data for recording the monotonic counter 100, when the memory block is write-backed, the memory block corresponding to the count base bit having a small record data is the current memory block. When the memory block is not written in the negation mode, the binary data on the counting base bit is the true value original code to be represented, the value of the original code corresponds to the true value, therefore, when the memory block is not written in the negation mode, the memory block corresponding to the counting base bit with large recording data is the current memory block.
Further, the operation method of the monotonic counter 100 further includes a counting step, please refer to fig. 4, fig. 4 is a flowchart illustrating the counting step in the operation method of the monotonic counter 100 according to the embodiment of the present invention, as shown in fig. 4, after the first determining step S1O2 and/or the second determining step S1O3, the counting step may specifically include:
a full-writing judgment step S201. judging whether the current storage block is full; and a process for the preparation of a coating,
a first writing step S202, if the full writing judgment is yes, switching the storage block of which the data bit does not store the counting data into the current storage block, and writing data; or the like, or, alternatively,
and a second writing step S203. if the full writing judgment is negative, writing data into the first data bit which does not store counting data in the current storage block for counting.
Further, with reference to fig. 4, after the first writing step S202, the method may further include:
and an erasing step S204, erasing the storage blocks except the current storage block.
Specifically, the erasing step S204 is to ensure that, after the current storage block is full of data, there is a storage block which does not store counting data for switching and continuing to count.
Referring to fig. 5, fig. 5 is a schematic flowchart illustrating a counting step in an operation method of the monotonic counter 100 according to an embodiment of the present invention, and as shown in fig. 5, the first writing step S202 may specifically include:
a counting base bit writing sub-step S2021, switching a storage block of which the data bit does not store counting data into a current storage block, and writing a counting value into the counting base bit of the current storage block;
an identification bit writing sub-step S2022, writing the identification bit of the current storage block;
a check bit writing substep S2023, writing the check bit of the current storage block;
a data bit writing sub-step s2024. write data in the first data bit of the current memory block which does not store the count data for counting.
Specifically, when data is written into the memory block, the monotonic counter 100 may have an abnormal situation such as power failure, which may cause an error in the data being written, and if the count base bit, the flag bit, and the check bit are written simultaneously, when an abnormal situation occurs, there may be a situation where data in the count base bit, the flag bit, and the check bit all have an error, and the check bit has a mismatch, so that, when the first writing step S202 is performed, the count base bit, the flag bit, and the check bit may be written in a sequential writing manner, specifically, the writing order may be: writing a counting base bit, then writing an identification bit, and finally writing a check bit; it can also be: writing the counting base bit, then writing the check bit, and finally writing the identification bit, and the like. The sequential writing can prevent the error matching of the check bits due to the error of the data in the count base bit, the identification bit and the check bits when the monotonic counter 100 is abnormal.
Different from the prior art, the present invention provides an operation method of a monotonic counter 100, the operation method is applied to the monotonic counter 100, and the monotonic counter 100 includes a plurality of memory blocks, the operation method includes: reading the counting base bit, the identification bit and the check bit of each storage block; when the identification bit and the check bit of only one storage block are valid, determining the storage block with the valid identification bit and check bit as a current storage block; when the identification bits and the check bits of the plurality of memory blocks are valid, the current memory block is determined from the plurality of memory blocks by comparing the size of the counting base bit, so that the monotonic counter 100 can find the current memory block which counts at the current moment when an abnormal condition occurs without additionally introducing an additional memory block into the monotonic counter 100, and the operation method of the monotonic counter 100 is simplified.
In addition to the above embodiments, the present invention may have other embodiments. All technical solutions formed by using equivalents or equivalent substitutions fall within the protection scope of the claims of the present invention.
In summary, although the preferred embodiments of the present invention have been described above, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (10)
1. A monotonic counter comprising a controller and a plurality of memory blocks, the memory blocks comprising a count base bit, an identification bit, a check bit, and a data bit for storing count data, wherein:
the controller is configured to determine that the memory block with the valid identification bit and valid check bit is a current memory block when the identification bit and the valid check bit of only one memory block are valid, and determine the current memory block from the plurality of memory blocks by comparing the size of the count base bit when the identification bit and the valid check bit of a plurality of memory blocks are valid.
2. The monotonic counter of claim 1, wherein when the identification bits and the check bits of a plurality of the memory blocks are valid, the controller is further configured to:
when each storage block is written in a negation mode, determining the storage block corresponding to the counting base bit with small recording data as a current storage block; and/or the presence of a catalyst in the reaction mixture,
and when each storage block is not written in a negation mode, determining that the storage block corresponding to the counting base bit with large recording data is a current storage block.
3. The monotonic counter of claim 1, wherein the controller is further configured to read a count value of the current memory block, the count value being a sum of data bits of the current memory block and data recorded by a count base bit.
4. The monotonic counter of claim 1, wherein the controller is further configured to:
when the current storage block is not fully written, writing data into a first data bit which does not store counting data in the current storage block for counting; and/or the presence of a catalyst in the reaction mixture,
and when the current storage block is full, switching the storage block of which the data bit does not store the counting data into the current storage block, and writing data.
5. A method of operating a monotonic counter, the monotonic counter comprising a plurality of memory blocks, the method comprising:
reading, namely reading the counting base bit, the identification bit and the check bit of each storage block;
a first determination step of determining, when the identification bit and the check bit of only one of the storage blocks are valid, that the storage block in which the identification bit and the check bit are valid is a current storage block;
a second determination step of determining a current memory block from among the plurality of memory blocks by comparing sizes of the count base bits when the identification bits and the check bits of the plurality of memory blocks are valid.
6. The operating method according to claim 5, wherein the second determining step specifically includes:
a negation judgment substep, which is used for judging whether each storage block is negation write-in or not; and a process for the preparation of a coating,
a first sub-determination step of determining, if the negation is determined to be yes, that the memory block corresponding to the count base bit having small recording data is a current memory block; and/or the presence of a catalyst in the reaction mixture,
and a second sub-determination step of determining that the storage block corresponding to the counting base bit with large recording data is the current storage block if the negation judgment is negative.
7. The operating method according to claim 5, further comprising, after the first determining step and/or the second determining step:
reading a count value of the current storage block, wherein the count value is the sum of the data bit of the current storage block and the data recorded by the count base bit.
8. The operating method according to claim 7, characterized in that after the first and/or second determination step, the operating method further comprises a counting step comprising:
a full-writing judging step, namely judging whether the current storage block is full; and a process for the preparation of a coating,
a first writing step of switching the memory block in which the data bit does not store the count data to the current memory block and writing data if the full writing judgment is yes; and/or the presence of a catalyst in the reaction mixture,
and a second writing step, if the full writing judgment is no, writing data into the first data bit which does not store counting data in the current storage block for counting.
9. The operating method according to claim 8, wherein the first writing step specifically includes:
a count base bit writing sub-step of writing the count value into the count base bit of the current memory block;
an identification bit writing sub-step, writing the identification bit of the current storage block;
a check bit writing sub-step, writing the check bit of the current storage block;
and a data bit writing sub-step, writing data in the first data bit which does not store counting data in the current storage block for counting.
10. The operating method according to claim 8, further comprising, after the first writing step:
and an erasing step, namely erasing the storage blocks except the current storage block.
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