CN112581585B - TLM device of GPU command processing module based on SysML view and operation method - Google Patents
TLM device of GPU command processing module based on SysML view and operation method Download PDFInfo
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Abstract
The invention relates to the technical field of computer hardware modeling, in particular to a TLM device of a GPU command processing module based on a SysML view and an operation method. The system comprises a preprocessing unit, a simplified instruction set processor, an access bus arbitration unit, a register unit, a vertex cache unit, a vertex index cache unit, an instruction cache unit and a data cache unit, wherein the preprocessing unit is used for realizing precoding, distribution and processing of all OpenGL commands, the simplified instruction set processor is used for realizing graphics command analysis, parameter setting, graphics function code issuing, graphics attribute and matrix parameter push and pop operations and matrix operation and parameter standardization operation of partial functions of all non-graphics drawing class commands, and the access bus arbitration unit is used for realizing access to an axi bus. The TLM device and the operating method of the GPU command processing module based on the SysML view can convert complex, tedious and ambiguous characters into clear graphic modes, and achieve preliminary verification of the GPU command processing module architecture.
Description
Technical Field
The invention belongs to the technical field of computer hardware modeling, relates to a TLM device of a GPU command processing module, and particularly relates to a TLM device of a GPU command processing module based on a SysML view and an operation method.
Background
SysML is a new system modeling language that is developed by International System engineering institute INCOSE (international council on Systems Engineering) and object management organization OMG (Object Management Engineering) based on reuse and expansion of subsets of UML 2.0. SysML defines new modeling elements by expanding the existing UML2.0 with new properties and constraints.
SysML is an abbreviation of System Modeling Language, which is an object-oriented graphical modeling language that expands some new elements compared to UML language (Unified Modeling Language ), which is more conducive to system engineering modeling, and compared to other languages such as SCADE modeling language, sysML is capable of modeling not only software but also hardware and the entire system. In the traditional chip design process, along with the increasing of the complexity of the design, the design codes and a large number of documents become more and more difficult to master, and the SysML presents the whole design from multiple angles by using various graphs, so that a huge and complex system can be clearly and rapidly shown, modeling and visual support is provided for software and hardware development, the design period is shortened, and the development progress and the functions of assisting in system design and verification are accelerated.
The system and the method can realize verification of the algorithm and the architecture of the command processing module in early stage of chip design by using the SysML graphic modeling language to carry out the design of the object-level model on the GPU command processing module, thereby greatly shortening the development period of projects.
Disclosure of Invention
Based on the problems in the background technology, the TLM device and the operation method of the GPU command processing module based on the SysML view can convert complex and complicated words which are easy to cause ambiguity into clear graphic modes, and realize the primary verification of the GPU command processing module architecture.
The technical scheme of the invention is as follows: the TLM device of the GPU command processing module based on the SysML view is characterized in that: the system comprises a preprocessing unit, a graphics command analysis unit, a parameter setting unit, a graphics function code issuing unit, a graphics attribute and matrix parameter push and pop operation, a partial function matrix operation and parameter standardization operation, an access bus arbitration unit, a register unit, a vertex cache unit, a vertex index cache unit, an instruction cache unit and a data cache unit, wherein the preprocessing unit is used for realizing the precoding and distribution of all OpenGL commands and the processing of partial OpenGL commands;
the preprocessing unit is respectively connected with the simplified instruction set processor, the access bus arbitration unit and the register unit;
the reduced instruction set processor is connected with the instruction cache unit and the data cache unit;
the preprocessing unit is connected with the vertex cache unit and the vertex index cache unit;
the preprocessing unit further comprises three FIFO units; the FIFO units are respectively graph_cmd_fifo, new_list_fifo and call_list_fifo; the three FIFO units of the graph_cmd_fifo, the new_list_fifo and the call_list_fifo are respectively an OpenGL command FIFO, a display list loading FIFO and a display list calling FIFO;
the TLM device also comprises a plurality of processes, methods and sockets;
the process and the method are used for realizing command preprocessing, RISC processing, report interrupt, display list FIFO management, DMA processing from a host to a command processor, parameter initialization process from a state parameter management unit to a command processor module, exception processing method and register management process from the state parameter management unit to the command processor module;
the socket is used for realizing the interconnection communication function with an external module;
the vertex cache unit and the vertex index cache unit provide cache for vertex array commands;
the instruction cache unit and the data cache unit provide caches of instructions and data for the reduced instruction set processor.
As a preferred option: the above processes include a pre_process_cthread process, a cmd_process_core_cthread process, a report_interrupt_method process, a list_fifo_message_cthread process, a hiu2cmd_dma_target_cthread process, a sgu2 cmd_parametric_target_cthread process, a sgu2cmd_graph_reg_target_cthread process;
the above methods include an outlide_acceptance_target_method method;
the sockets include cmd2sgu _draw_initial_socket, sgu _2cmd_resource_status_target_socket, cmd2hiu _cfg_dma2c0_initial_socket, cmd2hiu _cfg_dma_c2s0_initial_socket, cmd2hiu _cfg_dma2c1_initial_socket, cmd2hiu _cfg_dma2s1_initial_socket, cmd2sgu _graph_functional_initial_socket, sgu _funcode_selectjsocket, and wid2_ sgu _initial_socket vc2l2cache_initiator_socket, vic2l2cache_initiator_socket, cmd2axi0_initiator_socket, sgu2cmd_graph_reg_target_socket, cmd2hiu _excursions_irq_socket, usa2 cmd_excursions_status_socket, geu 2cmd_excursions_status_socket, jsu 2cmd_excursions_status_socket, sgu2cmd_paraminit_target_socket, sgu 2cmd_function_packet_destination_socket, hiu 2cmd_dma_socket.
The operating method of the TLM device of the GPU command processing module based on the SysML view is characterized by comprising the following steps of: the method comprises the following operation steps:
1) Creating CM package objects
1.1 Judging the cm_pkt_fifo state, if the cm_pkt_fifo state is empty, setting pre_process_busy to 0 and returning to the step 1); if cm_pkt_fifo is not empty, setting pre_process_busy to 1;
1.2 A read graphics command interface FIFO obtains a command packet header, sets an immittUnit, creates a CM packet object and stores command packet information into a linked list;
the execution unit comprises: 0-a preprocessing unit; 1-RISC reduced instruction set processor execution;
2) Display list command loading
2.1 If newlist_flag is equal to 1 and the current command is glNewList, the operation is invalid, and the simulation is exited; if newlist_flag is equal to 1 and the current command is not glNewList, writing the current command into the display list FIFO directly;
2.2 Judging a display list mode, if the mode is COMPILE, directly returning to the step 1), and continuously judging the cm_pkt_fifo state; if the mode is GL_COMPILE_AND_EXECUTE, entering step 3);
3) Command package classification
3.1 When the command packet is
The glArrayelement/glDrawelements/glLoadFirmWare/glNewList/glEndList/glCalllList command, then enter special command processing flow;
3.2 When the command packet is
A glVertex/glMaterial/glNormal/glColor/glSecondaryColor/glTexCoord/glMultiTexCoord/glFogCoord/glEdgeFlag/glVertexBackup0/glVertexBackup1/glVertexattrib graphic drawing command enters a drawing command processing flow and is uniformly sent to the SGU_GDU unit according to 160 bit width;
3.3 If the command packet is other commands except the two commands, sending the command packet to the processor of the reduced instruction set for processing;
3.4 Returning to step 1) to continue reading OpenGL commands.
As a preferred option: the processing method of the reduced instruction set processor in the step 3.3) comprises the following steps:
3.3.1 A risc _ enable signal is detected,
setting risc_core_busy=0 to 0 when risc_enable signal value is false and returning to step 3.3.1);
setting risc_core_busy=1 when risc_enable value is true and proceeding to step 3.3.2);
3.3.2 Analyzing the received command and carrying out striping treatment; configuring parameters carried by the command to a state parameter register, configuring and starting PCIe_DMA according to the data address and the size carried by the command, and issuing a function code in the graphic command to a lower-level pipeline unit of the 3D engine;
3.3.3 Returning to step 3.3.1) continuing to detect the risc _ enable signal.
As a preferred option: the GPU command processing module further comprises interrupt processing work, and when an interrupt occurs, the steps are as follows:
step 1: reading the glGetError_reg1-glGetError_reg3 error state registers;
step 2: performing logic OR operation on the glGetError_reg1-glGetError_reg3 register values, and giving a result to cmd_acceptance_irq_socket;
step 3: and ending the exit.
The invention has the advantages that:
according to the TLM device of the GPU command processing module based on the SysML view, the overall design of the functions of the GPU command processing module is presented from two angles through the internal block diagram and the active diagram of the command processing module, complex and complicated characters which are easy to generate ambiguity are converted into clear graphic modes, the initial verification of the GPU command processing module architecture is realized, modeling and visual support is provided for software and hardware development, the design period is shortened, and development progress is accelerated and the functions of assisting in system design and verification are achieved.
Drawings
FIG. 1 is an internal block diagram of a GPU command processing module according to the present invention.
FIG. 2 is an active diagram of a GPU command processing module preprocessing process according to the present invention.
Fig. 3 is an active diagram of a risc kernel process of the GPU command processing module of the present invention.
FIG. 4 is an activity diagram of a GPU command processing module reporting interrupts in accordance with the present invention.
Detailed Description
The technical scheme of the invention is clearly and completely described below with reference to the accompanying drawings and the specific embodiments. It is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments, and that all other embodiments obtained by a person skilled in the art without making creative efforts based on the embodiments in the present invention are within the protection scope of the present invention.
Referring to fig. 1-4, a TLM device of a GPU command processing module based on a SysML view includes a preprocessing unit for implementing pre-decoding, allocation and processing of partial OpenGL commands for all OpenGL commands, a simplified instruction set processor for implementing graphics command parsing, parameter setting, graphics function code issuing, push and pop operations for graphics attributes and matrix parameters, and matrix operations and parameter normalization operations for partial functions, an access bus arbitration unit for implementing access to axi buses, a register unit, a vertex cache unit, a vertex index cache unit, an instruction cache unit, a cache unit for vertices;
the preprocessing unit is respectively connected with the simplified instruction set processor, the access bus arbitration unit and the register unit;
the reduced instruction set processor is connected with the instruction cache unit and the data cache unit;
the preprocessing unit is connected with the vertex cache unit and the vertex index cache unit;
the preprocessing unit further comprises three FIFO units; the FIFO units are respectively graph_cmd_fifo, new_list_fifo and call_list_fifo; the three FIFO units of the graph_cmd_fifo, the new_list_fifo and the call_list_fifo are respectively an OpenGL command FIFO, a display list loading FIFO and a display list calling FIFO;
the TLM device also comprises a plurality of processes, methods and sockets;
the process and the method are used for realizing command preprocessing, RISC processing, report interrupt, display list FIFO management, DMA processing from a host to a command processor, parameter initialization process from a state parameter management unit to a command processor module, exception processing method and register management process from the state parameter management unit to the command processor module;
the socket is used for realizing the interconnection communication function with an external module;
the vertex cache unit and the vertex index cache unit provide cache for vertex array commands;
the instruction cache unit and the data cache unit provide caches of instructions and data for the reduced instruction set processor.
As a preferred option: the above processes include a pre_process_cthread process, a cmd_process_core_cthread process, a report_interrupt_method process, a list_fifo_message_cthread process, a hiu2cmd_dma_target_cthread process, a sgu2 cmd_parametric_target_cthread process, a sgu2cmd_graph_reg_target_cthread process;
the above methods include an outlide_acceptance_target_method method;
the sockets include cmd2sgu _draw_initial_socket, sgu _2cmd_resource_status_target_socket, cmd2hiu _cfg_dma2c0_initial_socket, cmd2hiu _cfg_dma_c2s0_initial_socket, cmd2hiu _cfg_dma2c1_initial_socket, cmd2hiu _cfg_dma2s1_initial_socket, cmd2sgu _graph_functional_initial_socket, sgu _funcode_selectjsocket, and wid2_ sgu _initial_socket vc2l2cache_initiator_socket, vic2l2cache_initiator_socket, cmd2axi0_initiator_socket, sgu2cmd_graph_reg_target_socket, cmd2hiu _excursions_irq_socket, usa2 cmd_excursions_status_socket, geu 2cmd_excursions_status_socket, jsu 2cmd_excursions_status_socket, sgu2cmd_paraminit_target_socket, sgu 2cmd_function_packet_destination_socket, hiu 2cmd_dma_socket.
A method of operating a TLM device of a GPU command processing module based on a sysplex view, comprising the steps of:
1) Creating CM package objects
1.1 Judging the cm_pkt_fifo state, if the cm_pkt_fifo state is empty, setting pre_process_busy to 0 and returning to the step 1); if cm_pkt_fifo is not empty, setting pre_process_busy to 1;
1.2 A read graphics command interface FIFO obtains a command packet header, sets an immittUnit, creates a CM packet object and stores command packet information into a linked list;
the execution unit comprises: 0-a preprocessing unit; 1-RISC reduced instruction set processor execution;
2) Display list command loading
2.1 If newlist_flag is equal to 1 and the current command is glNewList, the operation is invalid, and the simulation is exited; if newlist_flag is equal to 1 and the current command is not glNewList, writing the current command into the display list FIFO directly;
2.2 Judging a display list mode, if the mode is COMPILE, directly returning to the step 1), and continuously judging the cm_pkt_fifo state; if the mode is GL_COMPILE_AND_EXECUTE, entering step 3);
3) Command package classification
3.1 When the command packet is
The glArrayelement/glDrawelements/glLoadFirmWare/glNewList/glEndList/glCalllList command, then enter special command processing flow;
3.2 When the command packet is
A glVertex/glMaterial/glNormal/glColor/glSecondaryColor/glTexCoord/glMultiTexCoord/glFogCoord/glEdgeFlag/glVertexBackup0/glVertexBackup1/glVertexattrib graphic drawing command enters a drawing command processing flow and is uniformly sent to the SGU_GDU unit according to 160 bit width;
3.3 If the command packet is other commands except the two commands, sending the command packet to the processor of the reduced instruction set for processing;
3.4 Returning to step 1) to continue reading OpenGL commands.
As a preferred option: the processing method of the reduced instruction set processor in the step 3.3) comprises the following steps:
3.3.1 A risc _ enable signal is detected,
setting risc_core_busy=0 to 0 when risc_enable signal value is false and returning to step 3.3.1);
setting risc_core_busy=1 when risc_enable value is true and proceeding to step 3.3.2);
3.3.2 Analyzing the received command and carrying out striping treatment; configuring parameters carried by the command to a state parameter register, configuring and starting PCIe_DMA according to the data address and the size carried by the command, and issuing a function code in the graphic command to a lower-level pipeline unit of the 3D engine;
3.3.3 Returning to step 3.3.1) continuing to detect the risc _ enable signal.
As a preferred option: the GPU command processing module further comprises interrupt processing work, and when an interrupt occurs, the steps are as follows:
step 1: reading the glGetError_reg1-glGetError_reg3 error state registers;
step 2: performing logic OR operation on the glGetError_reg1-glGetError_reg3 register values, and giving a result to cmd_acceptance_irq_socket;
step 3: and ending the exit.
Finally, it should be noted that the above embodiments are merely illustrative of the technical solution of the present invention, and not limiting thereof; although the invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art will understand that; the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (5)
1. A TLM device of a GPU command processing module based on a sysplex view, characterized in that: the system comprises a preprocessing unit, a graphics command analysis unit, a parameter setting unit, a graphics function code issuing unit, a graphics attribute and matrix parameter push and pop operation, a partial function matrix operation and parameter standardization operation, an access bus arbitration unit, a register unit, a vertex cache unit, a vertex index cache unit, an instruction cache unit and a data cache unit, wherein the preprocessing unit is used for realizing the precoding and distribution of all OpenGL commands and the processing of partial OpenGL commands;
the preprocessing unit is respectively connected with the simplified instruction set processor, the access bus arbitration unit and the register unit;
the reduced instruction set processor is connected with the instruction cache unit and the data cache unit;
the preprocessing unit is connected with the vertex cache unit and the vertex index cache unit;
the preprocessing unit further comprises three FIFO units; the FIFO units are respectively graph_cmd_fifo, new_list_fifo and call_list_fifo; the three FIFO units of the graph_cmd_fifo, the new_list_fifo and the call_list_fifo are respectively an OpenGL command FIFO, a display list loading FIFO and a display list calling FIFO;
the TLM device also comprises a plurality of processes, methods and sockets;
the process and the method are used for realizing command preprocessing, RISC processing, report interrupt, display list FIFO management, DMA processing from a host to a command processor, parameter initialization process from a state parameter management unit to a command processor module, exception processing method and register management process from the state parameter management unit to the command processor module;
the socket is used for realizing the interconnection communication function with an external module;
the vertex cache unit and the vertex index cache unit provide cache for vertex array commands;
the instruction cache unit and the data cache unit provide caches of instructions and data for the reduced instruction set processor.
2. The TLM device of a SysML view based GPU command processing module of claim 1, wherein: the processes include a pre_process_cthread process, a cmd_process_core_cthread process, a report_interrupt_method process, a list_fifo_message_cthread process, a hiu2cmd_dma_target_cthread process, a sgu2 cmd_parametric_target_cthread process, a sgu2cmd_graph_reg_target_cthread process;
the method comprises an outlide_acceptance_target_method method;
the sockets include a cmd2sgu _draw_initial_socket socket, a sgu _2cmd_resource_status_target_socket socket, a cmd2hiu _cfg_dma2c0_initial_socket socket, a cmd2hiu _cfg_dmac2 s0_initial_socket socket, a cmd2hiu _cfg_dma2c1_initial_socket socket, a cmd2hiu _cfg_dma2s1_initial_socket, a cmd2sgu _graph_functional_initial_socket, a sgu _Funcode_selectjsocket, a cmd2_plug socket, a wid2_ sgu _initial_socket vc2l2cache_initiator_socket, vic2l2cache_initiator_socket, cmd2axi0_initiator_socket, sgu2cmd_graph_reg_target_socket, cmd2hiu _excursions_irq_socket, usa2 cmd_excursions_status_socket, geu 2cmd_excursions_status_socket, jsu 2cmd_excursions_status_socket, sgu2cmd_paraminit_target_socket, sgu 2cmd_function_packet_destination_socket, hiu 2cmd_dma_socket.
3. A method of operating a TLM device based on a GPU command processing module for a sysplex view as defined in claim 1, wherein: the method comprises the following operation steps:
1) Creating CM package objects
1.1 Judging the cm_pkt_fifo state, if the cm_pkt_fifo state is empty, setting pre_process_busy to 0 and returning to the step 1); if cm_pkt_fifo is not empty, setting pre_process_busy to 1;
1.2 A read graphics command interface FIFO obtains a command packet header, sets an immittUnit, creates a CM packet object and stores command packet information into a linked list;
the execution unit is as follows: 0-a preprocessing unit; 1-a reduced instruction set processor execution;
2) Display list command loading
2.1 If newlist_flag is equal to 1 and the current command is glNewList, the operation is invalid, and the simulation is exited; if newlist_flag is equal to 1 and the current command is not glNewList, writing the current command into the display list FIFO directly;
2.2 Judging a display list mode, if the mode is COMPILE, directly returning to the step 1), and continuously judging the cm_pkt_fifo state; if the mode is GL_COMPILE_AND_EXECUTE, entering step 3);
3) Command package classification
3.1 If the command packet is a glArrayelement/glDrawelements/glLoadFirmWare/glNewList/glEndList/glCalllList command, entering a special command processing flow;
3.2 When the command packet is a glVertex/glMaterial/glNormal/glColor/glSecondaryColor/gltex code/glmultitetxcode/glfogcodond/glEdgeFlag/glVertex backup0/glVertex backup1/glVertex trie graphic drawing command, entering a drawing command processing flow, and uniformly transmitting to the SGU_GDU unit according to 160 bits wide;
3.3 If the command packet is other commands except the two commands, sending the command packet to the processor of the reduced instruction set for processing;
3.4 Returning to step 1) to continue reading OpenGL commands.
4. A method of operating a TLM device of a sysplm view based GPU command processing module as defined in claim 3, wherein: the processing method of the reduced instruction set processor in the step 3.3) comprises the following steps:
3.3.1 A risc _ enable signal is detected,
setting risc_core_busy=0 to 0 when risc_enable signal value is false and returning to step 3.3.1);
setting risc_core_busy=1 when risc_enable value is true and proceeding to step 3.3.2);
3.3.2 Analyzing the received command and carrying out striping treatment; configuring parameters carried by the command to a state parameter register, configuring and starting PCIe_DMA according to the data address and the size carried by the command, and issuing a function code in the graphic command to a lower-level pipeline unit of the 3D engine;
3.3.3 Returning to step 3.3.1) continuing to detect the risc _ enable signal.
5. A method of operating a TLM device of a sysplm view based GPU command processing module as defined in claim 4, wherein: the GPU command processing module also comprises interrupt processing work, and when an interrupt occurs, the steps are as follows:
step 1: reading the glGetError_reg1-glGetError_reg3 error state registers;
step 2: performing logic OR operation on the glGetError_reg1-glGetError_reg3 register values, and giving a result to cmd_acceptance_irq_socket;
step 3: and ending the exit.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002132489A (en) * | 2000-08-23 | 2002-05-10 | Nintendo Co Ltd | Graphics system |
| CN103838669A (en) * | 2012-11-26 | 2014-06-04 | 辉达公司 | System, method, and computer program product for debugging graphics programs locally |
| WO2015134941A1 (en) * | 2014-03-06 | 2015-09-11 | Graphite Systems, Inc. | Multiprocessor system with independent direct access to bulk solid state memory resources |
| CN111028132A (en) * | 2019-11-21 | 2020-04-17 | 中国航空工业集团公司西安航空计算技术研究所 | SystemC-based GPU command processor unit hardware TLM microstructure |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7397797B2 (en) * | 2002-12-13 | 2008-07-08 | Nvidia Corporation | Method and apparatus for performing network processing functions |
| US9569612B2 (en) * | 2013-03-14 | 2017-02-14 | Daniel Shawcross Wilkerson | Hard object: lightweight hardware enforcement of encapsulation, unforgeability, and transactionality |
| US10970238B2 (en) * | 2019-04-19 | 2021-04-06 | Intel Corporation | Non-posted write transactions for a computer bus |
-
2020
- 2020-12-24 CN CN202011542813.5A patent/CN112581585B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002132489A (en) * | 2000-08-23 | 2002-05-10 | Nintendo Co Ltd | Graphics system |
| CN103838669A (en) * | 2012-11-26 | 2014-06-04 | 辉达公司 | System, method, and computer program product for debugging graphics programs locally |
| WO2015134941A1 (en) * | 2014-03-06 | 2015-09-11 | Graphite Systems, Inc. | Multiprocessor system with independent direct access to bulk solid state memory resources |
| CN111028132A (en) * | 2019-11-21 | 2020-04-17 | 中国航空工业集团公司西安航空计算技术研究所 | SystemC-based GPU command processor unit hardware TLM microstructure |
Non-Patent Citations (2)
| Title |
|---|
| 基于OpenGL的GPU命令处理器设计方法研究;刘晖;田泽;张骏;马城城;;航空计算技术;20200525(03);全文 * |
| 基于SystemC的GPU参数分配单元硬件TLM建模;姜丽云;田泽;吴晓成;张骏;;信息通信;20200215(02);全文 * |
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