CN111045665B - UML-based GPU command processor - Google Patents
UML-based GPU command processor Download PDFInfo
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- CN111045665B CN111045665B CN201911147124.1A CN201911147124A CN111045665B CN 111045665 B CN111045665 B CN 111045665B CN 201911147124 A CN201911147124 A CN 201911147124A CN 111045665 B CN111045665 B CN 111045665B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/30—Creation or generation of source code
- G06F8/34—Graphical or visual programming
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to the technical field of computer hardware modeling, in particular to a UML-based GPU command processor unit, which comprises a structural view of the GPU command processor unit, an interface view of the GPU command processor unit and a behavior diagram of the GPU command processor unit; the structural view of the GPU command processor unit is used for describing the internal structure of the GPU command processor unit and the connection relation with other units; the interface diagram of the GPU command processor unit is used for describing a transaction-level interface of the GPU command processor unit; the behavior diagram of the GPU command processor unit is used for describing communication behaviors among substructures inside the GPU command processor unit. The invention provides a UML model for a GPU command processor unit, which can help system developers to better understand system architecture and functions, establish a more reliable and more complete system model and verify the feasibility of a hardware structure more efficiently.
Description
Technical Field
The invention relates to the technical field of computer hardware modeling, in particular to a GPU command processor unit based on UML.
Background
The UML (unified Modeling Language), also called as a unified Modeling Language, is a graphical Language supporting Modeling and software system development, and provides Modeling and visualization support for software development, and the UML can help designers to shorten design time, reduce improvement cost, and optimize software and hardware segmentation.
The GPU pipeline has high speed, parallel characteristics and flexible programmability, and provides a good operation platform for graphic processing and general parallel computing. At present, the GPU development capability in China is weak, and a large number of commercial GPU chips imported from abroad are adopted in display control systems in various fields. Particularly in the military field, the GPU chips imported from foreign countries and used for commercial use have hidden dangers in the aspects of safety, reliability, security and the like, and cannot meet the requirements of military environments; moreover, for political, military, economic reasons and the like, technology blocking and product monopoly are carried out in China abroad, and bottom technical data of the GPU chip, such as register data, detailed internal micro-architecture, core software source codes and the like, are difficult to obtain, so that the functions and the performances of the GPU cannot be fully exerted, and the portability is poor; the problems seriously restrict the independent development and autonomous development of the display system in China, break through the key technology of the graphics processor and develop the graphics processor chip at will.
Disclosure of Invention
Based on the problems in the background art, the UML-based GPU command processor provided by the invention can help system developers to better understand system architecture and functions through a hardware view model of a GPU fragment coloring task scheduling unit modeled by UML, establish a more reliable and complete system model, and can verify the feasibility of a hardware structure more efficiently.
The specific technical scheme of the invention is as follows:
the invention provides a UML-based GPU command processor unit, which comprises a structural view of the GPU command processor unit, an interface view of the GPU command processor unit and a behavior view of the GPU command processor unit; the structural view of the GPU command processor unit is used for describing the internal structure of the GPU command processor unit and the connection relation with other units; the interface diagram of the GPU command processor unit is used for describing a transaction-level interface of the GPU command processor unit; the behavior diagram of the GPU command processor unit is used for describing communication behaviors among substructures inside the GPU command processor unit.
The structural view of the GPU command processor unit, the interface diagram of the GPU command processor unit and the behavior diagram of the GPU command processor unit are all realized by modeling through UML language and a transaction-level modeling method.
Preferably, the structural view of the GPU command processor unit includes the following elements:
thread: cmd _ Main _ Thread and Cmd _ Dma _ Thread;
FIFO: graphCmdFifo, newListFifo, and callListFifo;
1 input port: pcie2CmdExport;
8 output ports: cmd2RomPort, cmd2AxiPort, vaCache2AxiPort, cmdCache2AxiPort, cmd2 PciiPort, cmd2SguGraphPort, cmd2SpmuPort and cmd2UsaPort.
Preferably, the interface diagram of the GPU command processor unit includes the following elements:
interface: inheriting Pceie 2Cmdif of an sc _ interface of SystemC;
the interface comprises a method Get _ Graph _ Command _ Service () for acquiring a graphics Command Service;
the interface comprises a method Put _ Graph _ Command () for issuing graphics commands to the Command handler.
Preferably, the behavior diagram of the GPU command processor unit includes a Main Thread Cmd _ Main _ Thread and a DMA Thread Cmd _ DMA _ Thread; the Main Thread Cmd _ Main _ Thread comprises a command processor Main Thread initialization, a graphic command FIFO empty state judgment and an OpenGL command processing routine execution; the DMA Thread Cmd _ DMA _ Thread includes a command processor DMA Thread to initialize, detect dmaEnable status, and resolve and process DMA operations.
Preferably, the Main Thread Cmd _ Main _ Thread specifically executes the following steps:
1) Setting cmdBusyStatus =0, notifying SGU, and executing 2);
2) Judging the graphCmdFifo state, and returning to 1 if the graphCmdFifo state is empty); if the graph CmdFifo is not empty, execute 3);
3) Executing an OpenGL command processing routine, comprising the steps of:
3.1 cmdBusyStatus =1;
3.2 Read OpenGL function codes in the graphics command FIFO;
3.3 Execute OpenGL command processing routines corresponding to OpenGL function codes;
3.4 cmdBusyStatus =0, back to 2).
Preferably, the DMA Thread Cmd _ DMA _ Thread specifically executes the following steps:
a) Set dmaBusyStatus =0, execute B);
b) Waiting and detecting dmaEnable, and if not 1, continuing waiting and detecting dmaEnable; if the number is 1, executing C);
c) Parsing and processing DMA operations, comprising the steps of:
a) Setting dmaBusyStatus =1;
b) Resolving dmaPath;
c) Performing a corresponding DMA operation according to the dmaPath;
d) Set dmaBusyStatus =1, return to step B).
The beneficial technical effects of the invention are as follows:
1. the invention provides a GPU-oriented command processor unit, which comprises: step 1: cmdBusyStatus =0 and notifies the SGU of the status; and 2, step: judging the graphCmdFifo state; and step 3: cmdBusyStatus =1 and notifies the SGU of the status; and 4, step 4: the Opengl processing routine Process _ Opengl _ Command () is executed.
2. The invention solves the problem of comparison of RTL simulation result models of the GPU command processor unit, solves the problem of function verification of the GPU command processor unit, and accelerates the simulation process.
The invention models the GPU command processor unit through UML language and transaction-level modeling method, and specifically comprises a structural view, an interface diagram and a unit internal behavior diagram of the GPU command processor unit.
The method can help system developers to better understand system architecture and functions, establish a more reliable and more complete system model, and can more efficiently verify the feasibility of a hardware structure.
Drawings
FIG. 1 is a structural view of a GPU command processor unit;
FIG. 2 is a GPU command processor unit interface diagram;
FIG. 3 is a diagram of GPU command processor unit host process behavior;
figure 4 is a diagram of GPU command processor unit DMA process behavior.
Detailed Description
The invention will now be described in detail with reference to the drawings attached hereto.
In an embodiment of the present invention, as shown in fig. 1 to 4, a UML-based GPU command processor unit is proposed, which is characterized in that: the method comprises the steps of obtaining a structural view of a GPU command processor unit, an interface view of the GPU command processor unit and a behavior view of the GPU command processor unit; the structural view of the GPU command processor unit is used for describing the internal structure of the GPU command processor unit and the connection relation with other units; the interface diagram of the GPU command processor unit is used for describing a transaction-level interface of the GPU command processor unit; the behavior diagram of the GPU command processor unit is used for describing communication behaviors among substructures inside the GPU command processor unit.
The structural view of the GPU command processor unit, the interface diagram of the GPU command processor unit and the behavior diagram of the GPU command processor unit are all realized by modeling through UML language and a transaction-level modeling method.
In one embodiment, as shown in FIG. 1, the structural view of the GPU command processor unit includes the following elements:
thread: cmd _ Main _ Thread and Cmd _ Dma _ Thread;
FIFO: graphCmdFifo, newListFifo, and callListFifo;
1 input port: pcie2CmdExport;
8 output ports: cmd2RomPort, cmd2AxiPort, vaCache2AxiPort, cmdCache2AxiPort, cmd2 PciiPort, cmd2SguGraphPort, cmd2SpmuPort and cmd2UsaPort.
In one embodiment, as shown in FIG. 2, the interface diagram of the GPU command processor unit includes the following elements:
interface: inheriting Pceie 2Cmdif of an sc _ interface of SystemC;
the interface comprises a method Get _ Graph _ Command _ Service (), and is used for acquiring a graphic Command Service;
the interface includes a method Put _ Graph _ Command () for issuing graphics commands to the Command handler.
In one embodiment, the behavior diagram of the GPU command processor unit includes a Main Thread Cmd _ Main _ Thread and a DMA Thread Cmd _ Dma _ Thread; the Main Thread Cmd _ Main _ Thread comprises a command processor Main Thread initialization, a graphic command FIFO empty state judgment and an OpenGL command processing routine execution; the DMA Thread Cmd _ DMA _ Thread includes a command processor DMA Thread to initialize, detect dmaEnable status, and resolve and process DMA operations.
In one embodiment, as shown in fig. 3, the Main Thread Cmd _ Main _ Thread specifically performs the following steps:
1) Setting cmdBusyStatus =0, notifying SGU, and executing 2);
2) Judging the graphCmdFifo state, and if the graphCmdFifo state is empty, returning to 1); if the graph CmdFifo is not empty, execute 3);
3) Executing an OpenGL command processing routine, comprising the steps of:
3.1 cmdBusyStatus =1;
3.2 Read OpenGL function codes in the graphics command FIFO;
3.3 Execute an OpenGL command processing routine corresponding to the OpenGL function code;
3.4 cmdBusyStatus =0, back to 2).
In one embodiment, as shown in fig. 4, the DMA Thread Cmd _ DMA _ Thread specifically performs the following steps:
a) Set dmaBusyStatus =0, execute B);
b) Waiting and detecting dmaEnable, and if not 1, continuing waiting and detecting dmaEnable; if the value is 1, executing C);
c) Resolving and processing DMA operations, comprising the steps of:
a) Setting dmaBusyStatus =1;
b) The dmaPath is parsed;
c) Performing a corresponding DMA operation according to the dmaPath;
d) Set dmaBusyStatus =1, return to step B).
Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art; the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (5)
1. A UML-based GPU command processor unit, comprising: the method comprises the steps of obtaining a structural view of a GPU command processor unit, an interface view of the GPU command processor unit and a behavior view of the GPU command processor unit; the structural view of the GPU command processor unit is used for describing the internal structure of the GPU command processor unit and the connection relation with other units; the interface diagram of the GPU command processor unit is used for describing a transaction-level interface of the GPU command processor unit; the behavior diagram of the GPU command processor unit is used for describing communication behaviors among substructures inside the GPU command processor unit;
the structural view of the GPU command processor unit, the interface diagram of the GPU command processor unit and the behavior diagram of the GPU command processor unit are all realized by modeling through UML language and a transaction-level modeling method;
the behavior diagram of the GPU command processor unit comprises a Main Thread Cmd _ Main _ Thread and a DMA Thread Cmd _ Dma _ Thread; the Main Thread Cmd _ Main _ Thread comprises a command processor Main Thread initialization, a graphic command FIFO empty state judgment and an OpenGL command processing routine execution; the DMA Thread Cmd _ DMA _ Thread includes a command processor DMA Thread to initialize, detect dmaEnable status, and resolve and process DMA operations.
2. A UML-based GPU command processor unit as claimed in claim 1, wherein: the structural view of the GPU command processor unit comprises the following elements:
thread: cmd _ Main _ Thread and Cmd _ Dma _ Thread;
FIFO: graphCmdFifo, newListFifo, and callListFifo;
1 input port: pcie2CmdExport;
8 output ports: cmd2RomPort, cmd2AxiPort, vaCache2AxiPort, cmdCache2AxiPort, cmd2 PciiPort, cmd2SguGraphPort, cmd2SpmuPort, and cmd2UsaPort.
3. A UML-based GPU command processor unit as claimed in claim 1, wherein: the interface diagram of the GPU command processor unit comprises the following elements:
interface: inheriting Pcel 2Cmdif of sc _ interface of SystemC;
the interface comprises a method Get _ Graph _ Command _ Service () for acquiring a graphics Command Service;
the interface comprises a method Put _ Graph _ Command () for issuing graphics commands to the Command handler.
4. A UML-based GPU command processor unit as claimed in claim 1, wherein:
the Main Thread Cmd _ Main _ Thread specifically comprises the following steps:
1) Setting cmdBusyStatus =0, notifying SGU, and executing 2);
2) Judging the graphCmdFifo state, and returning to 1 if the graphCmdFifo state is empty); if the graph CmdFifo is not empty, then execute 3);
3) Executing an OpenGL command processing routine, comprising the steps of:
3.1 cmdBusyStatus =1;
3.2 Read OpenGL function codes in the graphics command FIFO;
3.3 Execute OpenGL command processing routines corresponding to OpenGL function codes;
3.4 cmdBusyStatus =0, back to 2).
5. A UML-based GPU command processor unit as claimed in claim 1, wherein:
the DMA Thread Cmd _ Dma _ Thread specifically comprises the following steps:
a) Set dmaBusyStatus =0, execute B);
b) Waiting and detecting dmaEnable, and if not 1, continuing waiting and detecting dmaEnable; if the value is 1, executing C);
c) Resolving and processing DMA operations, comprising the steps of:
a) Set dmaBusyStatus =1;
b) The dmaPath is parsed;
c) Performing a corresponding DMA operation according to the dmaPath;
d) Set dmaBusyStatus =1, return to step B).
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| US20080074431A1 (en) * | 2003-11-19 | 2008-03-27 | Reuven Bakalash | Computing system capable of parallelizing the operation of multiple graphics processing units (GPUS) supported on external graphics cards |
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| CN109615685A (en) * | 2018-11-14 | 2019-04-12 | 西安翔腾微电子科技有限公司 | Method is executed towards the hardware view model and texture of GPU texture textures based on UML |
| CN109741235A (en) * | 2018-12-11 | 2019-05-10 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of host interface means and modeling method based on GPU chip |
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