CN112579282A

CN112579282A - Data processing method, device, system and computer readable storage medium

Info

Publication number: CN112579282A
Application number: CN201910948681.7A
Authority: CN
Inventors: 张帅
Original assignee: Beijing Jingdong Century Trading Co Ltd; Beijing Jingdong Shangke Information Technology Co Ltd
Current assignee: Beijing Jingdong Century Trading Co Ltd; Beijing Jingdong Shangke Information Technology Co Ltd
Priority date: 2019-09-30
Filing date: 2019-09-30
Publication date: 2021-03-30

Abstract

The present disclosure provides a data processing method, including: a method of data processing, comprising: receiving an access request; determining a target object to which the access request is directed based on the access request; determining an accessed state of the target object; determining a response mode for the access request based on the accessed state; when the response mode is determined to be the first response mode, acquiring the target object from the first storage unit; and when the response mode is determined to be the second response mode, at least the target object is acquired from the second storage unit, wherein the mode of acquiring the target object from the first storage unit is different from the mode of acquiring the target object from the second storage unit. The present disclosure also provides a data processing apparatus, a data processing system, and a computer-readable storage medium.

Description

Data processing method, device, system and computer readable storage medium

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a data processing method, a data processing apparatus, a data processing system, and a computer-readable storage medium.

Background

In internet applications, caching systems have been widely used. The data can be read and written quickly through the cache system, so that the performance of the system can be improved to a certain extent. Current cache systems include, for example, redis, memcache, and the like. The cache system mostly adopts the fragmentation to store data, and the data can be accessed on the corresponding fragmentation when the data is read and written. In practical applications, especially during peak periods of data access, there is usually a large amount of access to the data, even hot spot data that is frequently accessed.

In the process of implementing the concept of the present disclosure, the inventor finds that in the prior art, at least the following problems exist, in the related art, when a large amount of data is accessed, a huge pressure is generally exerted on a cache server in a background, and meanwhile, since the cached data is generally stored in a byte array, most of the cached data needs to be subjected to a reverse-sequencing process, a large amount of server computing resources are consumed, and the overall performance and the user experience of the system are further affected.

Disclosure of Invention

In view of the above, the present disclosure provides an optimized data processing method, data processing apparatus, data processing system, and computer readable storage medium.

One aspect of the present disclosure provides a data processing method, including: the method comprises the steps of receiving an access request, determining a target object to which the access request aims based on the access request, determining an accessed state of the target object, and determining a response mode aiming at the access request based on the accessed state. When the response mode is determined to be a first response mode, the target object is acquired from a first storage unit, and when the response mode is determined to be a second response mode, at least the target object is acquired from a second storage unit, wherein the manner of acquiring the target object from the first storage unit is different from the manner of acquiring the target object from the second storage unit.

According to the embodiment of the disclosure, a target object can be accessed by a plurality of threads; the determining the accessed state of the target object comprises: determining at least one target thread in the plurality of threads, wherein the at least one target thread is a thread currently accessing the target object, and determining an accessed state of the target object, wherein the accessed state represents a state that the target object is accessed by the at least one target thread.

According to the embodiment of the present disclosure, when a plurality of target threads are included, the determining a response mode for the access request includes: determining that a response mode for a first target thread is the first response mode, the first thread is a target thread which accesses the target object first in the target threads, and determining that a response mode for a second target thread is the second response mode, the second thread is a target thread except the first target thread in the target threads.

According to the embodiment of the present disclosure, when a target thread is included, the determining a response mode for the access request includes: determining an access order of the target thread to access the target object, determining a response mode aiming at a first access order as the first response mode, wherein the first access order represents that the target thread accesses the target object for the first time, and determining a response mode aiming at a second access order as the second response mode, wherein the second access order is an access order of the target thread except the first access order.

According to an embodiment of the present disclosure, acquiring at least the target object from the second storage unit includes: and acquiring initial data from the second storage unit, and performing deserialization processing on the initial data to obtain the target object.

According to an embodiment of the present disclosure, acquiring at least the target object from the second storage unit includes: determining attribute information of the target object, dividing the target object into static data and dynamic data based on the attribute information of the target object, acquiring the static data from the first storage unit, acquiring the dynamic data from the second storage unit, and performing deserialization processing on the dynamic data.

According to an embodiment of the present disclosure, the first storage unit includes a memory unit, and the second storage unit includes a cache unit.

Another aspect of the present disclosure provides a data processing apparatus including: the device comprises a receiving module, a first determining module, a second determining module and a third determining module. The receiving module receives an access request, the first determining module determines a target object to which the access request aims based on the access request, the second determining module determines the accessed state of the target object, and the third determining module determines a response mode aiming at the access request based on the accessed state. When the response mode is determined to be a first response mode, the target object is acquired from a first storage unit, and when the response mode is determined to be a second response mode, at least the target object is acquired from a second storage unit, wherein the manner of acquiring the target object from the first storage unit is different from the manner of acquiring the target object from the second storage unit.

According to the embodiment of the disclosure, a target object can be accessed by a plurality of threads; the determining the accessed state of the target object comprises: determining at least one target thread in the plurality of threads, wherein the at least one target thread is a thread which currently accesses the target object, and determining an accessed state of the target object, wherein the accessed state represents a state that the target object is accessed by the at least one target thread.

According to the embodiment of the present disclosure, when a plurality of target threads are included, the third determining module includes: a first determination submodule and a second determination submodule. The first determining submodule determines that a response mode for a first target thread is the first response mode, the first thread is a target thread which accesses the target object first in the target threads, and the second determining submodule determines that a response mode for a second target thread is the second response mode, the second thread is a target thread except the first target thread in the target threads.

According to an embodiment of the present disclosure, when a target thread is included, the third determining module includes: a third determination submodule, a fourth determination submodule, and a fifth determination submodule. The third determining submodule determines an access order of the target thread to access the target object, the fourth determining submodule determines a response mode for a first access order to be the first response mode, the first access order represents that the target thread accesses the target object for the first time, and the fifth determining submodule determines a response mode for a second access order to be the second response mode, wherein the second access order is an access order of the target thread except the first access order.

Another aspect of the present disclosure provides a computer-readable storage medium storing computer-executable instructions for implementing the method as described above when executed.

Another aspect of the disclosure provides a computer program comprising computer executable instructions for implementing the method as described above when executed.

According to the embodiment of the disclosure, the problems that in the related art, when a large amount of data are accessed, huge pressure is generally caused to a cache server at a background, and meanwhile, since the cached data are generally stored in byte arrays and mostly need to be processed in a reverse order, a large amount of server computing resources are consumed, and further the overall performance and the user experience of a system are affected can be solved, and therefore, the technical effects of relieving the pressure of the server and improving the data access efficiency can be achieved.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

FIG. 1 schematically illustrates a system architecture of a data processing method and a data processing system according to an embodiment of the present disclosure;

FIG. 2 schematically shows a flow chart of a data processing method according to an embodiment of the present disclosure;

FIG. 3 schematically illustrates a flow chart for determining a manner of response in accordance with an embodiment of the present disclosure;

FIG. 4 schematically illustrates a flow chart for determining a response mode according to another embodiment of the present disclosure;

FIG. 5 schematically shows a block diagram of a data processing apparatus according to an embodiment of the present disclosure;

FIG. 6 schematically shows a block diagram of a third determination module according to an embodiment of the present disclosure;

FIG. 7 schematically illustrates a block diagram of a third determination module according to another embodiment of the present disclosure; and

FIG. 8 schematically shows a block diagram of a computer system suitable for data processing according to an embodiment of the present disclosure.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The terms "comprises," "comprising," and the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.

All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It is noted that the terms used herein should be interpreted as having a meaning that is consistent with the context of this specification and should not be interpreted in an idealized or overly formal sense.

Where a convention analogous to "at least one of A, B and C, etc." is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., "a system having at least one of A, B and C" would include but not be limited to systems that have a alone, B alone, C alone, a and B together, a and C together, B and C together, and/or A, B, C together, etc.). Where a convention analogous to "A, B or at least one of C, etc." is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., "a system having at least one of A, B or C" would include but not be limited to systems that have a alone, B alone, C alone, a and B together, a and C together, B and C together, and/or A, B, C together, etc.).

An embodiment of the present disclosure provides a data processing method, including: and receiving an access request, and determining a target object to which the access request aims based on the access request. Then, an accessed state of the target object is determined. Finally, based on the accessed state, a response mode for the access request is determined. And when the response mode is determined to be the first response mode, the target object is acquired from the first storage unit, and when the response mode is determined to be the second response mode, the target object is acquired from at least the second storage unit, wherein the mode of acquiring the target object from the first storage unit is different from the mode of acquiring the target object from the second storage unit.

Fig. 1 schematically shows a system architecture of a data processing method and a data processing system according to an embodiment of the present disclosure. It should be noted that fig. 1 is only an example of a system architecture to which the embodiments of the present disclosure may be applied to help those skilled in the art understand the technical content of the present disclosure, and does not mean that the embodiments of the present disclosure may not be applied to other devices, systems, environments or scenarios.

As shown in fig. 1, the system architecture 100 according to this embodiment may include

terminal devices

101, 102, 103, a network 104 and a server 105. The network 104 serves as a medium for providing communication links between the

terminal devices

101, 102, 103 and the server 105. Network 104 may include various connection types, such as wired, wireless communication links, or fiber optic cables, to name a few.

The user may use the

terminal devices

101, 102, 103 to interact with the server 105 via the network 104 to receive or send messages or the like. The

terminal devices

101, 102, 103 may have installed thereon various communication client applications, such as shopping-like applications, web browser applications, search-like applications, instant messaging tools, mailbox clients, social platform software, etc. (by way of example only).

The

terminal devices

101, 102, 103 may be various electronic devices having a display screen and supporting web browsing, including but not limited to smart phones, tablet computers, laptop portable computers, desktop computers, and the like.

The server 105 may be a server providing various services, such as a background management server (for example only) providing support for websites browsed by users using the

terminal devices

101, 102, 103. The background management server may analyze and perform other processing on the received data such as the user request, and feed back a processing result (e.g., a webpage, information, or data obtained or generated according to the user request) to the terminal device.

It should be noted that the data processing method provided by the embodiment of the present disclosure may be generally executed by the server 105. Accordingly, the data processing apparatus provided by the embodiments of the present disclosure may be generally disposed in the server 105. The data processing method provided by the embodiment of the present disclosure may also be executed by a server or a server cluster different from the server 105 and capable of communicating with the

terminal devices

101, 102, 103 and/or the server 105. Accordingly, the data processing apparatus provided by the embodiment of the present disclosure may also be disposed in a server or a server cluster different from the server 105 and capable of communicating with the

terminal devices

101, 102, 103 and/or the server 105.

For example, the access request acquired by the embodiment of the present disclosure may be stored in the

terminal devices

101, 102, 103, and the access request is transmitted to the server 105 through the

terminal devices

101, 102, 103, the server 105 may determine the target object to which the access request is directed and determine the accessed state of the target object based on the access request, and determine the response mode for the access request based on the accessed state, or the

terminal devices

101, 102, 103 may determine the target object to which the access request is directed and determine the accessed state of the target object based directly on the access request, and determine the response mode for the access request based on the accessed state. In addition, the access request may also be directly stored in the server 105, and the server 105 determines the target object to which the access request is directed and determines the accessed state of the target object directly based on the access request, and determines the response mode for the access request based on the accessed state.

It should be understood that the number of terminal devices, networks, and servers in fig. 1 is merely illustrative. There may be any number of terminal devices, networks, and servers, as desired for implementation.

Fig. 2 schematically shows a flow chart of a data processing method according to an embodiment of the present disclosure.

As shown in fig. 2, the method includes operations S210 to S240.

In operation S210, an access request is received.

According to embodiments of the present disclosure, data is typically stored in a storage system. The storage system may be, for example, a cache system or a memory system. After the storage system receives an access request from the outside, the storage system may respond to the access request and provide corresponding data.

In operation S220, based on the access request, a target object to which the access request is directed is determined.

In the embodiment of the present disclosure, the access request has, for example, an object identifier of a target object to be accessed, and after receiving the access request, the storage system may determine, based on the object identifier, the target object to which the access request is directed.

In operation S230, an accessed state of the target object is determined.

According to embodiments of the present disclosure, for example, a target object can be accessed by multiple threads. First, at least one target thread of the plurality of threads is determined, and second, an accessed state of the target object is determined, the accessed state representing a state in which the target object is accessed by the at least one target thread.

The access state includes, for example, the number of target threads accessing the target object, the access order, and the like. Based on the access status, a response mode for the access request may be determined.

In operation S240, a response manner to the access request is determined based on the accessed state.

And when the response mode is determined to be the first response mode, acquiring the target object from the first storage unit. And when the response mode is determined to be the second response mode, at least the target object is acquired from the second storage unit. In other words, the second response mode may include acquiring the target object from the second storage unit, or acquiring the target object from the first storage unit and the second storage unit.

According to an embodiment of the present disclosure, the first storage unit includes a memory unit, and the second storage unit includes a cache unit. According to the embodiment of the present disclosure, the manner of acquiring the target object from the first storage unit is different from the manner of acquiring the target object from the second storage unit.

For example, the target object may be directly obtained from the memory unit, in other words, the initial data is stored in the memory unit after being deserialized in advance, for example.

For example, retrieving at least the target object from the second storage unit includes: and acquiring initial data from the second storage unit, and performing deserialization processing on the initial data to obtain the target object. That is, the initial data is directly stored in the cache unit, and when the target object is obtained from the cache unit, the initial object in the cache unit needs to be deserialized to obtain the required target object.

According to the method and the device, the response mode is determined according to the accessed state of the target object, when the response mode is the first response mode, the target object can be directly obtained from the first storage unit, deserialization processing is not needed, the data access efficiency is improved, the calculation pressure of the server can be reduced without deserialization processing, and the system performance of the server is improved. When the response mode is the second response mode, the target object may be acquired from the second storage unit. According to the scheme, the target object is selectively acquired from the first storage unit or the second storage unit through different response modes, and the pressure of the first storage unit or the second storage unit is reduced.

According to an embodiment of the present disclosure, the operation S240 described above includes, for example, the following descriptions of fig. 3 and 4.

Fig. 3 schematically illustrates a flow chart for determining a response mode according to an embodiment of the present disclosure.

As shown in FIG. 3, when a plurality of target threads are included, the above operation S240 includes S241a to S242 a.

In operation S241a, it is determined that the response mode for the first target thread is the first response mode, and the first target thread is a target thread that accesses the target object first among the plurality of target threads.

According to the embodiment of the disclosure, when a plurality of target threads access a target object, the target thread accessed first is determined to be a first target thread, and the target object is obtained from a memory unit.

In operation S242a, it is determined that the response mode for the second target thread is the second response mode, and the second target thread is a target thread other than the first target thread among the plurality of target threads. For example, a target thread other than the first target thread among the plurality of target threads is determined as the second target thread, and the target object may be acquired from the cache unit. The second target thread acquires the target object from the cache unit because the first target thread acquires the target object from the memory unit first and the first target thread may have performed modification operation on the target object in the memory unit, so that the second target thread acquires the target object from the cache unit and the accuracy of the acquired target object is ensured.

Specifically, when a plurality of target threads acquire a target object at the same time, the number of times that the target object is referred to can be calculated by reference counting, which is mainly reflected on a spatial level (multiple target threads access at the same time). For example, when each of the plurality of target threads performs business logic processing, the reference count of the target object is increased by 1, and when the execution is completed, the reference count of the target object is decreased by 1. The object identifier and the reference count of the target object may be stored in the memory unit in an associated manner.

The reference count can reflect the current condition that the target object is accessed by the target thread, so that whether the current target thread is the thread accessed first can be determined through the reference count of the target object, and the response mode of the target thread can be conveniently determined.

Fig. 4 schematically illustrates a flow chart of a manner of determining a response according to another embodiment of the present disclosure.

As shown in FIG. 4, when a target thread is included, the operation S240 may further include S241 b-S242 b.

In operation S241b, an access order in which the target thread accesses the target object is determined.

According to the embodiment of the disclosure, when one target thread accesses a target object, the target thread may access the target object multiple times. Thus, the access order in which the target thread accesses the target object may be determined first.

In operation S242b, it is determined that the response mode for the first access order is the first response mode, and the first access order indicates that the target thread accessed the target object for the first time.

For example, when the target thread accesses the target object for the first time, the target object is obtained from the memory unit.

In operation S243b, it is determined that the response mode for the second access order is the second response mode, and the second access order is an access order of the target thread other than the first access order.

For example, when the target thread accesses the target object from the cache location for a subsequent access, except for the first access. The reason why the target object is obtained from the cache unit by the subsequent accesses except the first access is that the target thread may have performed a modification operation on the target object in the memory unit at the time of the first access, and therefore the subsequent accesses except the first access obtain the target object from the cache unit to ensure the accuracy of the obtained target object.

Specifically, when one target thread accesses the target object multiple times, the number of times that the target object is referenced can be calculated through reference counting, which is mainly reflected on a time level (one target thread accesses at different times). For example, the reference count of the target object is increased by 1 every time the target thread performs the business logic processing, and is decreased by 1 when the execution is completed. The object identifier and the reference count of the target object may be stored in the memory unit in an associated manner.

The reference count can reflect the number of times that the target object is currently accessed by the target thread, so that whether the current access of the target thread is the first access can be determined through the reference count of the target object, and a response mode can be determined conveniently according to the number of times that the target thread is accessed.

According to an embodiment of the present disclosure, acquiring at least the target object from the second storage unit includes: the target object is acquired from the second storage unit, or the target object is acquired from the first storage unit and the second storage unit. Specifically, the following steps (1) to (4) may be included:

(1) attribute information of the target object is determined.

According to an embodiment of the present disclosure, the target object may, for example, comprise a plurality of sub-objects, each sub-object having, for example, corresponding attribute information.

(2) The target object is divided into static data and dynamic data based on the attribute information of the target object.

For example, the plurality of sub-objects are divided into static data and dynamic data according to the attribute information. For example, the target object includes sub-object 1, sub-object 2, and sub-object 3. The attribute information of the sub-object 1 and the sub-object 2 is first attribute information, which for example characterizes the sub-object 1 and the sub-object 2 as style data, wherein the style data is for example data that does not need to be modified or updated in real time. The attribute information of the sub-object 3 is, for example, second attribute information, and the second attribute information, for example, represents that the sub-object 3 is data that needs to be modified or updated in real time. Thus, sub-object 1 and sub-object 2 may be divided into static data and sub-object 3 may be divided into dynamic data. The static data may be stored in the memory unit, and the dynamic data may be stored in the cache unit.

(3) Static data is retrieved from a first storage unit.

(4) And acquiring the dynamic data from the second storage unit, and performing deserialization processing on the dynamic data.

According to the embodiment of the present disclosure, the target object read from the memory unit may be first reset (the resetting includes, for example, changing data into data before modification), and then the target object may be split statically and statically according to the attribute information, where the splitting mainly aims to reduce deserialization. Specifically, whether the target object needs to be deserialized or not can be judged based on the reference count of the target object, and if the target object needs to be deserialized, the static data and the dynamic data can be obtained by further performing dynamic and static splitting on the target object, so that the dynamic data can be deserialized in a targeted manner. Static data can directly read the object in the memory unit because no change exists.

In the embodiment of the present disclosure, the target object may be preferentially read from the memory unit, and considering that the target object in the memory unit may have a change, the distributed coordination service may be utilized to monitor the change of the external object, so as to update the data in the memory unit in real time, and update the data in the cache unit synchronously. In addition, the data stored in the memory unit may originate from multiple system platforms, and the change mechanism may not be uniform, so that the data of each data source type can be managed separately, that is, the memory unit performs fine-grained management according to the data source type.

According to the embodiment of the disclosure, the data in the memory unit is guaranteed to be updated accurately and reliably by preferentially reading the data in the memory unit. By carrying out dynamic and static splitting on the target object, the deserialization processing is reduced, and the computing resource is saved.

Fig. 5 schematically shows a block diagram of a data processing apparatus according to an embodiment of the present disclosure.

As shown in fig. 5, the data processing apparatus 500 includes a receiving module 510, a first determining module 520, a second determining module 530, and a third determining module 540.

The receiving module 510 may be used to receive an access request. According to the embodiment of the present disclosure, the receiving module 510 may perform, for example, the operation S210 described above with reference to fig. 2, which is not described herein again.

The first determination module 520 may be configured to determine a target object for which the access request is directed based on the access request. According to the embodiment of the present disclosure, the first determining module 520 may perform, for example, operation S220 described above with reference to fig. 2, which is not described herein again.

The second determination module 530 may be used to determine the accessed state of the target object.

According to the embodiment of the disclosure, a target object can be accessed by a plurality of threads; determining the accessed state of the target object comprises: determining at least one target thread in the plurality of threads, wherein the at least one target thread is a thread currently accessing the target object, and determining the accessed state of the target object, wherein the accessed state represents the state of the target object accessed by the at least one target thread.

According to an embodiment of the present disclosure, the second determining module 530 may perform, for example, the operation S230 described above with reference to fig. 2, which is not described herein again.

The third determining module 540 may be configured to determine a response mode for the access request based on the accessed state.

According to the embodiment of the present disclosure, when the response mode is determined to be the first response mode, the target object is acquired from the first storage unit, and when the response mode is determined to be the second response mode, the target object is acquired at least from the second storage unit, wherein the manner of acquiring the target object from the first storage unit is different from the manner of acquiring the target object from the second storage unit.

According to an embodiment of the present disclosure, the third determining module 540 may, for example, perform operation S240 described above with reference to fig. 2, which is not described herein again.

FIG. 6 schematically shows a block diagram of a third determination module according to an embodiment of the disclosure.

As shown in fig. 6, when multiple target threads are included, the third determination module 540 may include a first determination submodule 541a and a second determination submodule 542 a.

The first determining sub-module 541a may be configured to determine that a response mode for the first target thread is a first response mode, where the first thread is a target thread that accesses the target object first among the plurality of target threads. According to the embodiment of the present disclosure, the first determining submodule 541a may perform, for example, the operation S241a described above with reference to fig. 3, which is not described herein again.

The second determining submodule 542a may be configured to determine that a response mode for a second target thread is a second response mode, where the second thread is a target thread other than the first target thread in the plurality of target threads. According to the embodiment of the present disclosure, the second determining submodule 542a may perform, for example, the operation S242a described above with reference to fig. 3, which is not described herein again.

Fig. 7 schematically illustrates a block diagram of a third determination module according to another embodiment of the present disclosure.

As shown in fig. 7, when one target thread is included, the third determination module 540 may include a third determination submodule 541b, a fourth determination submodule 542b, and a fifth determination submodule 543 b.

The third determination submodule 541b may be configured to determine an access order in which the target thread accesses the target object. According to the embodiment of the present disclosure, the third determining submodule 541b may perform, for example, the operation S241b described above with reference to fig. 4, which is not described herein again.

The fourth determining submodule 542b may be configured to determine that the response mode for the first access order is the first response mode, and the first access order indicates that the target thread accesses the target object for the first time. According to the embodiment of the present disclosure, the fourth determining submodule 542b may perform, for example, the operation S242b described above with reference to fig. 4, which is not described herein again.

The fifth determining sub-module 543b may be configured to determine that the response mode for the second accessing order is the second response mode, and the second accessing order is the accessing order of the target thread except the first accessing order. According to the embodiment of the present disclosure, the fifth determining sub-module 543b may perform, for example, operation S243b described above with reference to fig. 4, which is not described herein again.

Any number of modules, sub-modules, units, sub-units, or at least part of the functionality of any number thereof according to embodiments of the present disclosure may be implemented in one module. Any one or more of the modules, sub-modules, units, and sub-units according to the embodiments of the present disclosure may be implemented by being split into a plurality of modules. Any one or more of the modules, sub-modules, units, sub-units according to embodiments of the present disclosure may be implemented at least in part as a hardware circuit, such as a Field Programmable Gate Array (FPGA), a Programmable Logic Array (PLA), a system on a chip, a system on a substrate, a system on a package, an Application Specific Integrated Circuit (ASIC), or may be implemented in any other reasonable manner of hardware or firmware by integrating or packaging a circuit, or in any one of or a suitable combination of software, hardware, and firmware implementations. Alternatively, one or more of the modules, sub-modules, units, sub-units according to embodiments of the disclosure may be at least partially implemented as a computer program module, which when executed may perform the corresponding functions.

For example, any number of the receiving module 510, the first determining module 520, the second determining module 530, the third determining module 540, the first determining sub-module 541a, the second determining sub-module 542a, the third determining sub-module 541b, the fourth determining sub-module 542b, and the fifth determining sub-module 543b may be combined into one module to be implemented, or any one of the modules may be split into a plurality of modules. Alternatively, at least part of the functionality of one or more of these modules may be combined with at least part of the functionality of the other modules and implemented in one module. According to an embodiment of the present disclosure, at least one of the receiving module 510, the first determining module 520, the second determining module 530, the third determining module 540, the first determining submodule 541a, the second determining submodule 542a, the third determining submodule 541b, the fourth determining submodule 542b, and the fifth determining submodule 543b may be implemented at least partially as a hardware circuit, such as a Field Programmable Gate Array (FPGA), a Programmable Logic Array (PLA), a system on a chip, a system on a substrate, a system on a package, an Application Specific Integrated Circuit (ASIC), or may be implemented by hardware or firmware such as any other reasonable manner of integrating or packaging a circuit, or implemented by any one of three implementations of software, hardware, and firmware, or by a suitable combination of any of them. Alternatively, at least one of the receiving module 510, the first determining module 520, the second determining module 530 and the third determining module 540, the first determining sub-module 541a, the second determining sub-module 542a, the third determining sub-module 541b, the fourth determining sub-module 542b and the fifth determining sub-module 543b may be at least partly implemented as a computer program module which, when executed, may perform a corresponding function.

FIG. 8 schematically shows a block diagram of a computer system suitable for data processing according to an embodiment of the present disclosure. The computer system illustrated in FIG. 8 is only one example and should not impose any limitations on the scope of use or functionality of embodiments of the disclosure.

As shown in fig. 8, a computer system 800 according to an embodiment of the present disclosure includes a processor 801 that can perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM)802 or a program loaded from a storage section 808 into a Random Access Memory (RAM) 803. The processor 801 may include, for example, a general purpose microprocessor (e.g., a CPU), an instruction set processor and/or associated chipset, and/or a special purpose microprocessor (e.g., an Application Specific Integrated Circuit (ASIC)), among others. The processor 801 may also include onboard memory for caching purposes. The processor 801 may include a single processing unit or multiple processing units for performing different actions of the method flows according to embodiments of the present disclosure.

In the RAM 803, various programs and data necessary for the operation of the system 800 are stored. The processor 801, the ROM 802, and the RAM 803 are connected to each other by a bus 804. The processor 801 performs various operations of the method flows according to the embodiments of the present disclosure by executing programs in the ROM 802 and/or RAM 803. Note that the programs may also be stored in one or more memories other than the ROM 802 and RAM 803. The processor 801 may also perform various operations of method flows according to embodiments of the present disclosure by executing programs stored in the one or more memories.

System 800 may also include an input/output (I/O) interface 805, also connected to bus 804, according to an embodiment of the disclosure. The system 800 may also include one or more of the following components connected to the I/O interface 805: an input portion 806 including a keyboard, a mouse, and the like; an output section 807 including a signal such as a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and the like, and a speaker; a storage portion 808 including a hard disk and the like; and a communication section 809 including a network interface card such as a LAN card, a modem, or the like. The communication section 809 performs communication processing via a network such as the internet. A drive 810 is also connected to the I/O interface 805 as necessary. A removable medium 811 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 810 as necessary, so that a computer program read out therefrom is mounted on the storage section 808 as necessary.

According to embodiments of the present disclosure, method flows according to embodiments of the present disclosure may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable storage medium, the computer program containing program code for performing the method illustrated by the flow chart. In such an embodiment, the computer program can be downloaded and installed from a network through the communication section 809 and/or installed from the removable medium 811. The computer program, when executed by the processor 801, performs the above-described functions defined in the system of the embodiments of the present disclosure. The systems, devices, apparatuses, modules, units, etc. described above may be implemented by computer program modules according to embodiments of the present disclosure.

The present disclosure also provides a computer-readable storage medium, which may be contained in the apparatus/device/system described in the above embodiments; or may exist separately and not be assembled into the device/apparatus/system. The computer-readable storage medium carries one or more programs which, when executed, implement the method according to an embodiment of the disclosure.

According to embodiments of the present disclosure, the computer-readable storage medium may be a computer-non-volatile computer-readable storage medium, which may include, for example and without limitation: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present disclosure, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

For example, according to embodiments of the present disclosure, a computer-readable storage medium may include the ROM 802 and/or RAM 803 described above and/or one or more memories other than the ROM 802 and RAM 803.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Those skilled in the art will appreciate that various combinations and/or combinations of features recited in the various embodiments and/or claims of the present disclosure can be made, even if such combinations or combinations are not expressly recited in the present disclosure. In particular, various combinations and/or combinations of the features recited in the various embodiments and/or claims of the present disclosure may be made without departing from the spirit or teaching of the present disclosure. All such combinations and/or associations are within the scope of the present disclosure.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims

1. A method of data processing, comprising:

receiving an access request;

determining a target object to which the access request is directed based on the access request;

determining an accessed state of the target object; and

determining a response mode for the access request based on the accessed state;

when the response mode is determined to be a first response mode, acquiring the target object from a first storage unit;

when it is determined that the response mode is the second response mode, acquiring at least the target object from a second storage unit,

wherein the target object is acquired from the first storage unit in a different manner than the target object is acquired from the second storage unit.

2. The method of claim 1, wherein the target object is accessible by a plurality of threads; the determining the accessed state of the target object comprises:

determining at least one target thread of the plurality of threads; and

determining an accessed state of the target object, the accessed state representing a state in which the target object is accessed by the at least one target thread.

3. The method of claim 2, wherein, when multiple target threads are included, the determining a manner of response to the access request comprises:

determining that a response mode for a first target thread is the first response mode, wherein the first target thread is a target thread which accesses the target object first in the plurality of target threads; and

and determining that a response mode aiming at a second target thread is the second response mode, wherein the second target thread is a target thread except the first target thread in the plurality of target threads.

4. The method of claim 2 or 3, wherein, when a target thread is included, said determining a response mode for the access request comprises:

determining an access order of the target thread to access the target object;

determining a response mode aiming at a first access sequence as the first response mode, wherein the first access sequence represents that the target thread accesses the target object for the first time; and

determining that a response mode for a second access order is the second response mode, the second access order being an access order of the target thread other than the first access order.

5. The method of claim 1, wherein said retrieving at least the target object from a second storage unit comprises:

acquiring initial data from the second storage unit; and

and performing deserialization processing on the initial data to obtain the target object.

6. The method of claim 1, wherein said retrieving at least the target object from a second storage unit comprises:

determining attribute information of the target object;

dividing the target object into static data and dynamic data based on the attribute information of the target object;

acquiring the static data from the first storage unit; and

and acquiring the dynamic data from the second storage unit, and performing deserialization processing on the dynamic data.

7. The method of claim 1, wherein the first storage unit comprises a memory unit and the second storage unit comprises a cache unit.

8. A data processing apparatus comprising:

the receiving module receives an access request;

a first determination module that determines, based on the access request, a target object to which the access request is directed;

a second determination module that determines an accessed state of the target object; and

a third determining module, configured to determine a response mode for the access request based on the accessed state;

9. A data processing system comprising:

one or more processors;

a memory for storing one or more programs,

wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the method of any of claims 1-7.

10. A computer-readable storage medium storing computer-executable instructions for implementing the method of any one of claims 1 to 7 when executed.