CN112564634A - Front-end reading circuit applied to radiation detector - Google Patents

Front-end reading circuit applied to radiation detector Download PDF

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Publication number
CN112564634A
CN112564634A CN202011393943.7A CN202011393943A CN112564634A CN 112564634 A CN112564634 A CN 112564634A CN 202011393943 A CN202011393943 A CN 202011393943A CN 112564634 A CN112564634 A CN 112564634A
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pmos
preamplifier
transistor
nmos transistor
capacitor
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Inventor
赵汝法
唐晓斌
张定冬
王巍
樊琦
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Chongqing Zhongyi Zhixin Technology Co ltd
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Chongqing Zhongyi Zhixin Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01T—MEASUREMENT OF NUCLEAR OR X-RADIATION
    • G01T1/00—Measuring X-radiation, gamma radiation, corpuscular radiation, or cosmic radiation
    • G01T1/16—Measuring radiation intensity
    • G01T1/161—Applications in the field of nuclear medicine, e.g. in vivo counting
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01T—MEASUREMENT OF NUCLEAR OR X-RADIATION
    • G01T1/00—Measuring X-radiation, gamma radiation, corpuscular radiation, or cosmic radiation
    • G01T1/16—Measuring radiation intensity
    • G01T1/17—Circuit arrangements not adapted to a particular type of detector
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01T—MEASUREMENT OF NUCLEAR OR X-RADIATION
    • G01T1/00—Measuring X-radiation, gamma radiation, corpuscular radiation, or cosmic radiation
    • G01T1/36—Measuring spectral distribution of X-rays or of nuclear radiation spectrometry
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers

Abstract

The invention relates to a front-end reading circuit applied to a radiation detector, belonging to the technical field of microelectronics, and comprising a preamplifier, a zero-pole eliminating circuit and a shaper; the signal from the detector enters the preamplifier from the input port, the output end of the preamplifier is connected with the input end of the zero-pole elimination circuit, the output end of the zero-pole elimination circuit is connected with the input end of the shaper, and the output end of the shaper outputs a voltage signal. The invention comprises a preamplifier, a pole-zero elimination circuit and a shaper, wherein the preamplifier is used for amplifying charge signals output by a detector, the pole-zero elimination circuit is used for reducing the time constant of exponential decay signals and eliminating undershoot of output signals, the shaper is used for filtering noise and adjusting waveforms, and the output waveforms are improved through the pole-zero elimination circuit, so that the front-end reading of the signals of the radiation detector is realized.

Description

Front-end reading circuit applied to radiation detector
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a front-end reading circuit applied to a radiation detector.
Background
Aiming at three major factors of doctors, patients and focuses in the field of medical image diagnosis, the cadmium zinc telluride multi-energy spectrum detector has ultralow radiation dose, hyperfine physical resolution and revolutionary energy spectrum analysis capability, and has essential improvement on the overall performance of the existing diagnosis system product. In order to fully exert the advantages of the cadmium zinc telluride multi-energy spectrum detector, the cadmium zinc telluride multi-energy spectrum detector is applied to radiation imaging.
A conventional sensing circuit is shown in fig. 1. The charge signal output by the detector is converted into a voltage signal through a preamplifier, and then the voltage signal is filtered by a shaper to filter noise and adjust the waveform. Since the design scheme belongs to a cascade system, the respective zero poles of the preamplifier and the shaper influence each other when the whole system outputs. The conventional readout circuit shapes the output waveform as shown in fig. 2. With the same charge signal input, successive inputs result in a stack of signals, reflected in the figure, and the baseline drifts, in order that the amplitudes of the shaped output waveforms are different.
Therefore, there is a need for a technical solution to reduce or eliminate the mutual influence of the zero-poles of the preamplifier and the shaper in the system, and improve the quality of the output waveform, mainly in terms of the amplitude of the output waveform and the stability of the baseline.
Disclosure of Invention
The present invention is directed to solving the above problems of the prior art. A front-end readout circuit for application to a radiation detector is presented. The technical scheme of the invention is as follows:
a front-end readout circuit for application to a radiation detector, comprising: the circuit comprises an input port, a preamplifier, a zero-pole elimination circuit, a shaper and an output port; the signal from the detector is connected with the input port, the input port is connected with the input end of the preamplifier, the output end of the preamplifier is connected with the input end of the zero-pole elimination circuit, the output end of the zero-pole elimination circuit is connected with the input end of the shaper, and the output end of the shaper outputs a voltage signal;
the preamplifier carries out secondary amplification through an NMOS tube M5 and a PMOS tube M3 to amplify charge signals output by the detector, and the zero pole elimination circuit passes through a resistor RPZAnd a capacitor C1To reduce the time constant of the exponentially decaying signal and eliminate output signal undershoot, said shaper passing through a resistor R1Resistance R2Capacitor C1Capacitor C2And an amplifier comprising a CR-RC filter for filtering noise and adjusting the waveform.
Further, the preamplifier comprises a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6, a capacitor CfAnd a resistance RfWherein the gate of the PMOS transistor M1 is connected to VBIAS1The source electrode of the PMOS tube M1 is connected with VDD, the drain electrode of the PMOS tube M1 is connected with the source electrode of the PMOS tube M2, and the grid electrode of the PMOS tube M2 is connected with VBIAS2The drains of the PMOS tubes M2 are respectively connected with the capacitor CfOne end of the NMOS transistor M4, the drain electrode of the NMOS transistor M3, the gate electrode of the NMOS transistor M4 and the V are connectedBIAS3The source electrode of the NMOS transistor M4 is connected with the drain electrode of the NMOS transistor M5, the source electrode of the NMOS transistor M5 is connected with GND, and the grid electrode of the NMOS transistor M5 is respectively connected with the capacitor CfAnother terminal of (1), a resistor RfOne end of the PMOS tube M3 is connected with IN, the source electrode of the PMOS tube M3 is connected with VDD, and the drain electrode of the PMOS tube M3 is respectively connected with a resistor RfThe other end of the NMOS transistor M6, the gate of the NMOS transistor M6 and VBIAS4Are connected.
Furthermore, in the preamplifier, VDD is a power line, GND is a ground line, and VBIAS1、VBIAS2、VBIAS3And VBIAS4The signal is an offset signal, IN is a detector input signal, after the signal is input by the detector, the input charge is amplified and converted into a voltage signal by the preamplifier, the voltage signal is output by a node 1, wherein the node 1 is the drain electrode of a PMOS (P-channel metal oxide semiconductor) transistor M3 and a resistor R respectivelyfAnd the other end of the NMOS transistor M6 to the drain thereof.
Further, the preamplifier is characterized in that the preamplifier is used for pre-amplifyingThe equivalent total capacitance of the input end of the device is Cif
Cif＝Ci+(1+Ao)Cf
Wherein, CiIs the total capacitance of the input terminal, AoFor open loop gain, CfIs a feedback capacitance.
When the open loop gain AoWhen large, (1+ A)o)Cf＞＞CfThe input charge Q is mainly accumulated in the feedback capacitor CfAbove, the output voltage amplitude is approximately CfVoltage of, i.e.
Figure BDA0002813887660000021
Feedback capacitance CfIs a fixed value, so the output voltage of the preamplifier is only related to the input charge, and the function of amplifying the charge signal input by the detector is realized.
Further, the pole-zero elimination circuit comprises a resistor RPZAnd a capacitor C1Resistance RPZOne terminal of (1) and node 1 and capacitor C1Is connected to be input by a node 1 and is output by a node 2, wherein the node 2 is a resistor RPZAnd the other end of (1) and node 1 and capacitor C1And the other end of the same.
Further, the pole-zero elimination circuit specifically includes:
ideal preamplifier, output signal v0Has a time domain function of
Figure BDA0002813887660000031
Wherein Q isiFor inputting electric charge, CfFor feedback capacitance, RfFor feedback resistance, t represents time, Qiτf＝RfCfAs a function of time for the preamplifier;
output v of ideal shapersHas a time domain function of
Figure BDA0002813887660000032
Wherein Q isiFor inputting electric charge, CfFor feedback capacitance, RfFor feedback resistance, τ is the former time constant, τfIs the preamplifier time constant.
Let the former time constant tau and the preamplifier time constant taufIs λ, then
Figure BDA0002813887660000033
The magnitude and width of the signal undershoot is determined by λ.
After adding the zero pole elimination circuit, the shaper outputs vsHas a frequency domain function of
Figure BDA0002813887660000034
Wherein Q isiFor inputting electric charge, CfFor feedback capacitance, RPZ、R1And R2Resistance designed for the circuit, C1And C2For the capacitance of the circuit design, s represents the time domain and n represents the shaper order.
Designing the circuit as
CfRf＝C1RPZ
The shaper outputs vsIs rewritten as a frequency domain function
Figure BDA0002813887660000041
Preamplifier time constant τf＝RPZCfThe time constant τ R of the former1C1＝R2C2；
In the usual case τf> τ, whereby RPZ||R1≈R1
The pole of the preamplifier and the zero of the shaper are mutually offset, and the time constant of the exponential decay signal is taufIs reduced to τ.
Further, the former includes a resistor R1Resistance R2Capacitor C2And an operational amplifier in which the resistor R1Is connected to node 2, resistor R1The other end of the resistor is respectively connected with the inverting terminal of the operational amplifier and the resistor R2One terminal of and a capacitor C2Is connected with the non-inverting terminal of the operational amplifier and VREFConnected to the outputs of the operational amplifiers via resistors R2Another terminal of (1) and a capacitor C2Are connected at the other end with VREFThe signal at node 2, which is the reference voltage, passes through the shaper and outputs a shaped waveform, which is an analog signal.
Further, the operational amplifier comprises an NMOS transistor M7, a PMOS transistor M8, a PMOS transistor M9, an NMOS transistor M10, a PMOS transistor M11, an NMOS transistor M12, a PMOS transistor M13, a PMOS transistor M14, an NMOS transistor M15, a PMOS transistor M16, a PMOS transistor M17 and a capacitor CCWherein the grid of NMOS transistor M7 is connected with the drain of NMOS transistor M7, the drain of PMOS transistor M8 and the grid of NMOS transistor M12, the source of NMOS transistor M7 is connected with GND, the grid of PMOS transistor M8 is connected with the drain of NMOS transistor M10, the drain of PMOS transistor M11, the grid of PMOS transistor M11 and the grid of PMOS transistor M13, the grid of PMOS transistor M9 is connected with VPThe source electrode of the PMOS tube M9 is respectively connected with the drain electrode of the PMOS tube M17, the source electrode of the PMOS tube M11 and the source electrode of the PMOS tube M14, and the grid electrode of the NMOS tube M10 is connected with VBIAS7The source electrode of the NMOS tube M10 is connected with GND, the source electrode of the NMOS tube M12 is connected with GND, and the drain electrode of the NMOS tube M12 is respectively connected with the drain electrode of the PMOS tube M13 and the capacitor CCOne end of the PMOS transistor M13 is connected with the grid electrode of the NMOS transistor M15, and the grid electrode of the PMOS transistor M13 is connected with the VNThe source of the NMOS tube M15 is connected with GND, and the drain of the NMOS tube M15 is connected with the capacitor CCThe other end of the PMOS transistor M16 is connected with the drain electrode of the PMOS transistor M16 and the OUT, and the grid electrode of the PMOS transistor M16 is connected with the VBIAS6The source electrode of the PMOS tube M16 is connected with VDD, and the gate electrode of the PMOS tube M17 is connected with VBIAS5The source electrode of the PMOS tube M17 is connected with VDD and operatedThe computing amplifier VDD is a power line, GND is a ground line, VBIAS5、VBIAS6And VBIAS7For bias signal, VPIs the non-inverting terminal of the operational amplifier, VNIs the inverting terminal of the operational amplifier.
The invention has the following advantages and beneficial effects:
the invention adds a zero pole elimination circuit between the preamplifier and the shaper, namely by a first integral capacitor C of the shaper1Upper parallel resistance RPZA zero is introduced, the size of which is the same as the pole generated by the preamplifier, and the zero pole of the preamplifier and the zero pole of the shaper are eliminated. Under the condition that the frequency of an input radiation signal is 100 KHz, the baseline wander of the whole reading circuit can be controlled below 1mV within 1ms, while the baseline wander of the front-end reading circuit of the traditional radiation detector can reach 30mV-40mV under the same condition.
Drawings
FIG. 1 is a functional block diagram of a conventional sensing circuit;
FIG. 2 is a simulated output waveform of a conventional sensing circuit;
FIG. 3 is a functional block diagram of a radiation detector front-end readout circuit in accordance with a preferred embodiment of the present invention;
FIG. 4 is a circuit diagram of a radiation detector front end readout circuit in accordance with a preferred embodiment of the present invention;
fig. 5 is a circuit diagram of an operational amplifier in a shaper according to a preferred embodiment of the present invention.
FIG. 6 provides a simulated output waveform of a preferred embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described in detail and clearly with reference to the accompanying drawings. The described embodiments are only some of the embodiments of the present invention.
The technical scheme for solving the technical problems is as follows:
the technical scheme for solving the technical problems is as follows: the signal from the detector enters the preamplifier from the input port, the output end of the preamplifier is connected with the input end of the zero-pole elimination circuit, the output end of the zero-pole elimination circuit is connected with the input end of the shaper, and the output end of the shaper outputs a voltage signal. The invention comprises a preamplifier, a pole-zero elimination circuit and a shaper, wherein the preamplifier is used for amplifying charge signals output by a detector, the pole-zero elimination circuit is used for reducing the time constant of exponential decay signals and eliminating undershoot of output signals, the shaper is used for filtering noise and adjusting waveforms, and the output waveforms are improved through the pole-zero elimination circuit, so that the front-end reading of the signals of the radiation detector is realized.
In order to better understand the technical solutions, the technical solutions will be described in detail below with reference to the drawings and specific embodiments.
Examples
A front-end readout circuit for use in a radiation detector, as shown in fig. 3, comprising: a preamplifier, a zero-pole eliminating circuit and a shaper;
the signal from the detector enters the preamplifier from the input port, the output end of the preamplifier is connected with the input end of the zero-pole elimination circuit, the output end of the zero-pole elimination circuit is connected with the input end of the shaper, and the output end of the shaper outputs a voltage signal.
The preamplifier carries out secondary amplification through an NMOS tube M5 and a PMOS tube M3 to amplify charge signals output by the detector, and the zero pole elimination circuit passes through a resistor RPZAnd a capacitor C1To reduce the time constant of the exponentially decaying signal and eliminate output signal undershoot, said shaper passing through a resistor R1Resistance R2Capacitor C1Capacitor C2And an amplifier comprising a CR-RC filter for filtering noise and adjusting the waveform.
As a preferred technical solution, as shown in fig. 4, the preamplifier includes a PMOS transistor M1, a PMOS transistor M2, a PMOS transistor M3, an NMOS transistor M4, an NMOS transistor M5, an NMOS transistor M6, a capacitor CfAnd a resistance RfWherein the gate of the PMOS transistor M1 is connected to VBIAS1The source electrode of the PMOS tube M1 is connected with VDD, the drain electrode of the PMOS tube M1 is connected with the source electrode of the PMOS tube M2, and the grid electrode of the PMOS tube M2 is connected with VBIAS2The drains of the PMOS tubes M2 are respectively connected with the capacitor CfOne end of the NMOS transistor M4, the drain electrode of the NMOS transistor M3, the gate electrode of the NMOS transistor M4 and the V are connectedBIAS3The source electrode of the NMOS transistor M4 is connected with the drain electrode of the NMOS transistor M5, the source electrode of the NMOS transistor M5 is connected with GND, and the grid electrode of the NMOS transistor M5 is respectively connected with the capacitor CfAnother terminal of (1), a resistor RfOne end of the PMOS tube M3 is connected with IN, the source electrode of the PMOS tube M3 is connected with VDD, and the drain electrode of the PMOS tube M3 is respectively connected with a resistor RfThe other end of the NMOS transistor M6, the gate of the NMOS transistor M6 and VBIAS4Are connected.
Furthermore, in the preamplifier, VDD is a power line, GND is a ground line, and VBIAS1、VBIAS2、VBIAS3And VBIAS4The signal is an offset signal, IN is a detector input signal, after the signal is input by the detector, the input charge is amplified and converted into a voltage signal by the preamplifier, the voltage signal is output by a node 1, wherein the node 1 is the drain electrode of a PMOS (P-channel metal oxide semiconductor) transistor M3 and a resistor R respectivelyfAnd the other end of the NMOS transistor M6 to the drain thereof.
Further, the preamplifier is characterized in that the equivalent total capacitance of the input end of the preamplifier is Cif
Cif＝Ci+(1+Ao)Cf
Wherein, CiIs the total capacitance of the input terminal, AoFor open loop gain, CfIs a feedback capacitance.
When the open loop gain AoWhen large, (1+ A)o)Cf＞＞CfThe input charge Q is mainly accumulated in the feedback capacitor CfAbove, the output voltage amplitude is approximately CfVoltage of, i.e.
Figure BDA0002813887660000071
Feedback capacitance CfIs a constant value, so that the output voltage of the preamplifier is only equal toThe input charges are related, and the function of amplifying the charge signals input by the detector is realized.
As a preferred technical solution, as shown in fig. 4, the pole-zero elimination circuit includes a resistor RPZAnd a capacitor C1Resistance RPZOne terminal of (1) and node 1 and capacitor C1Is connected to one end of a resistor RPZAnd the other end of (1) and node 1 and capacitor C1And the other end of the two are connected.
Further, the pole-zero elimination circuit is characterized by being input by a node 1 and output by a node 2, wherein the node 2 is a resistor RPZAnd the other end of (1) and node 1 and capacitor C1And the other end of the same.
Further, the pole-zero elimination circuit specifically includes:
ideal preamplifier, output signal v0Has a time domain function of
Figure BDA0002813887660000081
Wherein Q isiFor inputting electric charge, CfFor feedback capacitance, RfFor feedback resistance, t represents time, Qiτf＝RfCfAs a function of time for the preamplifier;
output v of ideal shapersHas a time domain function of
Figure BDA0002813887660000082
Wherein Q isiFor inputting electric charge, CfFor feedback capacitance, RfFor feedback resistance, τ is the former time constant, τfIs the preamplifier time constant.
Let the former time constant tau and the preamplifier time constant taufIs λ, then
Figure BDA0002813887660000083
The magnitude and width of the signal undershoot is determined by λ.
After adding the zero pole elimination circuit, the shaper outputs vsHas a frequency domain function of
Figure BDA0002813887660000084
Wherein Q isiFor inputting electric charge, CfFor feedback capacitance, RPZ、R1And R2Resistance designed for the circuit, C1And C2For the capacitance of the circuit design, s represents the time domain and n represents the shaper order.
Designing the circuit as
CfRf＝C1RPZ
The shaper outputs vsIs rewritten as a frequency domain function
Figure BDA0002813887660000085
Preamplifier time constant τf＝RPZCfThe time constant τ R of the former1C1＝R2C2；
In the usual case τf> τ, whereby RPZ||R1≈R1
The pole of the preamplifier and the zero of the shaper are mutually offset, and the time constant of the exponential decay signal is taufIs reduced to τ.
As a preferred solution, said former comprises a resistor R, as shown in fig. 41Resistance R2Capacitor C2And an operational amplifier in which the resistor R1Is connected to node 2, resistor R1The other end of the resistor is respectively connected with the inverting terminal of the operational amplifier and the resistor R2One terminal of and a capacitor C2Is connected to the non-inverting terminal of the operational amplifier andVREFconnected to the outputs of the operational amplifiers via resistors R2Another terminal of (1) and a capacitor C2And the other end of the two are connected.
As a preferred technical solution, as shown in fig. 5, the operational amplifier includes an NMOS transistor M7, a PMOS transistor M8, a PMOS transistor M9, an NMOS transistor M10, a PMOS transistor M11, an NMOS transistor M12, a PMOS transistor M13, a PMOS transistor M14, an NMOS transistor M15, a PMOS transistor M16, a PMOS transistor M17, and a capacitor CCWherein the grid of NMOS transistor M7 is connected with the drain of NMOS transistor M7, the drain of PMOS transistor M8 and the grid of NMOS transistor M12, the source of NMOS transistor M7 is connected with GND, the grid of PMOS transistor M8 is connected with the drain of NMOS transistor M10, the drain of PMOS transistor M11, the grid of PMOS transistor M11 and the grid of PMOS transistor M13, the grid of PMOS transistor M9 is connected with VPThe source electrode of the PMOS tube M9 is respectively connected with the drain electrode of the PMOS tube M17, the source electrode of the PMOS tube M11 and the source electrode of the PMOS tube M14, and the grid electrode of the NMOS tube M10 is connected with VBIAS7The source electrode of the NMOS tube M10 is connected with GND, the source electrode of the NMOS tube M12 is connected with GND, and the drain electrode of the NMOS tube M12 is respectively connected with the drain electrode of the PMOS tube M13 and the capacitor CCOne end of the PMOS transistor M13 is connected with the grid electrode of the NMOS transistor M15, and the grid electrode of the PMOS transistor M13 is connected with the VNThe source of the NMOS tube M15 is connected with GND, and the drain of the NMOS tube M15 is connected with the capacitor CCThe other end of the PMOS transistor M16 is connected with the drain electrode of the PMOS transistor M16 and the OUT, and the grid electrode of the PMOS transistor M16 is connected with the VBIAS6The source electrode of the PMOS tube M16 is connected with VDD, and the gate electrode of the PMOS tube M17 is connected with VBIAS5And the source electrode of the PMOS pipe M17 is connected with VDD.
Further, the operational amplifier is characterized in that VDD is a power line, GND is a ground line, and V isBIAS5、VBIAS6And VBIAS7For bias signal, VPIs the non-inverting terminal of the operational amplifier, VNIs the inverting terminal of the operational amplifier.
Further, said former characterized in that said former has VREFThe signal at node 2, which is the reference voltage, passes through the shaper and outputs a shaped waveform, which is an analog signal.
FIG. 6 provides a simulated output waveform of a preferred embodiment of the present invention. Wherein the abscissa is time T and the ordinate is voltage V. Simulation results show that after the zero-pole elimination circuit is added, under the condition of input of the same charge signal, the amplitude deviation of the output waveform after forming is smaller, and the baseline drift is more stable.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above examples are to be construed as merely illustrative and not limitative of the remainder of the disclosure. After reading the description of the invention, the skilled person can make various changes or modifications to the invention, and these equivalent changes and modifications also fall into the scope of the invention defined by the claims.

Claims (8)

1. A front-end readout circuit for use in a radiation detector, comprising: the circuit comprises an input port, a preamplifier, a zero-pole elimination circuit, a shaper and an output port; the signal from the detector is connected with the input port, the input port is connected with the input end of the preamplifier, the output end of the preamplifier is connected with the input end of the zero-pole elimination circuit, the output end of the zero-pole elimination circuit is connected with the input end of the shaper, and the output end of the shaper outputs a voltage signal;
the preamplifier carries out secondary amplification through an NMOS tube M5 and a PMOS tube M3 to amplify charge signals output by the detector, and the zero pole elimination circuit passes through a resistor RPZAnd a capacitor C1To reduce the time constant of the exponentially decaying signal and eliminate output signal undershoot, said shaper passing through a resistor R1Resistance R2Capacitor C1Capacitor C2And an amplifier comprising a CR-RC filter for filtering noise and adjusting the waveform.
2. The front-end readout circuit applied to the radiation detector as claimed in claim 1, wherein the preamplifier comprises a PMOS transistor M1, a PMOS transistor M2, a PMOS transistor M3, an NMOS transistor M4, an NMOS transistor M5, an NMOS transistor M6, a capacitor CfAnd a resistance RfWherein the gate of the PMOS transistor M1 is connected to VBIAS1The source electrode of the PMOS tube M1 is connected with VDD, the drain electrode of the PMOS tube M1 is connected with the source electrode of the PMOS tube M2, and the grid electrode of the PMOS tube M2 is connected with VBIAS2The drains of the PMOS tubes M2 are respectively connected with the capacitor CfOne end of the NMOS transistor M4, the drain electrode of the NMOS transistor M3, the gate electrode of the NMOS transistor M4 and the V are connectedBIAS3The source electrode of the NMOS transistor M4 is connected with the drain electrode of the NMOS transistor M5, the source electrode of the NMOS transistor M5 is connected with GND, and the grid electrode of the NMOS transistor M5 is respectively connected with the capacitor CfAnother terminal of (1), a resistor RfOne end of the PMOS tube M3 is connected with IN, the source electrode of the PMOS tube M3 is connected with VDD, and the drain electrode of the PMOS tube M3 is respectively connected with a resistor RfThe other end of the NMOS transistor M6, the gate of the NMOS transistor M6 and VBIAS4Are connected.
3. The front-end readout circuit for radiation detector as claimed in claim 2, wherein in the preamplifier, VDD is power line, GND is ground, VBIAS1、VBIAS2、VBIAS3And VBIAS4The signal is an offset signal, IN is a detector input signal, after the signal is input by the detector, the input charge is amplified and converted into a voltage signal by the preamplifier, the voltage signal is output by a node 1, wherein the node 1 is the drain electrode of a PMOS (P-channel metal oxide semiconductor) transistor M3 and a resistor R respectivelyfAnd the other end of the NMOS transistor M6 to the drain thereof.
4. A front-end readout circuit for use in a radiation detector as claimed in claim 2 or 3, wherein the equivalent total capacitance at the input of the preamplifier is Cif
Cif＝Ci+(1+Ao)Cf
Wherein, CiIs the total capacitance of the input terminal, AoFor open loop gain, CfIs a feedback capacitance.
When the open loop gain AoWhen large, (1+ A)o)Cf＞＞CfThe input charge Q is mainly accumulated in the feedback capacitor CfAbove, the output voltage amplitude is approximately CfVoltage of, i.e.
Figure FDA0002813887650000021
Feedback capacitance CfIs a fixed value, so the output voltage of the preamplifier is only related to the input charge, and the function of amplifying the charge signal input by the detector is realized.
5. The front-end readout circuit for use in a radiation detector as claimed in claim 4, wherein the pole-zero cancellation circuit comprises a resistor RPZAnd a capacitor C1Resistance RPZOne terminal of (1) and node 1 and capacitor C1Is connected to be input by a node 1 and is output by a node 2, wherein the node 2 is a resistor RPZAnd the other end of (1) and node 1 and capacitor C1And the other end of the same.
6. The front-end readout circuit applied to the radiation detector according to claim 5, wherein the pole-zero cancellation circuit specifically comprises:
ideal preamplifier, output signal v0Has a time domain function of
Figure FDA0002813887650000022
Wherein Q isiFor inputting electric charge, CfFor feedback capacitance, RfFor feedback resistance, t represents time, Qiτf＝RfCfAs a function of time for the preamplifier;
output v of ideal shapersHas a time domain function of
Figure FDA0002813887650000023
Wherein Q isiFor inputting electric charge, CfFor feedback capacitance, RfFor feedback resistance, τ is the former time constant, τfIs the preamplifier time constant.
Let the former time constant tau and the preamplifier time constant taufIs λ, then
Figure FDA0002813887650000031
The magnitude and width of the signal undershoot is determined by λ.
After adding the zero pole elimination circuit, the shaper outputs vsHas a frequency domain function of
Figure FDA0002813887650000032
Wherein Q isiFor inputting electric charge, CfFor feedback capacitance, RPZ、R1And R2Resistance designed for the circuit, C1And C2For the capacitance of the circuit design, s represents the time domain and n represents the shaper order.
Designing the circuit as
CfRf＝C1RPZ
The shaper outputs vsIs rewritten as a frequency domain function
Figure FDA0002813887650000033
Preamplifier time constant τf＝RPZCfThe time constant τ R of the former1C1＝R2C2；
In the usual case τf> τ, whereby RPZ||R1≈R1
The pole of the preamplifier and the zero of the shaper are mutually offset, and the time constant of the exponential decay signal is taufIs reduced to τ.
7. Front-end readout circuit for a radiation detector according to claim 5, characterized in that the shaper comprises a resistor R1Resistance R2Capacitor C2And an operational amplifier in which the resistor R1Is connected to node 2, resistor R1The other end of the resistor is respectively connected with the inverting terminal of the operational amplifier and the resistor R2One terminal of and a capacitor C2Is connected with the non-inverting terminal of the operational amplifier and VREFConnected to the outputs of the operational amplifiers via resistors R2Another terminal of (1) and a capacitor C2Are connected at the other end with VREFThe signal at node 2, which is the reference voltage, passes through the shaper and outputs a shaped waveform, which is an analog signal.
8. The front-end readout circuit applied to the radiation detector of claim 7, wherein the operational amplifier comprises an NMOS transistor M7, a PMOS transistor M8, a PMOS transistor M9, an NMOS transistor M10, a PMOS transistor M11, an NMOS transistor M12, a PMOS transistor M13, a PMOS transistor M14, an NMOS transistor M15, a PMOS transistor M16, a PMOS transistor M17 and a capacitor CCWherein the grid of NMOS transistor M7 is connected with the drain of NMOS transistor M7, the drain of PMOS transistor M8 and the grid of NMOS transistor M12, the source of NMOS transistor M7 is connected with GND, the grid of PMOS transistor M8 is connected with the drain of NMOS transistor M10, the drain of PMOS transistor M11, the grid of PMOS transistor M11 and the grid of PMOS transistor M13, the grid of PMOS transistor M9 is connected with VPThe source electrode of the PMOS tube M9 is respectively connected with the drain electrode of the PMOS tube M17, the source electrode of the PMOS tube M11 and the source electrode of the PMOS tube M14, and the grid electrode of the NMOS tube M10 is connected with VBIAS7The source electrode of the NMOS tube M10 is connected with GND, and the source electrode of the NMOS tube M12The drain electrode of the NMOS tube M12 is connected with the drain electrode of the PMOS tube M13 and the capacitor C respectivelyCOne end of the PMOS transistor M13 is connected with the grid electrode of the NMOS transistor M15, and the grid electrode of the PMOS transistor M13 is connected with the VNThe source of the NMOS tube M15 is connected with GND, and the drain of the NMOS tube M15 is connected with the capacitor CCThe other end of the PMOS transistor M16 is connected with the drain electrode of the PMOS transistor M16 and the OUT, and the grid electrode of the PMOS transistor M16 is connected with the VBIAS6The source electrode of the PMOS tube M16 is connected with VDD, and the gate electrode of the PMOS tube M17 is connected with VBIAS5The source electrode of the PMOS tube M17 is connected with VDD, the operational amplifier VDD is a power supply line, GND is a ground line, and V isBIAS5、VBIAS6And VBIAS7For bias signal, VPIs the non-inverting terminal of the operational amplifier, VNIs the inverting terminal of the operational amplifier.
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Application publication date: 20210326