CN112563132A - Rapid thinning and polishing method for surface heterostructure - Google Patents
Rapid thinning and polishing method for surface heterostructure Download PDFInfo
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- CN112563132A CN112563132A CN202011267262.6A CN202011267262A CN112563132A CN 112563132 A CN112563132 A CN 112563132A CN 202011267262 A CN202011267262 A CN 202011267262A CN 112563132 A CN112563132 A CN 112563132A
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- 239000000243 solution Substances 0.000 description 13
- 229910000420 cerium oxide Inorganic materials 0.000 description 11
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 11
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31058—After-treatment of organic layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
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Abstract
The invention provides a method for quickly thinning and polishing a surface heterostructure, which utilizes a chemical reagent to change the surface state and the property of a metal material in the thinning and polishing process, reduces the grinding force required by the separation of the metal material, and controls the removal rate of the metal and photoresist to be at the same level. The process method abandons pure mechanical grinding of the cast iron plate, avoids the tensile deformation of the metal structure caused by pure physical grinding action, effectively controls the dimensional precision and the plane flatness of the graph, and has the thinning and polishing speed of 2-3 mu m/min.
Description
Technical Field
The invention relates to the field of substrate polishing, in particular to a method for quickly thinning and polishing a surface heterostructure.
Background
With the rapid development in the field of semiconductor technology, semiconductor devices have become increasingly complex. In order to improve the integration and reduce the manufacturing cost, the size of the device is reduced more and more, the number of original devices in a unit area of a chip is increased more and more, and the in-plane wiring cannot meet the requirement of high-density device distribution, so that only a multilayer wiring structure can be adopted. When the metal layer is stacked too much on the wafer substrate, the surface relief of the chip is more obvious. The most intuitive negative effect of surface relief is that it is difficult to obtain a smooth photoresist film during the photoresist leveling process of the subsequent photolithography process, so that it is difficult to accurately control the dimension of the photoresist pattern by adjusting the exposure amount during the exposure and development process, and the dimension deviation is fatal to the performance of the semiconductor device.
A flattening process for semiconductor wafer includes such steps as grinding the homogeneous or heterogeneous material on the surface of wafer, removing the material with a certain sacrificial thickness, and chemically polishing to smooth the surface. If the material of the surface of the wafer is single, the sacrificial thickness material can be removed quickly and efficiently by adopting a mechanical grinding method, the thickness difference is controlled within a small range, and then the surface height is flattened by adopting a chemical mechanical polishing method, so that the roughness is reduced. However, devices in the semiconductor processing industry often have a combined pattern of multiple materials on the surface, and the hardness and toughness of the materials are greatly different, so that the removal rate of the surface materials is inconsistent by using a mechanical grinding method, and the tensile deformation is caused in the grinding hard contact process by a more prominent structure in the further grinding process, so that the grinding rate needs to be reduced to control the pattern accuracy.
The existing method for quickly thinning and polishing the surface heterostructure can effectively solve the problem that the composite pattern of multiple materials on the surface has large difference in hardness and toughness, and the adoption of a mechanical grinding method can cause inconsistent removal rate of the surface materials, so that the more prominent structure in the further grinding process can cause tensile deformation in the grinding and hard contact process.
Disclosure of Invention
The invention provides a method for quickly thinning and polishing a surface heterostructure, aiming at solving the problems that in the prior art, the thickness difference of a heterogeneous graph on the surface after a planarization process is larger due to different cutting rates of different materials in the planarization process caused by different hardness and toughness of heterogeneous materials, and the performance of a metal structure device is influenced due to the fact that the flexible metal is stretched, deformed or damaged in a pure mechanical grinding and thinning process.
The invention provides a method for quickly thinning and polishing a surface heterostructure, which comprises the following steps:
s1, using a thickness gauge to measure the thickness of the heterogeneous pattern on the surface of the wafer to be processed on the substrate, and recording the height of the highest pattern of the heterogeneous pattern on the surface and the height of the mode range in the heterogeneous pattern on the surface;
s2, mounting a polyurethane disc on a wafer thinning machine, and chemically thinning and mechanically thinning the substrate through the polyurethane disc;
s3, measuring the highest pattern height and mode range height in the heterogeneous pattern on the surface of the substrate subjected to the primary chemical thinning and mechanical thinning by using a thickness gauge, and if the thickness difference exceeds the thinning preset value, performing the step S2; if the measured thickness difference value meets the requirement of the thinning preset value, performing step S4;
s4, detaching the polyurethane disc on the wafer thinning machine, installing a soft flannelette disc for polishing on the wafer thinning machine, and carrying out chemical polishing and mechanical polishing on the substrate by using the soft polishing flannelette disc for polishing;
s5, measuring the thickness of the surface heterogeneous graph of the upper surface of the semiconductor substrate after mechanochemical polishing by adopting a thickness gauge, and repeating the step S4 if the thickness difference of the surface heterogeneous graph exceeds the preset polishing value; if the measured thickness difference and the overall height of the surface heterogeneous pattern meet the requirement of a polishing preset value, performing step S6;
and S6, finishing the thinning and polishing of the substrate.
After chemical mechanical thinning, the thickness difference between the highest pattern and the mode range pattern on the surface of the semiconductor substrate should be controlled within 30 μm. In step S4, after the chemical mechanical polishing, the thickness difference between the highest pattern on the surface of the semiconductor substrate and the pattern in the height mode range should be controlled within 3 μm, and the thickness difference between the adjacent heterogeneous patterns on the surface of the semiconductor substrate should be controlled within 1 μm;
the invention relates to a method for quickly thinning and polishing a surface heterostructure, which is used as a preferred mode, wherein a base body comprises a surface heterogeneous graph and a semiconductor substrate, and the surface heterogeneous graph is arranged on the upper surface of the semiconductor substrate; the surface heterogeneous pattern comprises a surface photoresist and a plurality of surface metal columnar structures vertical to the semiconductor substrate, wherein the surface photoresist is fully distributed on the upper surface of the semiconductor substrate and fills gaps among the surface metal.
The thickness difference exists between the surface metal material and the surface photoresist material, the surface metal is a plurality of columns and cuboids which are distributed on the sector antenna, distributed in a honeycomb shape and randomly distributed and perpendicular to the substrate, and the surface photoresist material is arranged in a gap between every two adjacent metal materials.
As a preferred mode, the preset thinning value in the step S3 is 0-30 mu m.
As an optimal mode, the chemical thinning and mechanical thinning, and the chemical polishing and mechanical polishing removal rates are the same.
As a preferred mode, the surface roughness of the surface heterogeneous pattern after chemical polishing and mechanical polishing in the step S4 is less than 1 nm.
The invention relates to a method for quickly thinning and polishing a surface heterostructure, which is a preferable mode, wherein the preset polishing value in the step S5 is 0-1 mu m.
According to the method for quickly thinning and polishing the surface heterostructure, which is disclosed by the invention, as a preferable mode, in the polishing process in the step S4, the stretching rate of the surface metal structure in the length direction of the graph is controlled within 3%.
As a preferred mode, the polishing solution used for chemical thinning and chemical polishing is a chemical reagent capable of selectively corroding metals.
The method is suitable for the combination of non-single material of the surface pattern, especially the soft metal and photoresist material. In the thinning and polishing process of the process method, the surface state and the property of the metal material are changed by using a chemical reagent, the grinding force required during the separation is reduced, and the removal rates of the metal and the photoresist are controlled to be at the same level. The process method abandons pure mechanical grinding of the cast iron plate, avoids the tensile deformation of the metal structure caused by pure physical grinding action, effectively controls the dimensional precision and the plane flatness of the graph, and has the thinning and polishing speed of 2-3 mu m/min.
The invention has the following beneficial effects:
the chemical mechanical thinning and chemical mechanical polishing combined processing method is adopted, primary flattening processing is carried out on the surface of the wafer heterogeneous graph by utilizing chemical mechanical thinning, the metal graph with larger surface thickness difference is quickly removed, the whole graph thickness difference on the surface is controlled within a certain range, and the graph structure is prevented from being scratched, bumped and damaged when the substrate is polished on a soft flannelette disc. And then, polishing is carried out by utilizing a physical and chemical combined mode, so that the material removal rate is greatly increased, and the transverse drawing deformation of the graph caused by grinding and hard contact grinding of the cast iron disc is avoided. Meanwhile, because the hardness and density difference of the surface photoresist material and the metal material are large, when a cast iron disc is used for hard contact cutting, the cutting speed of the surface photoresist material and the metal material is different, the final thickness difference depends on the particle size of grinding liquid, and the removal rate of the metal material and the photoresist material can be adjusted by changing the proportion of hydrogen peroxide by adopting a physical and chemical combination removal mode on a soft flannelette disc, the thickness difference of each graph on the surface of the finally obtained wafer substrate is within 1 mu m, the roughness (Ra) of the surface metal material is within 1nm, the surface flatness is within 3 mu m, the thinning rate can be up to 2-3 mu m/min, and the deformation and stretching rate in the length direction of the graph is controlled within 3%.
Drawings
FIG. 1 is a flow chart of a method for rapid thinning and polishing of a surface heterostructure;
FIG. 2 is a schematic diagram of a substrate for a method of rapid thinning and polishing of a surface heterostructure;
FIG. 3 is a method for rapid thinning and polishing of a surface heterostructure.
Reference numerals:
1. surface heterogeneous patterns; 11. a surface photoresist; 12. a surface metal; 2. a semiconductor substrate.
Detailed Description
The technical solutions in the embodiments of the present invention will be made clear below with reference to the accompanying drawings in the embodiments of the present invention.
Example 1
As shown in fig. 1, a method for rapidly thinning and polishing a surface heterostructure includes the following steps:
s1, turning on a vacuum pump, placing the semiconductor substrate to be processed on a special suction tool, vacuumizing and adsorbing, measuring a photoresist material graph and a metal material graph in a heterogeneous graph on the surface of the semiconductor substrate by using a contact thickness gauge, and recording the highest value and the height mode range value in all graphs;
and S2, chemically and mechanically thinning, opening the wafer thinning machine, selecting a polyurethane disc according to the material characteristics of the surface of the heterogeneous graph, and installing the swing arm. Preparing a 3-micron cerium oxide suspension and water into a grinding fluid according to a certain proportion, and adjusting the dropping speed of the guide cylinder to 40-60 drops/min. Preparing a chemical corrosive liquid from the nanometer silicon oxide suspension, hydrogen peroxide and water according to a certain proportion, adjusting the dropping speed to 60-100 drops/min, fixing the semiconductor substrate to be processed on a grinding tool in a vacuum adsorption mode, and inverting the semiconductor substrate above a flannelette disc. Adjusting the rotating speed of the polyurethane disc to 20-50 revolutions per minute, grinding the substrate for 5-10 minutes, and controlling the mode range height of the surface of the substrate and the thickness difference value of the highest pattern within a required range through chemical mechanical thinning. After grinding, washing with deionized water, wiping with dust-free cloth in the washing process, and finally blowing clean with nitrogen;
s3, measuring the highest pattern height and mode range height in the heterogeneous pattern 1 on the surface of the base body after the primary chemical thinning and mechanical thinning by adopting a thickness gauge, and if the thickness difference value exceeds the thinning preset value, performing the step S2; if the measured thickness difference value meets the requirement of the thinning preset value, performing step S4;
and S4, detaching the polyurethane disc for chemical mechanical thinning, replacing the polyurethane disc with a soft flannelette disc for polishing, and fixing the swing arm. According to the silicon oxide polishing solution: hydrogen peroxide: and (5) preparing the mixed polishing solution according to the proportion of (1-5) to (80), adjusting the dropping speed to 60-120 drops/min, opening the cerium oxide grinding solution prepared in the step S2, adjusting the dropping speed to 40-60 drops/min, and dropping the cerium oxide grinding solution and the cerium oxide grinding solution on the soft flannelette disk together. Fixing the substrate on a tool and inverting the substrate on a flannelette disc, fixing 3-5kg of balance weight above the tool, adjusting the rotating speed of the flannelette disc to 60-100 revolutions per minute, and polishing the substrate for 10-15 min. Closing the cerium oxide grinding fluid guide pipe, adjusting the balance weight on the fixed tool to 5-8 kg, and polishing the substrate for 10-30 min;
s5, measuring the thickness of the surface heterogeneous graph 1 on the upper surface of the semiconductor substrate 2 after mechanochemical polishing by using a thickness gauge, if the thickness difference of the surface heterogeneous graph 1 exceeds the preset polishing value, stopping the polishing step after the cerium oxide suspension guide cylinder, reducing the counter weight, and repeating the step S4; if the measured thickness difference and the overall height of the surface heterogeneous pattern 1 meet the requirement of a preset polishing value, performing step S6;
s6, adopting a probe type step profiler to measure the substrate which meets the overall height requirement and the heterogeneous pattern thickness difference requirement in the step S5, wherein the heterogeneous pattern thickness difference is less than 1 μm, the overall thickness difference is controlled within 3 μm, and the surface roughness of a single material is less than 1 nm.
Optionally, before step S2, the substrate to be processed is placed on a special grinding tool, and vacuum adsorption is adopted. A polyurethane disc on a wafer thinning machine is installed, a swing arm is installed, a grinding liquid is a cerium oxide suspension with the particle size of 3 microns, a chemical corrosion liquid is a mixed solution of a nanometer-level silicon oxide suspension, hydrogen peroxide and water, the dripping speed of the cerium oxide suspension is 40-60 drops/min, the dripping speed of the chemical corrosion liquid is 60-120 drops/min, the grinding rotating speed is 20-50 revolutions/min, and the mode range height of the surface of a substrate and the thickness difference value of the highest pattern are controlled within a required range. And (4) after grinding, washing with deionized water, wiping with a dust-free cloth in the washing process, and finally, purging with nitrogen.
Further, the chemical etching solution in step S2 is prepared from a silicon oxide suspension: hydrogen peroxide: and (5) water, 20, (6-10) and 80.
Further, before the step S4, the polyurethane disk of the wafer thinning machine is replaced, the soft flannelette disk is installed, and the swing arm is installed. The chemical mechanical polishing process is divided into two parts: primary chemical mechanical polishing and secondary chemical mechanical polishing.
Further, the primary chemical mechanical polishing and the secondary chemical mechanical polishing specifically comprise the following processes:
and (2) performing primary chemical mechanical polishing, wherein the polishing solution is a cerium oxide suspension with the particle size of 3 mu m and a mixed solution of a nano-grade silicon oxide suspension, hydrogen peroxide and water, the polishing rotation speed is 60-100 r/min, the adding weight is 3-5kg, the dropping speed of the cerium oxide suspension is 40-60 drops/min, the dropping speed of the silicon oxide mixed polishing solution is 60-120 drops/min, and the polishing time is 10-15 min.
And (3) performing secondary chemical mechanical polishing, wherein the polishing solution is a mixed solution of a nano-grade silicon oxide turbid liquid, hydrogen peroxide and water, and stopping dripping of the cerium oxide turbid liquid during the secondary chemical mechanical polishing, wherein the polishing rotating speed is 60-100 revolutions per minute, the added balance weight is 5-8 kg, and the polishing time is 10-30 min.
Optionally, the polishing solution in step S4 includes a silicon oxide suspension: hydrogen peroxide: and (5) 80 parts of water, wherein the weight of the water is 20, (1-5).
As shown in FIG. 2, the base body includes a surface heterogeneous pattern 1 and a semiconductor substrate 2, and the surface heterogeneous pattern 1 is provided on the upper surface of the semiconductor substrate 2.
As shown in FIG. 3, the surface heterogeneous pattern 1 includes a surface photoresist 11 and a surface metal 12, the surface metal 12 is a plurality of columnar structures vertical to the semiconductor substrate 2, the surface photoresist 11 fully covers the upper surface of the semiconductor substrate 2 and fills the gaps between the surface metals 12.
And placing the semiconductor substrate to be processed on a special thickness measuring tool, and fixing the semiconductor substrate by adopting a vacuum adsorption mode.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.
Claims (8)
1. A method for quickly thinning and polishing a surface heterostructure is characterized by comprising the following steps: the method comprises the following steps:
s1, using a thickness gauge to measure the thickness of the wafer surface heterogeneous pattern (1) to be processed of the substrate, and recording the height of the highest pattern of the surface heterogeneous pattern (1) and the mode range height in the surface heterogeneous pattern (1);
s2, mounting a polyurethane disc on a wafer thinning machine, and chemically thinning and mechanically thinning the substrate through the polyurethane disc;
s3, measuring the highest pattern height and mode range height in the surface heterogeneous pattern (1) of the substrate subjected to the primary chemical thinning and the mechanical thinning by using the thickness gauge, and if the thickness difference value exceeds a thinning preset value, performing S2; if the measured thickness difference value meets the requirement of the preset thinning value, performing step S4;
s4, detaching the polyurethane disc on the wafer thinning machine, installing a soft polishing flannelette disc on the wafer thinning machine, and performing chemical polishing and mechanical polishing on the substrate by using the soft polishing flannelette disc for polishing;
s5, measuring the thickness of the surface heterogeneous pattern (1) on the upper surface of the semiconductor substrate (2) after mechanical and chemical polishing by using the thickness gauge, and if the thickness difference of the surface heterogeneous pattern (1) exceeds the preset polishing value, repeating the step S4; if the measured thickness difference and the overall height of the surface heterogeneous pattern (1) meet the preset polishing value requirement, performing step S6;
and S6, finishing the thinning and polishing of the substrate.
2. The method for rapidly thinning and polishing the surface heterostructure according to claim 1, wherein: the base body comprises a surface heterogeneous pattern (1) and a semiconductor substrate (2), wherein the surface heterogeneous pattern (1) is arranged on the upper surface of the semiconductor substrate (2); the surface heterogeneous pattern (1) comprises a surface photoresist (11) and surface metals (12), the surface metals (12) are vertical to the semiconductor substrate (2) in a columnar structure, and the surface photoresist (11) is fully distributed on the upper surface of the semiconductor substrate (2) and fills gaps among the surface metals (12).
3. The method for rapidly thinning and polishing the surface heterostructure according to claim 1, wherein: in the step S3, the preset thinning value is 0-30 μm.
4. The method for rapidly thinning and polishing the surface heterostructure according to claim 1, wherein: the chemical thinning and the mechanical thinning, the chemical polishing and the mechanical polishing removal rates are the same.
5. The method for rapidly thinning and polishing the surface heterostructure according to claim 1, wherein: the surface roughness of the surface heterogeneous pattern (1) after the chemical polishing and the mechanical polishing in the step S4 is less than 1 nm.
6. The method for rapidly thinning and polishing the surface heterostructure according to claim 1, wherein: the preset polishing value in the step S5 is 0-1 μm.
7. The method for rapidly thinning and polishing the surface heterostructure according to claim 2, wherein: and in the polishing process in the step S4, the stretching ratio of the surface metal (12) structure in the length direction of the graph is controlled within 3 percent.
8. The method for rapidly thinning and polishing the surface heterostructure according to claim 1, wherein: the polishing liquid used for the chemical thinning and the chemical polishing is a chemical agent capable of selectively corroding metal.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113526459A (en) * | 2021-07-16 | 2021-10-22 | 西南交通大学 | Surface planarization method for micro-scale 3D printing copper/nickel heterogeneous microstructure |
| CN114952600A (en) * | 2022-07-11 | 2022-08-30 | 赛莱克斯微系统科技（北京）有限公司 | Flattening method and device for high-frequency transmission microstructure and electronic equipment |
Citations (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10144634A (en) * | 1996-11-01 | 1998-05-29 | Ind Technol Res Inst | Chemical-mechanical polishing apparatus and method |
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