CN112562572A - Source driver and channel selection method thereof - Google Patents
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The invention discloses a source driver and a channel selection method thereof, wherein the channel selection method of the source driver comprises the steps of receiving a driving instruction, dividing the driving instruction into a bit mode and a packet mode according to a reading time sequence, counting the bit number of pixel data packets by a counter when the source driver is in the packet mode, calculating the bit number to be a multiple of the data quantity of sub-pixels, selecting a plurality of data channels corresponding to the number of the selected channels by a selection circuit by taking the multiple as the selection of the channel quantity, and transmitting a source driving signal to a sub-pixel row by the plurality of data channels.
Description
Technical Field
The present invention relates to a source driver and a channel selection method thereof, and more particularly, to a source driver and a channel selection method thereof, which can automatically select the number of channels to reduce the chip development cost, and are suitable for different resolution requirements.
Background
As the display device is continuously developing towards high resolution on the display screen, the number of channels required by the corresponding source receivers is different according to the requirement of resolution, and the number and configuration combination of the driving chips are correspondingly increased. In a general source driver chip, the setting of the channels is predefined, that is, the number of the channels used is fixed, for example, the number or the positions of the channels used is determined according to the judgment of the pins, and the source driver chip has not high commonality between display devices with different resolutions.
However, when a new resolution combination is generated, the requirement of the number of channels is changed, and the corresponding source driver chip needs to be redesigned to meet the requirement of the resolution. However, the development of corresponding driving chips aiming at different resolution requirements will greatly increase the time and cost of device development and affect the economic benefit of product development.
In view of the foregoing, the inventor of the present invention has devised and designed a source driver and a channel selection method thereof to solve the problems of the prior art and further enhance the industrial application.
Disclosure of Invention
In view of the problems of the prior art, an object of the present invention is to provide a source driver and a channel selection method thereof, which can automatically select the number of channels to be applied when panels with different resolutions require different numbers of channels, thereby solving the problem that the conventional driver chip cannot be shared and needs to be re-developed.
In view of the above, the present invention provides a channel selection method for a source driver, which is suitable for a source driver coupled to a pixel circuit. The source driver channel selection method comprises the steps that a source driver receives a driving instruction and provides source driving signals of sub-pixel columns in a pixel circuit; dividing the driving command into a bit mode and a packet mode according to the reading timing, wherein the bit mode comprises an operation command, and the packet mode comprises pixel data packets of the sub-pixel rows; the source driver reads the operation command to carry out reset action; counting the number of bits of the pixel data packet through a counter of a source driver, and calculating the number of bits as a multiple of the data quantity of the sub-pixels, wherein the multiple is used as the number of the selection channels; and generating a start pulse by a trigger circuit of the source driver according to the operation instruction, selecting a plurality of data channels corresponding to the number of the selected channels by a selection circuit of the source driver, and transmitting the source driving signal to the sub-pixel rows by the plurality of data channels.
In view of the above, the present invention provides a source driver, which includes a plurality of channels, a timing receiver, a counter, a flip-flop circuit, and a selection circuit. The channels are coupled to the pixel circuits, and the source driver transmits source driving signals to the sub-pixel rows in the pixel circuits through the channels. The timing receiver generates a read timing, and divides the driving command into a bit mode and a packet mode, wherein the bit mode comprises an operation command, and the packet mode comprises a pixel data packet of the sub-pixel row. The counter is coupled to the timing receiver, counts the number of bits of the pixel data packet, and counts the number of bits as a multiple of the amount of the sub-pixel data, and the multiple is used as the number of the selection channels. The trigger circuit is coupled to the counter and generates a start pulse according to the operation instruction. The selection circuit is coupled to the trigger circuit and the plurality of channels, selects a plurality of data channels corresponding to the number of the selection channels, and transmits the source driving signal to the sub-pixel rows through the plurality of data channels.
In an embodiment of the invention, the driving command of the data cycle includes a line data start interval, a polarity command interval, a data interval, a line data end interval and a blanking interval, and the data interval includes a pixel data packet. The trigger circuit can generate a start pulse after the reading termination interval.
In an embodiment of the present invention, the driving command may include a vertical blanking period, the driving command of the vertical blanking period includes a line data start interval, a blanking polarity command interval, and a vertical blanking data interval, and the vertical blanking data interval includes a non-integer type data packet. After the trigger circuit reads the line data starting interval and the blanking polarity instruction interval, the trigger circuit generates a starting pulse according to the number of the selection channels stored in the previous data period driving instruction.
In an embodiment of the invention, the trigger circuit may include a start pulse signal generator, the selection circuit may include a voltage level shifter, and the start pulse signal generator receives the number of the selection channels of the counter, controls the turning on and off of all the channels of the source driver through the voltage level shifter, and selects the plurality of data channels corresponding to the number of the selection channels.
In an embodiment of the invention, all channels of the source driver can form a plurality of channel groups according to a predetermined number of channels, and the voltage level converter controls the opening and closing of the plurality of channel groups and selects a plurality of data channels corresponding to the selected number of channels.
In an embodiment of the invention, the trigger circuit may include a start pulse first signal generator and a start pulse second signal generator, the selection circuit may include a first voltage level shifter and a second voltage level shifter, the start pulse first signal generator and the start pulse second signal generator receive the number of the selection channels of the counter, and respectively control the source driver to turn on and turn off the corresponding channels through the first voltage level shifter and the second voltage level shifter, so as to select the plurality of data channels corresponding to the number of the selection channels.
In an embodiment of the invention, all channels of the source driver may form a plurality of channel groups according to a predetermined number of channels, and the first voltage level shifter and the second voltage level shifter respectively control the on and off of the corresponding plurality of channel groups and select a plurality of data channels corresponding to the selected number of channels.
In summary, the source driver and the channel selection method thereof of the present invention can count the number of bits of the pixel data packet through the counter and convert the number of the bits into the number of the channels to be used without setting the selection channel of the driving chip in advance. For the displays with different resolutions, the time and cost consumed by the development of the driving chip are reduced, and the sharing of the driving chip among different displays is increased through the source driver and the channel selection method thereof.
Drawings
In order to make the technical features, contents and advantages of the present invention and the technical effects thereof more obvious, the present invention will be described with reference to the following drawings:
fig. 1 is a flowchart of a channel selection method of a source driver according to an embodiment of the invention.
FIG. 2 is a timing diagram illustrating a channel selection method of a source driver according to an embodiment of the invention.
Fig. 3A and 3B are schematic diagrams of a source driver according to a first embodiment of the invention.
Fig. 4A and 4B are schematic diagrams of a source driver according to a second embodiment of the invention.
Fig. 5A and 5B are schematic diagrams of a source driver according to a third embodiment of the invention.
Fig. 6A and 6B are schematic diagrams of a source driver according to a fourth embodiment of the invention.
Fig. 7A and 7B are schematic diagrams of a source driver according to a fourth embodiment of the invention.
Description of reference numerals:
10,20,30,40,50: source driver
11,21,31,41,51: time sequence receiver
12,22,32,42,52: counter with a memory
13,23: initial pulse signal generator
14,24: voltage level converter
15,26,35,46: delay element
25,45,55: channel group
25_1 to 25_240,45_1 to 45_240,55_1 to 55_ 240: first to 240 th channel groups
33A, 43A: initial pulse first signal generator
33B, 43B: initial pulse second signal generator
34A, 44A: first voltage level converter
34B, 44B: second voltage level converter
53_1 to 53_ 240: start pulse first signal generator to start pulse 240 signal generator
54_1 to 54_ 240: first to 240 th voltage level shifters
BAC: line data start interval
BK: covered section
BKPOL: block out polarity command interval
And (3) Bit: bit pattern
CH 1-CH 960: first to 960 th passages
DATA: data interval
DAT 1-DATN: first to Nth data cycle drive instructions
EOL: line data termination interval
POL: polarity command interval
Pkt: packet mode
STB 1-STBN, STVBK: starting pulse
S1-S5: step (ii) of
VBDATA: vertical blanking interval
VBK: driving instruction for vertical blanking period
Detailed Description
To facilitate understanding of the technical features, contents, and advantages of the present invention and the technical effects achieved thereby, the present invention will be described in detail with reference to the accompanying drawings in the form of embodiments, wherein the drawings are provided for illustration and an auxiliary specification, and are not necessarily true to scale and precise arrangement after the implementation of the present invention, and therefore, the appended claims should not be read as limiting the present invention to the actual implementation of the claims.
In the drawings, the thickness or width of the substrate, panel, region, wiring, etc. is exaggerated for clarity. Like reference numerals refer to like elements throughout the specification. It will be understood that when an element such as a substrate, panel, region or line is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected," may refer to physical and/or electrical connections. Further, "electrically connected" or "coupled" may mean that there are additional elements between the elements. Further, it will be understood that, although the terms "first", "second", "third" and/or the like may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should be used to distinguish one element, component, region, layer and/or section from another element, component, region, layer and/or section. Therefore, they are used for descriptive purposes only and not to be construed as indicating or implying relative importance or order relationships thereof.
Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Please refer to fig. 1, which is a flowchart illustrating a channel selection method of a source driver according to an embodiment of the invention. As shown in the figure, the source driver channel selection method includes the following steps (S1-S5):
step S1: the source driver receives a driving command and provides a source driving signal for a sub-pixel column in the pixel circuit. A matrix of a plurality of pixels is provided in a display area among display devices, which drives light emitting units therein through pixel circuits so that the display area can present a desired picture. The pixel circuit comprises a plurality of data lines and scanning lines, the scanning lines are connected with the grid driver, and the on or off of the transistors in the pixel circuit is controlled through scanning signals, so that whether the sub-pixels are displayed or not is controlled. The data line is connected with the source electrode driver, transmits the data signal to each sub-pixel row, provides the data voltage required by the pixel display picture and further controls the display brightness of the sub-pixels. In the present embodiment, after receiving the driving command, the source driver transmits the source driving signal to each sub-pixel row in the pixel circuit through the source driver, that is, the data signal of each row of sub-pixels is transmitted to each sub-pixel through a plurality of channels by the driving command of the data period.
Step S2: the driving command is divided into a bit mode and a packet mode according to the read timing. After receiving the driving command, the gate driver divides the driving command into a Bit mode (Bit mode) and a Packet mode (Packet mode) according to the read timing, wherein the Bit mode includes an operation command in the driving command, and the Packet mode includes a pixel data Packet of a sub-pixel row in the driving command of the data period.
Step S3: the source driver reads the operation command to perform a reset action. When the conventional source driver reads the driving command of the sub-pixels in the first row, the setting operation is performed in the bit pattern according to the operating command, and the operating command must include a channel setting pattern including information such as chip pin setting and the number of channels used by the corresponding chip, and the channel required by the source driver is set to be used as a data channel for subsequently transmitting data signals. However, in this embodiment, when the source driver reads the operation command of the sub-pixel row driving command, the source driver is in the bit mode, and only performs the reset operation according to the operation command, so that the counter performs the counting again when reading the pixel data packet, and the operation of setting the chip channel is not required when starting to execute the command.
Step S4: the number of bits of the pixel data packet is counted by a counter of the source driver, and the number of bits is counted as a multiple of the data amount of the sub-pixels, and the multiple is used as the number of the selection channels. When the source driver reads the pixel data packet of the driving instruction for driving the sub-pixel row data period, the source driver enters a packet mode, the counter counts the bit number of the pixel data packet, the pixel data packet comprises the pixel data of the sub-pixels, namely the pixel data of the red pixel, the pixel data of the green pixel and the pixel data of the blue pixel, each sub-pixel data output needs one output channel, and therefore the required channel number can be calculated by calculating the bit number to be the multiple of the sub-pixel data quantity. In this embodiment, the data size of a sub-pixel data is 9 bits (bit), so when the total number of counted bits is n times of 9 bits, the pixel circuit needs to select n channels to transmit the required pixel data.
Step S5: the trigger circuit of the source driver generates a start pulse according to the operation instruction, the selection circuit of the source driver selects a plurality of data channels corresponding to the number of the selection channels, and the plurality of data channels transmit the source driving signals to the sub-pixel rows. After the source driver reads the operation command, it will generate a start pulse through the trigger circuit, the rising edge of the pulse is to receive the pixel data, and the falling edge is to send out the pixel data, and transmit to each pixel in the sub-pixel row through the data channel selected by the selection circuit. The source driver will continue to read the driving command of the next row, and through the bit pattern reset counter, count the number of pixel data packet bits in the packet mode, and generate the start pulse to transmit the pixel data from the selected data channel to the sub-pixels of the next row.
Please refer to fig. 2, which is a timing diagram illustrating a channel selection method of a source driver according to an embodiment of the invention. As shown, the driving command may include a Data period (Data type) and a Vertical blanking period (Vertical blanking type), the driving command of the Data period includes a line Data start interval BAC, a polarity command interval POL, a Data interval Data, a line Data end interval EOL and a blanking interval BK, in this embodiment, N scan lines are shared, and the number of pixels to be transmitted in each scan line, i.e., the number of Data channels required by the source driver, is obtained by counting the number of bits in the Data interval Data through a counter.
In view of the timing diagram, when receiving the first data cycle driving command DAT1 of the data cycle, the source driver first reads a line data start interval BAC, which is the header of the command, and then a polarity command interval POL, at which the source driver is in the Bit mode Bit and the counter is in the reset phase. When reading the DATA interval DATA, the source driver switches to the packet mode Pkt, and the counter starts counting the number of bits in the DATA interval DATA, and counts the number of bits as a multiple n of the DATA amount of the sub-pixels, where the multiple n is the number of channels required by the source driver. Then, when the end interval EOL of the read line data is read, the source driver is converted to the Bit pattern Bit again, and the counter is reset to wait for the next counting. On the other hand, the trigger circuit of the source driver generates the first start pulse STB1 after the operation command of the line data end interval EOL, receives the pixel data at the rising edge of the pulse, and sends the data at the falling edge. Meanwhile, the selection circuit of the source driver selects the same number of data channels to transmit the pixel data according to the required number of channels obtained after counting by the counter.
For the channel output state of the source driver, when the first start pulse STB1 is received, the selection circuit also controls n channels of the multiple channels of the source driver according to the number of the selected channels (control operation Hi-z), i.e., turns on the data channels corresponding to the number of the selected channels, turns off the remaining channels, and allows the pixel data to be transmitted to each sub-pixel in the first row through the selected data channels when the pixel data is sent out.
After the first data period driving command DAT1, the second data period driving command DAT2 continues until the nth data period driving command DATN, completing one scan period from the first scan line to the last scan line. The second DATA period driving command DAT2, up to the nth DATA period driving command DATN, and the first DATA period driving command DAT1 belong to driving commands of a DATA period, and also include a line DATA start interval BAC, a polarity command interval POL, a DATA interval DATA, a line DATA end interval EOL, and a blanking interval BK, when the DATA interval DATA is read, the source driver is in a packet mode Pkt, and the rest are in Bit modes Bit, and in the packet mode, the counter counts the number of bits of pixel DATA in the DATA interval DATA, and determines the number of selected channels by calculating the number of bits as a multiple of the amount of sub-pixel DATA, and the operation is similar to that of the first DATA period driving command DAT1, and the same contents are not described repeatedly. Through the conversion of the driving command of the data cycle, the channels of the source driver output the pixel data signals of the second column to the last column in sequence.
The driving command VBK for the vertical blanking period includes a line data start interval BAC, a blanking polarity command interval BKPOL, and a vertical blanking data interval VBDATA, where the line data start interval BAC is the same as the line data start interval BAC of the data period and is also a header of the command, and unlike the driving command for the data period, the driving command VBK for the vertical blanking period includes the blanking polarity command interval BKPOL and the vertical blanking data interval VBDATA including non-integer data packets, and the non-integer data indicates that data in the vertical blanking data interval VBDATA is not a multiple of the amount of sub-pixel data, for example, is not a multiple of 9 bits. On the other hand, the driving command VBK of the vertical blanking period does not have the line data end interval EOL, and unlike the driving command of the data period, the trigger circuit cannot generate the start pulse after the operation command of the line data end interval EOL, so in the driving command VBK of the vertical blanking period, after the driving circuit generates the start pulse STVBK according to the number of the selected channels stored in the driving command of the previous data period after the line data start interval BAC and the blanking polarity command interval BKPOL, the counter receives the data of the vertical blanking data interval VBDATA at the rising edge of the pulse, and sends out the data at the falling edge. In the channel output state of the source driver, the vertically shaded gray-scale data is output.
After outputting the vertical blanking data, the first data period driving command DAT1 is received again, the reset operation and the counting operation of the counter are performed according to the timing reading driving command and the same Bit pattern Bit and packet pattern Pkt, the number of the selected channels is determined according to the counting result of the counter, and the pixel data of the first row is output to each sub-pixel.
Please refer to fig. 3A and fig. 3B, which are schematic diagrams of a source driver according to a first embodiment of the invention. Fig. 3A is a schematic diagram of the number of channels 956, and fig. 3B is a schematic diagram of the number of channels 480. As shown, the source driver 10 includes a plurality of channels CH 1-CH 960 coupled to the pixel circuits of the display for transmitting the source driving signals to the sub-pixel rows of the pixel circuits. In this embodiment, the number of channels of the driver chip design is 960, but the disclosure is not limited thereto, and in other embodiments, the number of channels of the driver chip may vary according to the resolution of the display, for example, the number of channels may be 726, 864, or 966.
The source driver 10 is further provided with a timing receiver 11, a counter 12, a start pulse signal generator 13, and a voltage level shifter 14. The timing receiver 11 generates a read timing to divide the driving commands into bit patterns and packet patterns, where the bit patterns include operation commands in the driving commands, such as a line data start interval, a polarity command interval, a line data end interval and a blanking interval in the driving commands of a data cycle, or a line data start interval and a blanking polarity command interval in the driving commands of a vertical blanking cycle. The packet mode includes pixel data packets of the sub-pixel rows, such as data intervals in the driving command of the data cycle or vertical blanking data intervals in the driving command of the vertical blanking cycle.
The counter 12 is coupled to the timing receiver 11, and when the bit mode is selected, the counter 12 performs a reset operation, and when the packet mode is switched, the counter 12 counts the number of bits of the pixel data packet and counts the number of bits as a multiple of the amount of the sub-pixel data, and the multiple is used as the number of the selected channels. The start pulse signal generator 13 is coupled to the counter 12 and serves as a trigger circuit of the source driver 10 for generating a start pulse according to an operation command. When the driving command is a data cycle, the start pulse signal generator 13 generates a start pulse after the reading termination interval; when the driving command is a vertical blanking period, the start pulse signal generator 13 generates a start pulse according to the number of the selected channels stored in the driving command of the previous data period after the start interval of the read line data and the blanking polarity command interval. The voltage level shifter 14 is coupled to the start pulse signal generator 13 and the channels CH 1-CH 960, and the voltage level shifter 14 selects the corresponding data channels according to the number of the selected channels, and transmits the source driving signals to the sub-pixel rows through the data channels. In this embodiment, the start pulse signal generator 13 generates the start pulse after reading the line data termination interval in the driving command of the data cycle under the driving command of the data cycle, and generates the start pulse after reading the line data start interval and the blanking polarity command interval in the driving command under the driving command of the vertical blanking cycle. The voltage level shifter 14 is connected to a plurality of channels CH 1-CH 960 of the source driver 10, so that the source driving signals can be sequentially transmitted from each channel to each sub-pixel with a delay time through the delay element 15 formed between the channels.
Referring to fig. 3A, the source driver 10 includes a first channel CH1 to a 960 th channel CH960, when the number of selected channels obtained by the counter 12 is 956, the start pulse signal generator 13 generates a start pulse to receive pixel data of the first channel CH1 to the 956 th channel CH956, and the voltage level shifter 14 controls to turn off the 957 th channel CH957 to the 960 th channel CH960, so that the pixel data can be transmitted to the sub-pixels through the selected first channel CH1 to the 956 th channel CH956 when the start pulse outputs the entire column of signals.
Referring to fig. 3B, when the counter 12 of the source driver 10 obtains the number of the selected channels 480, the start pulse signal generator 13 generates the start pulse to receive the pixel data of the first channel CH1 to the 480 th channel CH480, and the voltage level shifter 14 controls the 481 channel CH481 to the 960 th channel CH960 to be turned off, so that the pixel data can be transmitted to the sub-pixels through the selected first channel CH1 to the 480 th channel CH480 when the start pulse outputs the entire column of signals.
As described in the foregoing embodiments, when the source driver 10 is configured in displays with different resolutions, the chips of the source driver 10 often need to be re-developed due to different numbers of data channels, so that the number of the channels meets the requirement of the resolution, but the display has a wide variety of resolutions, and developing the driving chips according to the resolutions will greatly increase the development time and cost. In this embodiment, the content of the data interval in the driving signal can be analyzed by setting the counter 12, the number of the required data channels can be determined, and the channels can be controlled to be turned on and off by the voltage level shifter 14, so that the channels corresponding to the resolution of the display can correctly transmit the pixel data to each sub-pixel. Therefore, the same source driver 10 can be applied to displays with different resolutions, thereby greatly improving the commonality of the source driver 10 and reducing the time and cost required for developing the driving chip.
Please refer to fig. 4A and 4B, which are schematic diagrams illustrating a source driver according to a second embodiment of the invention. Fig. 4A is a schematic diagram of the number of channels 956, and fig. 4B is a schematic diagram of the number of channels 480. As shown, the source driver 20 includes 960 channels, i.e., a first channel CH1 through a 960 th channel CH960, which are coupled to the pixel circuits of the display for transmitting the source driving signals to the sub-pixel rows of the pixel circuits. The source driver 20 is provided with a timing receiver 21, a counter 22, a start pulse signal generator 23 and a voltage level shifter 24, wherein the start pulse signal generator 23 is a trigger circuit of the source driver 20 for generating a start pulse, and the voltage level shifter 24 is a selection circuit of the source driver 20. The source driver 20 is configured and channel-selected in a similar manner to the previous embodiments, and the same contents will not be described again.
In the present embodiment, 960 channels CH 1-CH 960 of the source driver 20 form 240 channel groups 25 by grouping every 4 channels, and one channel group 25 controls 4 channels, for example, the first channel group 25_1 controls the first channel CH1 to the fourth channel CH4, the second channel group 25_2 controls the fifth channel CH5 to the eighth channel CH8, and so on, until the 240 channel group 25_ 240. A delay element 26 is formed between each channel group 25 so that the respective channel groups can sequentially transfer pixel data by the controlled channels with delay time. After the counter 22 counts and determines the required number of channels, the voltage level shifter 24 controls the channel groups 25 to turn on and off, i.e. 4 channels in the channel groups 25 are turned on or off simultaneously, and then selects the data channel corresponding to the required number of channels to transmit the pixel data. In the embodiment, one channel group 25 is formed by 4 channels, but the embodiment is not limited thereto, and the source driver 20 may need to select different predetermined channel numbers to form the channel group 25, which is expected to make the circuit layout of the source driver 20 more efficient and help to simplify the process complexity.
Referring to fig. 4A, when the number of selected channels obtained by the counter 22 is 956, the voltage level shifter 24 turns off the 240 th channel group 25_240 and turns on the first channel group 25_1 to the 239 th channel group 25_239, so that the source driver 20 has 956 channels turned on (CH 1-CH 956) to transmit the pixel data to the sub-pixels. Referring to fig. 4B, when the number of selected channels obtained by the counter 22 of the source driver 20 is 480, the voltage level shifter 24 turns off the 121 th channel set 25_121 to the 240 th channel set 25_240 in the second half and turns on the first channel set 25_1 to the 120 th channel set 25_120 in the first half, so that the source driver 20 has 480 channels (CH 1-CH 480) capable of transmitting pixel data to the sub-pixels.
Please refer to fig. 5A and 5B, which are schematic diagrams illustrating a source driver according to a third embodiment of the invention. Fig. 5A is a schematic diagram of the number of channels 956, and fig. 5B is a schematic diagram of the number of channels 480. As shown, the source driver 30 includes 960 channels, i.e., a first channel CH1 through a 960 th channel CH960, which are coupled to the pixel circuits of the display for transmitting the source driving signals to the sub-pixel rows of the pixel circuits. The source driver 30 is provided with a timing receiver 31, a counter 32, a start pulse first signal generator 33A, a start pulse second signal generator 33B, a first voltage level shifter 34A and a second voltage level shifter 34B, wherein the start pulse first signal generator 33A is a trigger circuit of the source driver 30 and generates a start pulse of a first channel CH1 to a 480 th channel CH480, the first voltage level shifter 34A is a selection circuit of the source driver 30 and connects the first channel CH1 to the 480 th channel CH480, and a delay element 35 is formed between the channels, so that the first channel CH1 to the 480 th channel CH480 can be sequentially turned on and off under the control of a delay time. The start pulse second signal generator 33A is also a trigger circuit of the source driver 30, and generates start pulses for the 481 th channel CH481 to the 960 th channel CH960, and the second voltage level shifter 34B is a selection circuit of the source driver 30, and connects the 481 th channel CH481 to the 960 th channel CH960, and also forms a delay element 35 between the channels, so that the 481 st channel CH481 to the 960 th channel CH960 are sequentially turned on and off under the control of a delay time.
The timing receiver 31 and the counter 32 of the source driver 30 are similar to the previous embodiments, and the same channel selection manner is not repeated. In the present embodiment, the first start pulse signal generator 33A and the first voltage level shifter 34A are responsible for the data channel of the first half, and the second start pulse signal generator 33B and the second voltage level shifter 34B are responsible for the data channel of the second half. Referring to fig. 5A, when the number of the selected channels obtained by the counter 32 is 956, the start pulse first signal generator 33A generates start pulses to receive the pixel data of the first channel CH1 through the 480 th channel CH480, and the first voltage level shifter 34A controls to turn on the first channel CH1 through the 480 th channel CH 480. The start pulse second signal generator 33B also generates a start pulse, receives pixel data of the 481 th channel CH481 to the 956 th channel CH956, turns on the 481 th channel CH481 to the 956 th channel CH956, turns off the 957 th channel CH957 to the 960 th channel CH960, and when the start pulse outputs the entire column signal, the pixel data can be transferred to the sub-pixels through the turned-on first channel CH1 to the 956 th channel CH 956.
Referring to fig. 5B, when the number of the selected channels obtained by the counter 32 of the source driver 30 is 480, the start pulse first signal generator 33A generates the start pulse to receive the pixel data of the first channel CH1 through the 480 th channel CH480, and the first voltage level shifter 34A controls the first channel CH1 through the 480 th channel CH480 to be turned on. The start pulse the second signal generator 33B also generates the start pulse, but the second voltage level shifter 34B controls the 481 th channel CH481 to 960 th channel CH960 to be turned off, and when the start pulse outputs the entire column signal, the pixel data is transferred to the sub-pixels only through the first channel CH1 to the 480 th channel CH480 which are turned on in the first half. In the present embodiment, the source driver 30 is provided with two sets of flip-flop circuits and selection circuits, but the disclosure is not limited thereto, and in other embodiments, the source driver 30 may be provided with more than two sets of flip-flop circuits and selection circuits respectively responsible for controlling and transmitting data of corresponding channels.
Please refer to fig. 6A and 6B, which are schematic diagrams illustrating a source driver according to a fourth embodiment of the invention. Fig. 6A is a schematic diagram of the number of channels 956, and fig. 6B is a schematic diagram of the number of channels 480. As shown, the source driver 40 includes 960 channels, i.e., a first channel CH1 to a 960 th channel CH960, which form 240 channel groups 45 in a group of every 4 channels, and the 4 channels are controlled by one channel group 45, such as the first channel group 45_1 to the 240 th channel group 45_240 shown in the figure, and a delay element 46 is formed between each channel group 45, so that the respective channel groups can sequentially transmit pixel data through the controlled channels according to the delay time. The source driver 40 is provided with a timing receiver 41, a counter 42, a start pulse first signal generator 43A, a start pulse second signal generator 43B, a first voltage level shifter 44A and a second voltage level shifter 44B, wherein the start pulse first signal generator 43A is a trigger circuit of the source driver 40 and generates start pulses of a first channel CH1 to a 480 th channel CH480, and the first voltage level shifter 44A is a selection circuit of the source driver 40 and is connected to the channel group 45 of the first half section to control the on and off of the channel groups 45_1 to 45_ 120. The start pulse second signal generator 43A is also a trigger circuit of the source driver 40, and generates start pulses of the 481 channel CH481 to the 960 channel CH960, and the second voltage level shifter 44B is a selection circuit of the source driver 40, connected to the channel group 45 of the second half, and controls the channel groups 45_121 to 240 channel groups 45_240 to be turned on and off.
The timing receiver 41 and the counter 42 of the source driver 40 are similar to the previous embodiments, and the same channel selection manner is not repeated. In the present embodiment, the first start pulse signal generator 43A and the first voltage level shifter 44A are responsible for the first half of the channel group 45, and the second start pulse signal generator 43B and the second voltage level shifter 44B are responsible for the second half of the channel group 45. Referring to fig. 6A, when the number of the selected channels obtained by the counter 42 is 956, the start pulse first signal generator 43A generates start pulses to receive the pixel data of the first channel CH1 through the 480 th channel CH480, and the first voltage level shifter 44A turns on the first half of the channel group 45, i.e., turns on the first channel group 45_1 through the 120 th channel group 45_ 120. The start pulse second signal generator 43B also generates a start pulse, receives the pixel data of the 481 channel CH481 to the 956 channel CH956, and turns on the first 119 channel groups 45 of the second half by the second voltage level shifter 44B, i.e., turns on the 121 channel groups 45_121 to the 239 channel groups 45_239, and turns off the last channel group 45_240 of the second half. When the start pulse outputs the entire column signal, the pixel data can be transferred to the sub-pixels through the turned-on first channel CH1 to the 956 channel CH 956.
Referring to fig. 6B, when the number of the selected channels obtained by the counter 42 of the source driver 40 is 480, the start pulse first signal generator 43A generates the start pulse to receive the pixel data of the first channel CH1 to the 480 th channel CH480, and the first voltage level shifter 44A turns on the first half of the channel group 45, i.e., turns on the first channel group 45_1 to the 120 th channel group 45_ 120. The start pulse second signal generator 43B also generates the start pulse, but the second voltage level shifter 34B turns off the 121 th channel set 45_121 to the 240 th channel set 45_240 in the second half, and when the start pulse outputs the entire column signal, the pixel data is transmitted to the sub-pixels only through the first channel set 45_1 to the 120 th channel set 45_120 in the first half, i.e., through the first channel CH1 to the 480 th channel CH 480.
Please refer to fig. 7A and 7B, which are schematic diagrams illustrating a source driver according to a fifth embodiment of the invention. Fig. 7A is a schematic diagram of the number of channels 956, and fig. 7B is a schematic diagram of the number of channels 480. As shown, the source driver 50 includes 960 channels, i.e., a first channel CH1 to a 960 th channel CH960, which form 240 channel groups 55 by grouping every 4 channels, and one channel group 55 controls 4 channels, such as the first channel group 55_1 to the 240 th channel group 55_240 shown in the figure. The source driver 50 is provided with a timing receiver 51 and a counter 52, which are similar to the previous embodiments, and the same channel selection manner will not be repeated.
In the present embodiment, the source driver 50 is provided with a start pulse first signal generator 53_1 to a start pulse 240 signal generator 53_240 and a first voltage level shifter 54_1 to a 240 voltage level shifter 54_240 corresponding to the number of the channel groups 55, wherein the start pulse first signal generator 53_1 is a trigger circuit of the source driver 50 for generating start pulses of the first channel CH1 to the 4 th channel CH4, and the first voltage level shifter 54_1 is a selection circuit of the source driver 50 connected to the first channel group 55_1 for controlling the on and off of the first channel CH1 to the 4 th channel CH 4. Since each channel group 55 is controlled by a respective voltage level shifter, no delay element is required to be formed between the channel groups 55 as described in the previous embodiments, and the channel groups 25 are controlled to be turned on and off only by the corresponding voltage level shifters.
Referring to fig. 7A, when the number of selected channels obtained by the counter 52 is 956, the start pulse first signal generator 53_1 to the start pulse 240 signal generator 53_240 generate start pulses to receive pixel data of the first channel CH1 to the 956 channel CH956, the first voltage level converter 54_1 to the 239 voltage level converter 54_239 turn on the first channel set 55_1 to the 239 channel set 55_239, and the pixel data are sequentially transferred to the sub-pixels through the turned-on first channel CH1 to the 956 channel CH 956.
Referring to fig. 7B, when the number of selected channels obtained by the counter 52 is 480, the start pulse first signal generator 53_1 to the start pulse 240 signal generator 53_240 generate start pulses to receive the pixel data of the first channel CH1 to the 480 th channel CH480, the first voltage level converter 54_1 to the 120 th voltage level converter 54_120 turns on the first channel set 55_1 to the 120 th channel set 55_120, and the pixel data are sequentially transmitted to the sub-pixels through the turned-on first channel CH1 to the 480 th channel CH 480.
The foregoing is by way of example only, and not limiting. Any equivalent modifications or variations without departing from the spirit and scope of the present invention should be included in the claims.
Claims (16)
1. A method for selecting a channel of a source driver, the method being applied to a source driver coupled to a pixel circuit, the method comprising:
the source driver receives a driving instruction and provides a source driving signal of a sub-pixel row in the pixel circuit;
dividing the driving command into a bit mode and a packet mode according to the reading timing, wherein the bit mode comprises an operation command, and the packet mode comprises a pixel data packet of the sub-pixel row;
the source driver reads the operation command to perform a reset action;
counting a bit number of the pixel data packet by a counter of the source driver, and calculating the bit number as a multiple of a sub-pixel data amount, wherein the multiple is used as a selection channel number; and
and generating a starting pulse by a trigger circuit of the source driver according to the operation instruction, selecting a plurality of data channels corresponding to the number of the selected channels by a selection circuit of the source driver, and transmitting the source driving signal to the sub-pixel row by the plurality of data channels.
2. The method of claim 1, wherein the driving command comprises a data cycle, the driving command of the data cycle comprises a line data start interval, a polarity command interval, a data interval, a line data end interval and a blanking interval, the data interval comprises the pixel data packet.
3. The method of claim 2, wherein the trigger circuit generates the start pulse after reading the end interval.
4. The method of claim 1, wherein the driving command comprises a vertical blanking period, the driving command of the vertical blanking period comprises a line data start interval, a blanking polarity command interval, and a vertical blanking data interval, and the vertical blanking data interval comprises non-integer data packets.
5. The method of claim 4, wherein the trigger circuit generates the enable pulse according to the number of selected channels stored in a previous data cycle driving command after reading the line data start interval and the blanking polarity command interval.
6. The method of claim 1, wherein the trigger circuit comprises a start pulse signal generator, the selection circuit comprises a voltage level shifter, the start pulse signal generator receives the number of selected channels of the counter, controls all channels of the source driver to be turned on and off through the voltage level shifter, and selects the data channels corresponding to the number of selected channels.
7. The method as claimed in claim 6, wherein all channels of the source driver form a plurality of channel groups according to a predetermined number of channels, the voltage level shifter controls the turning on and off of the plurality of channel groups, and the plurality of data channels corresponding to the selected number of channels are selected.
8. The method of claim 1, wherein the trigger circuit comprises a first start pulse signal generator and a second start pulse signal generator, the selection circuit comprises a first voltage level shifter and a second voltage level shifter, the first start pulse signal generator and the second start pulse signal generator receive the number of selected channels of the counter, and the first voltage level shifter and the second voltage level shifter control the on and off of the corresponding channels of the source driver respectively to select the number of data channels corresponding to the number of selected channels.
9. The method of claim 8, wherein all channels of the source driver form a plurality of channel groups according to a predetermined number of channels, the first voltage level shifter and the second voltage level shifter control the corresponding channel groups to turn on and off respectively, and the data channels corresponding to the number of selected channels are selected.
10. A source driver, comprising:
the source drive transmits a source drive signal to a sub-pixel row in the pixel circuit through the plurality of channels;
a timing receiver for generating a read timing to divide a driving command into a bit pattern and a packet pattern, wherein the bit pattern comprises an operation command, and the packet pattern comprises a pixel data packet of the sub-pixel row;
a counter, coupled to the timing receiver, for counting a bit number of the pixel data packet and calculating the bit number as a multiple of a sub-pixel data amount, the multiple being used as a selection channel number;
a trigger circuit coupled to the counter for generating a start pulse according to the operation command; and
and the selection circuit is coupled with the trigger circuit and the channels, selects a plurality of data channels corresponding to the number of the selection channels, and transmits the source driving signal to the sub-pixel row through the plurality of data channels.
11. The source driver as claimed in claim 10, wherein the driving command comprises a data cycle, the driving command of the data cycle comprises a line data start interval, a polarity command interval, a data interval, a line data end interval and a blanking interval, the data interval comprises the pixel data packet.
12. The source driver as claimed in claim 10, wherein the driving command comprises a vertical blanking period, the driving command for the vertical blanking period comprises a line data start interval, a blanking polarity command interval and a vertical blanking data interval, and the vertical blanking data interval comprises non-integer data packets.
13. The source driver as claimed in claim 10, wherein the triggering circuit comprises a start pulse signal generator, the selecting circuit comprises a voltage level shifter, the start pulse signal generator receives the number of the selected channels of the counter, controls the on and off of the channels through the voltage level shifter, and selects the data channels corresponding to the number of the selected channels.
14. The method of claim 13, wherein the plurality of channels form a plurality of channel groups according to a predetermined number of channels, the voltage level shifter controls the plurality of channel groups to turn on and off, and the plurality of data channels corresponding to the selected number of channels are selected.
15. The method of claim 10, wherein the trigger circuit comprises a first start pulse signal generator and a second start pulse signal generator, the selection circuit comprises a first voltage level shifter and a second voltage level shifter, the first start pulse signal generator and the second start pulse signal generator receive the number of selected channels of the counter, and the first voltage level shifter and the second voltage level shifter control the corresponding channels to be turned on and off respectively to select the data channels corresponding to the number of selected channels.
16. The method of claim 15, wherein the plurality of channels form a plurality of channel groups according to a predetermined number of channels, the first voltage level shifter and the second voltage level shifter control the corresponding channel groups to turn on and off respectively, and the plurality of data channels corresponding to the number of selected channels are selected.
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| CN116913220A (en) * | 2023-07-14 | 2023-10-20 | 北京显芯科技有限公司 | Data transmission method, backlight controller and display device |
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| TW202207194A (en) | 2022-02-16 |
| CN112562572B (en) | 2023-11-17 |
| TWI731766B (en) | 2021-06-21 |
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