CN112560647A - Fingerprint identification circuit structure, device and driving method - Google Patents

Abstract

The invention relates to the technical field of fingerprint identification, and provides a fingerprint identification circuit structure, a fingerprint identification circuit device and a driving method. The fingerprint identification circuit structure comprises an ultrasonic transmitting and receiving element, a detection circuit and a signal output circuit; the ultrasonic transmitting and receiving element comprises a transmitting electrode, a piezoelectric layer and a receiving electrode which are sequentially stacked, the receiving electrode is electrically connected with the sampling node, and the ultrasonic transmitting and receiving element is configured to send out ultrasonic waves when receiving a preset electric signal and output corresponding voltage signals according to the received ultrasonic waves; the detection circuit is electrically connected with the sampling node and is configured to store the peak value of the voltage signal output by the receiving electrode at the sampling node as a sensing voltage; the signal output circuit is electrically connected to the sampling node, and the signal output circuit is configured to amplify the sensing voltage and to flow an amplified sensing current to the output node according to the amplified sensing voltage. Amplifying the sensing voltage by the signal output circuit reduces the on-resistance and reduces the power consumption.

Description

Fingerprint identification circuit structure, device and driving method

Technical Field

The present invention relates to the field of fingerprint identification technologies, and in particular, to a fingerprint identification circuit structure, a fingerprint identification device including the fingerprint identification circuit structure, and a method for driving the fingerprint identification circuit structure.

Background

Fingerprint identification is widely applied as a convenient and safe authority authentication mode, wherein the application of a fingerprint identification device based on the piezoelectric ultrasonic principle to mobile equipment has more development prospect. The piezoelectric ultrasonic fingerprint identification works by utilizing the positive piezoelectric effect and the inverse piezoelectric effect of a piezoelectric material, and the detection of a fingerprint image is realized by detecting the reflection intensity difference of an ultrasonic signal on a glass-finger interface.

When implementing a large-sized fingerprint identification device, there are hundreds or even tens of thousands of identical fingerprint detection units, i.e., pixels; the signal detection and processing circuit cannot process the output signals of all the pixel circuits at the same time, so a corresponding circuit unit is generally arranged below each pixel, and the piezoelectric element of each pixel converts the sound pressure into an electric signal and then enters the corresponding circuit unit to realize the acquisition, maintenance and transmission of the electric signal. At present, a circuit unit adopting a TFT (Thin Film Transistor) process has the advantages of low cost and easy large-scale integration, but the TFT switching characteristics are poor: the speed is low, and signals in a megahertz frequency band cannot be directly processed; the leakage is large, which is not beneficial to signal preservation; the on-resistance is large, the power consumption is large, and especially the power consumption of a large-scale array is larger.

The above information disclosed in the background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art that is known to a person of ordinary skill in the art.

Disclosure of Invention

The present invention is directed to overcome the above-mentioned disadvantage of the prior art that the on-resistance is large, and to provide a fingerprint identification circuit structure having a small on-resistance, a fingerprint identification device including the fingerprint identification circuit structure, and a method for driving the fingerprint identification circuit structure.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

According to an aspect of the present disclosure, there is provided a fingerprint identification circuit structure, including:

the ultrasonic transmitting and receiving element comprises a transmitting electrode, a piezoelectric layer and a receiving electrode which are sequentially stacked, wherein the receiving electrode is electrically connected with the sampling node, and the ultrasonic transmitting and receiving element is configured to send out ultrasonic waves when receiving a preset electric signal and output corresponding voltage signals according to the received ultrasonic waves;

a detection circuit electrically connected to a sampling node, the detection circuit configured to store a peak value of the voltage signal output by the receiving electrode at the sampling node as a sensing voltage;

and the signal output circuit is electrically connected with the sampling node, is configured to amplify the sensing voltage and flow amplified sensing current into the output node according to the amplified sensing voltage.

In an exemplary embodiment of the present disclosure, the signal output circuit includes:

the boosting sub-circuit is electrically connected with the sampling node and the detection control terminal and is configured to boost the sensing voltage of the sampling node according to a signal of the detection control terminal;

the detection sub-circuit is electrically connected with the sampling node, the power supply end and the intermediate node and is configured to output the amplified sensing current to the intermediate node according to the boosted sensing voltage;

and the first switch sub-circuit is electrically connected with the detection control end, the intermediate node and the output node and is configured to respond to a signal of the detection control end to control the connection and disconnection between the intermediate node and the output node.

In an exemplary embodiment of the disclosure, the boost sub-circuit includes a bootstrap capacitor, a first pole of the bootstrap capacitor is electrically connected to the detection control terminal, and a second pole of the bootstrap capacitor is electrically connected to the sampling node.

In an exemplary embodiment of the present disclosure, the boost sub-circuit includes a boost transistor, a first pole and a second pole of the boost transistor are both electrically connected to the detection control terminal, and a control pole of the boost transistor is electrically connected to the sampling node.

In an exemplary embodiment of the present disclosure, the detection sub-circuit comprises a detection transistor, a control electrode of the detection transistor is electrically connected to the sampling node, a first electrode of the detection transistor is electrically connected to the power supply terminal, and a second electrode of the detection transistor is electrically connected to the intermediate node;

the first switch sub-circuit comprises a first switch transistor, a control electrode of the first switch transistor is electrically connected with the detection control end, a first electrode of the first switch transistor is electrically connected with the intermediate node, and a second electrode of the first switch transistor is electrically connected with the output node.

In an exemplary embodiment of the present disclosure, the detection circuit includes a reset sub-circuit electrically connected to a bias terminal, a reset control terminal and the sampling node, and configured to supply a bias voltage provided from the bias terminal to the sampling node in response to a control of the reset control terminal.

In an exemplary embodiment of the present disclosure, the detection circuit further includes a second switch sub-circuit, which is electrically connected to the first sampling node, the second sampling node and the switch control terminal, and configured to control on/off between the first sampling node and the second sampling node in response to a signal of the switch control terminal; the first sampling node is closer to the ultrasonic transmitting and receiving element relative to the second sampling node, and the reset sub-circuit is electrically connected with the first sampling node.

According to an aspect of the present disclosure, a fingerprint identification device is provided, which includes any one of the above fingerprint identification circuit structures, and the fingerprint identification circuit structures are multiple and arranged in an array.

According to an aspect of the present disclosure, there is provided a driving method of a fingerprint identification circuit structure, applied to the fingerprint identification circuit structure of any one of the above, the driving method including, in one identification period:

in a transmitting stage, providing an alternating voltage signal to the transmitting electrode, and setting the voltage of the sampling node to be a fixed voltage through the detection circuit;

in a sampling phase, a fixed voltage is provided for the transmitting electrode, and the peak value of the voltage signal output by the receiving electrode is stored in the sampling node as a sensing voltage through the detection circuit;

in a reading stage, the fixed voltage provided for the transmitting electrode is kept unchanged, the sensing voltage is amplified through the signal output circuit, and the amplified sensing current is output to an output node according to the amplified sensing voltage.

In an exemplary embodiment of the disclosure, applied to the fingerprint recognition circuit structure of any one of the above, the driving method further includes, in one recognition period:

before the sampling stage begins, high voltage is provided for a switch control end of the second switch sub-circuit, and the first sampling node and the second sampling node are conducted;

and at the set moment after the sampling stage is completed, providing low voltage to the switch control end of the second switch sub-circuit to disconnect the first sampling node from the second sampling node.

According to the technical scheme, the invention has at least one of the following advantages and positive effects:

the fingerprint identification circuit structure of the invention transmits ultrasonic waves through the ultrasonic transmitting and receiving element and receives the ultrasonic waves reflected by fingerprints, and the peak value of a voltage signal output by the receiving electrode is stored in a sampling node as sensing voltage through the detection circuit; the sensing voltage is amplified by the signal output circuit, and an amplified sensing current flows into the output node according to the amplified sensing voltage. The sensing voltage is amplified through the signal output circuit, so that the on-resistance is reduced, the consumed power consumption is reduced, the output sensing current is amplified, an amplifying circuit is not required to be arranged in a subsequent circuit, the process flow is reduced, and the cost is reduced; and the power consumption is reduced without increasing the voltage of the power supply end.

Drawings

The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

FIG. 1 is a schematic diagram of an exemplary embodiment of a fingerprint identification circuit configuration of the present invention;

FIG. 2 is a schematic diagram of a fingerprint identification device formed by the fingerprint identification circuit structure of FIG. 1;

FIG. 3 is a schematic view of the structure of the insulating layer and the receiving electrode in FIG. 2;

FIG. 4 is a schematic diagram of another exemplary embodiment of a fingerprint identification circuit configuration of the present invention;

FIG. 5 is a schematic diagram of a further exemplary embodiment of the fingerprint identification circuit configuration of the present invention;

FIG. 6 is a schematic diagram of a further exemplary embodiment of a fingerprint identification circuit configuration of the present invention;

FIG. 7 is a schematic block diagram of a flow chart of an exemplary embodiment of a method for driving a fingerprint identification circuit configuration of the present invention;

FIG. 8 is a timing diagram of the driving process of the fingerprint recognition circuit structure of FIG. 1;

FIG. 9 is an equivalent circuit diagram of the fingerprint recognition circuit configuration of FIG. 1 during a transmit phase;

FIG. 10 is an equivalent circuit diagram of the fingerprint recognition circuit configuration of FIG. 1 in a hold phase;

fig. 11 is a timing diagram illustrating a driving process of the fingerprint recognition circuit structure of fig. 5.

The reference numerals of the main elements in the figures are explained as follows:

1. an ultrasonic transmitting and receiving element; tx, transmit electrode; p, a piezoelectric layer; rx, receiving electrode;

2. a detection circuit; m1, reset subcircuit (reset transistor); m4, a second switching sub-circuit (second switching transistor);

3. a signal output circuit; 31. a boost sub-circuit; c1, bootstrap capacitance; m5, a boost transistor; 32. a detection sub-circuit; m2, detection transistor; 33. a first switch sub-circuit; m3, a first switching transistor;

4. a protective layer; 5. an array substrate; 6. other functional layers; 7. an insulating layer;

n1, sampling node; n11, a first sampling node; n12, a second sampling node; n2, intermediate node; n3, output node;

v1, bias terminal; v2, reset control end; v3, a detection control end; v4, switch control end; vdd, a power supply terminal; vtx, emitter.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.

The human fingerprint includes convex fingerprint ridges F1 and concave fingerprint valleys F2, and when a finger is positioned over the fingerprint recognition device, the distance between the fingerprint ridges F1 and the surface of the fingerprint recognition device is smaller than the distance between the fingerprint valleys F2 and the surface of the fingerprint recognition device.

Therefore, the propagation path of the ultrasonic wave reaching the fingerprint ridge F1 and reflected back to the fingerprint identification device by the fingerprint ridge F1 is smaller than the propagation path of the ultrasonic wave reaching the fingerprint valley F2 and reflected back to the fingerprint identification device by the fingerprint valley F2. Therefore, the time of the echo reflected by the fingerprint ridge F1 reaching the fingerprint identification device is different from the time of the echo reflected by the fingerprint valley F2 reaching the fingerprint identification device, which also results in that the echo amount reflected by the fingerprint ridge F1 is different from the echo amount reflected by the fingerprint valley F2, and the fingerprint appearance of the finger covering the fingerprint identification device can be restored by analyzing the difference of the signal amount.

The present exemplary embodiment first provides a fingerprint identification circuit structure, referring to the schematic structural diagrams of an exemplary embodiment of the fingerprint identification circuit structures shown in fig. 1, 4 and 5; the fingerprint identification circuit structure can comprise an ultrasonic transmitting and receiving element 1, a detection circuit 2 and a signal output circuit 3; the ultrasonic transceiver 1 may include a transmitting electrode Tx, a piezoelectric layer P and a receiving electrode Rx stacked in sequence, the receiving electrode Rx is electrically connected to the sampling node N1, the ultrasonic transceiver 1 is configured to emit ultrasonic waves when receiving a predetermined electrical signal, and output a corresponding voltage signal according to the received ultrasonic waves; the detection circuit 2 is electrically connected to the sampling node N1, and the detection circuit 2 is configured to store the peak value of the voltage signal output from the receiving electrode Rx at the sampling node N1 as a sensing voltage; the signal output circuit 3 is electrically connected to the sampling node N1, and the signal output circuit 3 is configured to amplify the sensing voltage and flow an amplified sensing current to the output node N3 according to the amplified sensing voltage.

According to the fingerprint identification circuit structure, the signal output circuit 3 amplifies the sensing voltage to reduce the on-resistance, so that the consumed power consumption is reduced, the output sensing current is amplified, an amplifying circuit is not required to be arranged in a subsequent circuit, the process flow is reduced, and the cost is reduced; and power consumption is reduced without increasing the voltage of the power supply terminal Vdd.

In the present exemplary embodiment, referring to a schematic structural diagram of a fingerprint identification device formed by the fingerprint identification circuit structure in fig. 1 shown in fig. 2, the fingerprint identification device may include a protective layer 4, an ultrasonic transmission and reception element 1, an array substrate 5, and other functional layers 6.

The ultrasonic transmission and reception element 1 includes a transmission electrode Tx, a piezoelectric layer P, and a reception electrode Rx which are sequentially stacked. The transmitting electrode Tx is disposed on one side of the protecting layer 4, the protecting layer 4 provides protection for the transmitting electrode Tx, the material of the transmitting electrode Tx may be silver, and of course, the material of the transmitting electrode Tx may also be a conductive material such as gold or copper. The transmission electrodes Tx of the plurality of ultrasound transmitting and receiving elements 1 are provided integrally. The piezoelectric layer P is disposed on the side of the transmitting electrode Tx away from the protective layer 4, the material of the piezoelectric layer P is, for example, polyvinylidene fluoride (PVDF), aluminum nitride (AlN), lead zirconate titanate (PZT), zinc oxide (ZnO), and the piezoelectric layers P of the plurality of ultrasound transmitting and receiving elements 1 are integrally disposed. An insulating layer 7 is disposed on a side of the piezoelectric layer P away from the protective layer 4, as shown in fig. 3, M rows and N columns of through holes may be disposed on the insulating layer 7, the receiving electrodes Rx are disposed in the through holes and contact with the piezoelectric layer P, so that the receiving electrodes Rx of the ultrasonic transceiver elements 1 are spaced, a plurality of receiving electrodes Rx are arranged in an array, and adjacent receiving electrodes Rx are insulated and isolated by the insulating layer 7. Each receive electrode Rx forms a pixel for fingerprint recognition. The material of the receiving electrode Rx may be Indium Tin Oxide (ITO), and the material of the emitting electrode Tx may also be a conductive material such as gold, copper, Indium Zinc Oxide (IZO).

The detection circuit 2 and the signal output circuit 3 are disposed on the array substrate 5. The array substrate 5 is disposed on a side of the receiving electrode Rx away from the protection layer 4, so that the receiving electrode Rx is electrically connected to the sampling node N1.

With continued reference to fig. 1, the receiving electrode Rx of the ultrasound transmitting and receiving device 1 is electrically connected to the sampling node N1, and the transmitting electrode Tx is electrically connected to the transmitting end Vtx. The detection circuit 2 may include a reset sub-circuit M1, the reset sub-circuit M1 being electrically connected to the bias terminal V1, the reset control terminal V2 and the sampling node N1, and configured to supply the bias voltage supplied from the bias terminal V1 to the sampling node N1 in response to control of the reset control terminal V2. Specifically, the reset sub-circuit M1 is a reset transistor M1, a control electrode of the reset transistor M1 is electrically connected to a reset control terminal V2, a first electrode of the reset transistor M1 is electrically connected to the bias terminal V1, and a second electrode of the reset transistor M1 is electrically connected to the sampling node N1.

The signal output circuit 3 may include a boosting sub-circuit 31, a detecting sub-circuit 32, and a first switching sub-circuit 33; the boosting sub-circuit 31 is electrically connected with the sampling node N1 and the detection control terminal V3, and is configured to boost the sensing voltage of the sampling node N1 according to the signal of the detection control terminal V3; the detection sub-circuit 32 is electrically connected to the sampling node N1, the power supply terminal Vdd, and the intermediate node N2, and is configured to output an amplified sensing current to the intermediate node N2 according to the boosted sensing voltage; the first switch sub-circuit 33 is electrically connected to the detection control terminal V3, the intermediate node N2 and the output node N3, and is configured to control on/off between the intermediate node N2 and the output node N3 in response to a signal of the detection control terminal V3.

Specifically, the boost sub-circuit 31 may include a bootstrap capacitor C1, a first pole (negative terminal) of the bootstrap capacitor C1 is electrically connected to the detection control terminal V3, and a second pole (positive terminal) of the bootstrap capacitor C1 is electrically connected to the sampling node N1. The sensing sub-circuit 32 may include a sensing transistor M2, a control electrode of the sensing transistor M2 electrically connected to the sampling node N1, a first electrode of the sensing transistor M2 electrically connected to the power supply terminal Vdd, and a second electrode of the sensing transistor M2 electrically connected to the intermediate node N2. The first switch sub-circuit 33 may include a first switch transistor M3, a control pole of the first switch transistor M3 electrically connected to the detection control terminal V3, a first pole of the first switch transistor M3 electrically connected to the intermediate node N2, and a second pole of the first switch transistor M3 electrically connected to the output node N3.

The bootstrap capacitor C1 utilizes the characteristic that the voltage at two ends of the capacitor cannot change suddenly, when a certain voltage is kept at two ends of the capacitor, the voltage at the negative end of the capacitor is increased, the voltage at the positive end is still kept at the original voltage difference of the negative end, and the voltage equal to the voltage at the positive end is held by the negative end. In fact a positive feedback capacitor, is used to boost the supply voltage. Therefore, the sensing voltage of the sampling node N1 can be raised by the bootstrap capacitor C1, that is, the sensing voltage can be amplified by the bootstrap capacitor C1.

Referring to the schematic structure diagram of another exemplary embodiment of the circuit structure for fingerprint identification of the present invention shown in fig. 4, the exemplary embodiment is different from the exemplary embodiment in fig. 1 mainly in that: the boost sub-circuit 31 includes a boost transistor M5, the first pole and the second pole (source and drain) of the boost transistor M5 are both electrically connected to the detection control terminal V3, that is, the first pole and the second pole (source and drain) of the boost transistor M5 are connected to form a MOS capacitor, which can play the same role as the bootstrap capacitor C1, that is, the sensing voltage of the sampling node N1 can be raised, that is, the sensing voltage can be amplified; the control electrode of the boosting transistor M5 is electrically connected to the sampling node N1.

Referring to fig. 5, a schematic diagram of a further exemplary embodiment of the fingerprint identification circuit configuration of the present invention is shown; the main difference between this exemplary embodiment and the exemplary embodiment in fig. 1 is that: the detection circuit 2 of the fingerprint identification circuit structure may further include a second switch sub-circuit M4, the second switch sub-circuit M4 being electrically connected to the first sampling node N11, the second sampling node N12 and the switch control terminal V4, and configured to control on/off between the first sampling node N11 and the second sampling node N12 in response to a signal of the switch control terminal V4.

Specifically, the second switch sub-circuit M4 includes a second switch transistor M4, a control electrode of the second switch transistor M4 is electrically connected to the switch control terminal V4, a first electrode of the second switch transistor M4 is electrically connected to the first sampling node N11, and a second electrode of the second switch transistor M4 is electrically connected to the second sampling node N12. In this case, the second pole of the reset sub-circuit M1 is electrically connected to the first sampling node N11, and the first sampling node N11 is closer to the ultrasound transceiver element than the second sampling node N12. The bootstrap capacitor C1 can be prevented from leaking charges through the reset transistor M1 by the second switching transistor M4, and signal attenuation is reduced.

Of course, referring to fig. 6, a second switch sub-circuit M4 may also be added to the exemplary embodiment shown in fig. 4, that is, in the exemplary embodiment shown in fig. 6, the boost sub-circuit 31 includes a boost transistor M5, and the detection circuit 2 may further include a second switch sub-circuit M4; the position and connection relationship of the second switch sub-circuit M4 are the same as those in fig. 5, and therefore, the description thereof is omitted.

Furthermore, the invention also discloses a fingerprint identification device which can comprise any one of the fingerprint identification circuit structures. The specific structure of the fingerprint identification circuit structure has been described in detail above, and therefore, the detailed description thereof is omitted here.

The fingerprint identification device comprises a plurality of fingerprint identification circuit structures which can be arranged in an array form.

Specific examples of the fingerprint recognition device include any products or components having a fingerprint recognition function, such as a display panel having a fingerprint recognition function, an electronic product (e.g., a mobile phone or a tablet computer) having a fingerprint recognition function, and a fingerprint lock having a fingerprint recognition function.

It should be noted that, besides the fingerprint identification circuit structure, the fingerprint identification device further includes other necessary components and components, such as a display panel, a housing, a circuit board, a power line, and the like, taking a mobile phone as an example, and those skilled in the art can supplement the fingerprint identification device accordingly according to specific use requirements of the fingerprint identification device, and details are not repeated herein.

Further, the invention also discloses a driving method of the fingerprint identification circuit structure, which is applied to any one of the fingerprint identification circuit structures, and the driving method of the fingerprint identification circuit structure shown in fig. 7 is a flow schematic block diagram. The driving method may include the following steps in one recognition period:

in step S10, in the transmitting phase, an ac voltage signal is provided to the transmitting electrode Tx, and the voltage of the sampling node N1 is set to a fixed voltage by the detection circuit 2.

In step S20, in the sampling phase, a fixed voltage is provided to the transmitting electrode Tx, and the peak value of the voltage signal output from the receiving electrode Rx is stored at the sampling node N1 as the sensing voltage by the detection circuit 2.

In step S30, in the reading phase, the fixed voltage supplied to the transmitting electrode Tx is kept unchanged, the sensing voltage is amplified by the signal output circuit 3, and an amplified sensing current is output to the output node N3 according to the amplified sensing voltage.

A detailed driving process in one embodiment is described below with reference to fig. 1 and 8. The transistors in fig. 1 are all N-type transistors, and the effective voltage of the corresponding control electrode is a high level voltage.

In the transmitting stage, i.e. the stage t0 to t1, an alternating voltage signal is provided to the transmitting end Vtx of the transmitting electrode Tx, the alternating voltage signal may be a high-frequency high-voltage signal, the alternating voltage signal may be a sine wave or a square wave of 5 to 30MHz, and the number of pulses is controllable, and is 1 to 10. An effective voltage is supplied to the reset control terminal V2 to turn on the reset transistor M1, and a fixed bias voltage close to ground potential or ground potential is supplied to the bias terminal V1 to form an equivalent circuit diagram as shown in fig. 9. Therefore, the voltage of the receiving electrode Rx is fixed to the ground potential or the bias voltage of the ground potential, and the voltage difference between the transmitting electrode Tx and the receiving electrode Rx changes in an alternating current manner, so that the moving piezoelectric layer P is driven to vibrate and sound. Due to the fact that the transmission is over, there is still a certain oscillation in the circuit, and the ultrasonic interference signal is reflected back from the piezoelectric layer P earlier, the effective voltage of the reset control terminal V2 is kept for a certain time to eliminate the interference.

In a receiving stage, namely t 1-t 2, a fixed voltage is provided for a transmitting end Vtx of a transmitting electrode Tx, ultrasonic waves are reflected by fingerprints, and the ultrasonic waves reflected back on the receiving electrode Rx generate an alternating voltage signal Vecho; providing a high level Vbase to the bias voltage terminal V1, wherein the process of raising the gate potential of the detection transistor M2 is the process of receiving an echo (ultrasonic wave reflected by a fingerprint), and the gate direct current potential Vin of the detection transistor M2 is Vbase + Vecho; at time t2, the voltage at the reset control terminal V2 is lowered to near ground or ground, the reset transistor M1 is turned off, the sampling is ended, and the voltage at the bias terminal V1 is lowered to ground after the reset transistor M1 is completely turned off for about 10 μ s. Only half wavelength is taken and kept when the echo signal is collected, the sampling time is short, and the power consumption is low. The voltage at sampling node N1 will remain at the peak voltage during the fingerprint film signal fluctuations.

In the period from t2 to t3, the circuit does not sample the received signal for the signal blocking period, the waiting reading period or the holding period. In the equivalent circuit diagram at this time, Cp is a node parasitic capacitance as shown in fig. 10. The main effect of this phase is to stabilize the voltage at the sampling node N1.

In the reading phase, i.e., the phases t3 to t4, the fixed voltage provided to the transmitting terminal Vtx of the transmitting electrode Tx remains unchanged, and after the voltage of the sampling node N1 reaches a stable value, the effective voltage is provided to the detection control terminal V3, due to the existence of the bootstrap capacitor C1, the gate voltage of the detection transistor M2 will be pulled high, and reaches the turn-on voltage of the detection transistor M2, and at the same time, the switch transistor M3 will be turned on, and the detection transistor M2 outputs the amplified sensing current to the output node N3. The magnitude of the sensing current is related to the voltage of the gate of the detection transistor M2, and the voltage of the gate of the detection transistor M2 is related to the ultrasonic voltage, specifically:

the drain current I when the sense transistor M2 is saturated is:

I＝(1/2)UnCox(W/L)*(Vgs-Vth)²，

in the formula: un is the electron transfer rate; cox is unit area gate oxide capacitance; the width-length ratio of the W/L oxide layer; vth is a threshold voltage; the above are all fixed values. Vgs-Vth is the overdrive voltage; vbase + Vecho + V3, the drain current is therefore dependent only on the voltage Vgs at the gate of the detection transistor M2, the voltage Vgs at the gate of the detection transistor M2 is increased by the bootstrap capacitor C1 or the boost transistor, and the drain current I is therefore increased, so that the current flowing out of the detection transistor M2 is amplified.

The specific driving method of another exemplary embodiment of the fingerprint identification circuit structure shown in fig. 4 is the same as that described above, and therefore, the detailed description thereof is omitted here.

A detailed driving process in another embodiment will be described with reference to fig. 5 and 11. The transistors in fig. 5 are all N-type transistors, and the effective voltage of the corresponding control electrode is a high level voltage.

In a transmitting stage, namely a stage t 0-t 1, providing an alternating voltage signal to a transmitting end Vtx of a transmitting electrode Tx, wherein the alternating voltage signal can be a high-frequency high-voltage signal, the alternating voltage signal can be a sine wave or a square wave of 5-30 MHz, and the number of pulses is controllable and is 1-10; the reset control terminal V2 is supplied with an effective voltage to turn on the reset transistor M1, and the bias terminal V1 is supplied with a fixed bias voltage close to ground or earth potential. Therefore, the voltage of the receiving electrode Rx is fixed to the ground potential or the bias voltage of the ground potential, and the voltage difference between the transmitting electrode Tx and the receiving electrode Rx changes in an alternating current manner, so that the moving piezoelectric layer P is driven to vibrate and sound. Due to the fact that the transmission is finished, certain oscillation exists in the circuit, and the ultrasonic interference signal is reflected back from the piezoelectric layer P earlier, the effective voltage of the reset control terminal V2 is kept for a certain time to eliminate interference.

Before time t1, i.e., before the sampling phase begins, a high voltage is applied to the gate of the second switching transistor M4 (i.e., the switch control terminal V4), so that the second switching transistor M4 is turned on, and the first sampling node N11 and the second sampling node N12 are connected, so that the voltage of the first sampling node N11 is the same as the voltage of the second sampling node N12.

In a receiving stage, namely t 1-t 2, a fixed voltage is provided for a transmitting end Vtx of a transmitting electrode Tx, ultrasonic waves are reflected by fingerprints, and the ultrasonic waves reflected back on the receiving electrode Rx generate an alternating voltage signal Vecho; providing a high level Vbase to the bias voltage terminal V1, wherein the process of raising the gate potential of the detection transistor M2 is the process of receiving the echo signal, and the gate dc potential Vin of the detection transistor M2 is Vbase + Vecho; at time t2, the voltage at the reset control terminal V2 is lowered to near ground or ground, the reset transistor M1 is turned off, the sampling is ended, and after the reset transistor M1 is completely turned off for about 10 μ s, the voltages at the bias terminal V1 and the gates of the second switching transistor M4 (i.e., the switch control terminal V4) are lowered to ground, and the second switching transistor M4 is turned off. When the echo signal is collected, only half wavelength is taken and kept, the sampling time is short, and the power consumption is low. The voltage at sampling node N1 will remain at the peak voltage during the fingerprint film signal fluctuations.

In the period from t2 to t3, the circuit does not sample the received signal for the signal blocking period, the waiting reading period or the holding period. In the equivalent circuit diagram of this case, Cp is a node parasitic capacitance as shown in fig. 9. The main effect of this phase is to stabilize the voltage at the sampling node N1.

At the stage t 2-t 4, the second switch transistor M4 is in a turned-off state, so that the bootstrap capacitor C1 is prevented from leaking charges through the reset transistor M1, and signal attenuation is reduced.

The specific process of the reading stage is the same as that of fig. 7, and therefore, the description thereof is omitted.

The specific driving method of another exemplary embodiment of the fingerprint identification circuit structure shown in fig. 6 is the same as that described above, and therefore, the detailed description thereof is omitted here.

The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments, and the features discussed in connection with the embodiments are interchangeable, if possible. In the above description, numerous specific details are provided to give a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.

The terms "about" and "approximately" as used herein generally mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range. The amounts given herein are approximate, meaning that the meaning of "about", "approximately" or "approximately" may still be implied without specific recitation.

Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". Other relative terms, such as "high", "low", "top", "bottom", and the like, are also intended to have similar meanings. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.

In this specification, the terms "a", "an", "the" and "the" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and are not limiting on the number of their objects.

It is to be understood that the invention is not limited in its application to the details of construction and the arrangement of components set forth in the description. The invention is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications fall within the scope of the present invention. It will be understood that the invention disclosed and defined in this specification extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute alternative aspects of the present invention. The embodiments described in this specification illustrate the best mode known for carrying out the invention and will enable those skilled in the art to utilize the invention.

Claims (10)

1. A fingerprint identification circuit structure, comprising:

the ultrasonic transmitting and receiving element comprises a transmitting electrode, a piezoelectric layer and a receiving electrode which are sequentially stacked, wherein the receiving electrode is electrically connected with the sampling node, and the ultrasonic transmitting and receiving element is configured to send out ultrasonic waves when receiving a preset electric signal and output corresponding voltage signals according to the received ultrasonic waves;

a detection circuit electrically connected to a sampling node, the detection circuit configured to store a peak value of the voltage signal output by the receiving electrode at the sampling node as a sensing voltage;

and the signal output circuit is electrically connected with the sampling node, is configured to amplify the sensing voltage and flow amplified sensing current into the output node according to the amplified sensing voltage.

2. The fingerprint recognition circuit structure of claim 1, wherein the signal output circuit comprises:

the boosting sub-circuit is electrically connected with the sampling node and the detection control terminal and is configured to boost the sensing voltage of the sampling node according to a signal of the detection control terminal;

the detection sub-circuit is electrically connected with the sampling node, the power supply end and the intermediate node and is configured to output the amplified sensing current to the intermediate node according to the boosted sensing voltage;

and the first switch sub-circuit is electrically connected with the detection control end, the intermediate node and the output node and is configured to respond to a signal of the detection control end to control the connection and disconnection between the intermediate node and the output node.

3. The circuit structure of claim 2, wherein the boost sub-circuit comprises a bootstrap capacitor, a first pole of the bootstrap capacitor is electrically connected to the detection control terminal, and a second pole of the bootstrap capacitor is electrically connected to the sampling node.

4. The fingerprint identification circuit structure of claim 2, wherein the boost sub-circuit comprises a boost transistor, wherein a first pole and a second pole of the boost transistor are both electrically connected to the detection control terminal, and wherein a control pole of the boost transistor is electrically connected to the sampling node.

5. The fingerprint recognition circuit arrangement of claim 3 or 4, wherein the detection sub-circuit comprises a detection transistor having a control electrode electrically connected to the sampling node, a first electrode electrically connected to the power supply terminal, and a second electrode electrically connected to the intermediate node;

the first switch sub-circuit comprises a first switch transistor, a control electrode of the first switch transistor is electrically connected with the detection control end, a first electrode of the first switch transistor is electrically connected with the intermediate node, and a second electrode of the first switch transistor is electrically connected with the output node.

6. The fingerprint identification circuit structure of claim 1, wherein the detection circuit comprises a reset sub-circuit electrically connected to a bias terminal, a reset control terminal and the sampling node, and configured to provide a bias voltage provided by the bias terminal to the sampling node in response to control of the reset control terminal.

7. The fingerprint identification circuit structure of claim 6, wherein the detection circuit further comprises a second switch sub-circuit electrically connected to the first sampling node, the second sampling node and the switch control terminal, and configured to control the connection and disconnection between the first sampling node and the second sampling node in response to a signal of the switch control terminal; the first sampling node is closer to the ultrasonic transmitting and receiving element relative to the second sampling node, and the reset sub-circuit is electrically connected with the first sampling node.

8. A fingerprint identification device, comprising the fingerprint identification circuit structure of any one of claims 1 to 7, wherein the fingerprint identification circuit structure is a plurality of fingerprint identification circuit structures arranged in an array.

9. A driving method of a fingerprint identification circuit structure, which is applied to the fingerprint identification circuit structure of any one of claims 1 to 7, the driving method comprising in one identification period:

in a transmitting stage, providing an alternating voltage signal to the transmitting electrode, and setting the voltage of the sampling node to be a fixed voltage through the detection circuit;

in a sampling phase, a fixed voltage is provided for the transmitting electrode, and the peak value of the voltage signal output by the receiving electrode is stored in the sampling node as a sensing voltage through the detection circuit;

in a reading stage, the fixed voltage provided for the transmitting electrode is kept unchanged, the sensing voltage is amplified through the signal output circuit, and the amplified sensing current is output to an output node according to the amplified sensing voltage.

10. The driving method of a fingerprint recognition circuit structure according to claim 9, applied to the fingerprint recognition circuit structure of claim 7, further comprising, in one recognition cycle:

before the sampling stage begins, high voltage is provided for a switch control end of the second switch sub-circuit, and the first sampling node and the second sampling node are conducted;

and at the set moment after the sampling stage is completed, providing low voltage to the switch control end of the second switch sub-circuit to disconnect the first sampling node from the second sampling node.

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