CN111968575B

CN111968575B - Pixel driving circuit, driving method thereof and display device

Info

Publication number: CN111968575B
Application number: CN202010931075.7A
Authority: CN
Inventors: 刘珂; 石领; 王彦强; 吕祖彬; 罗鸿强; 丁小琪; 贵炳强
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2020-09-07
Filing date: 2020-09-07
Publication date: 2022-10-11
Anticipated expiration: 2040-09-07
Also published as: CN111968575A

Abstract

A pixel driving circuit, a driving method thereof and a display device are provided, the pixel driving circuit includes: the pixel driving sub-circuit is arranged to provide a driving signal to the light-emitting unit through a third node under the control of a second scanning signal end; the ultrasonic sensing sub-circuit is arranged to emit ultrasonic waves according to signals of the first node and the third power supply end and receive reflected ultrasonic echoes to generate a first sensing signal at the first node; the ultrasonic driving sub-circuit is arranged to provide a signal of a second scanning signal end to the first node under the control of the first scanning signal end and rectify the first induction signal; the signal acquisition sub-circuit is arranged to output a second sensing signal according to the first power supply end and the first sensing signal under the control of the first node. The pixel driving circuit provided by the embodiment integrates the ultrasonic fingerprint identification function, and the thickness of the display panel is reduced.

Description

Pixel driving circuit, driving method thereof and display device

Technical Field

The present disclosure relates to display technologies, and more particularly, to a pixel driving circuit, a driving method thereof, and a display device.

Background

Fingerprint identification is a biological identification mode, and is widely applied to the fields of smart phones, safety equipment and the like. Currently, common fingerprint identification schemes include optical, capacitive, and ultrasonic. The ultrasonic fingerprint identification mode is concerned with due to the characteristics of good penetrability, high accuracy, underwater unlocking, living body identification and the like.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The embodiment of the application provides a pixel driving circuit, a driving method thereof and a display device.

In one aspect, an embodiment of the present application provides a pixel driving circuit, including: pixel drive sub-circuit, ultrasonic wave sensing sub-circuit and signal acquisition sub-circuit, wherein:

the pixel driving sub-circuit is respectively connected with a first power supply end, a second scanning signal end, a data signal end, a third node and a second power supply end, and is arranged to provide a driving signal for the light-emitting unit through the third node according to signals of the first power supply end and the data signal end under the control of the second scanning signal end;

a first pole of the ultrasonic sensing sub-circuit is connected with the first node, a second pole of the ultrasonic sensing sub-circuit is connected with a third power supply end, and the ultrasonic sensing sub-circuit is configured to emit ultrasonic waves according to signals of the first node and the third power supply end and receive reflected ultrasonic echoes to generate a first sensing signal at the first node;

the ultrasonic driving sub-circuit is respectively connected with a first scanning signal end, the second scanning signal end and a first node, and is arranged to provide a signal of the second scanning signal end to the first node under the control of the first scanning signal end and rectify the first induction signal;

the signal acquisition sub-circuit is respectively connected with the first power end, the first node and the output end, and is set to output a second sensing signal to the output end according to the first power end and the first sensing signal under the control of the first sensing signal of the first node.

In an exemplary embodiment, the pixel driving sub-circuit includes: a compensation sub-circuit, a drive sub-circuit, a data write sub-circuit, a first storage sub-circuit, and a second storage sub-circuit, wherein:

the compensation sub-circuit is respectively connected with the first power supply end, the second scanning signal end and the fourth node, and is set to provide a signal of the first power supply end for the fourth node under the control of the second scanning signal end;

the driving sub-circuit is respectively connected with the fourth node, the second node and the third node, and is set to output driving current to the light-emitting unit through the third node under the control of the second node;

the data writing sub-circuit is respectively connected with the data signal terminal, the second scanning signal terminal and the second node, and is configured to write the voltage of the data signal terminal into the second node under the control of the second scanning signal terminal;

the first storage sub-circuit is respectively connected with the second node and the third node and is set to store a voltage value between the second node and the third node;

the second storage sub-circuit is connected to the third node and the second power supply terminal, respectively, and is configured to store a voltage value between the third node and the second power supply terminal.

In an exemplary embodiment, the compensation sub-circuit includes: and a control electrode of the first transistor is connected with the second scanning signal end, a first electrode of the first transistor is connected with the first power supply end, and a second electrode of the first transistor is connected with the fourth node.

In an exemplary embodiment, the driving sub-circuit includes: and a third transistor having a control electrode connected to the second node, a first electrode connected to the fourth node, and a second electrode connected to the third node.

In an exemplary embodiment, the data writing sub-circuit includes: and a control electrode of the second transistor is connected with the second scanning signal end, a first electrode of the second transistor is connected with the data signal end, and a second electrode of the second transistor is connected with the second node.

In an exemplary embodiment, the first storage sub-circuit includes: and a first pole of the first capacitor is connected with the second node, and a second pole of the first capacitor is connected with the third node.

In an exemplary embodiment, the second storage sub-circuit includes: and a first pole of the second capacitor is connected with the third node, and a second pole of the second capacitor is connected with the second power supply end.

In an exemplary embodiment, the pixel driving sub-circuit further includes a reset sub-circuit, the reset sub-circuit is respectively connected to the first scan signal terminal, the reference signal terminal and the second node, and the reset sub-circuit is configured to provide the signal of the reference signal terminal to the second node under the control of the first scan signal terminal.

In an exemplary embodiment, the reset sub-circuit includes: and a control electrode of the fourth transistor is connected with the first scanning signal end, a first electrode of the fourth transistor is connected with the reference signal end, and a second electrode of the fourth transistor is connected with the second node.

In an exemplary embodiment, the ultrasonic drive sub-circuit includes: and a control electrode of the fifth transistor is connected with the first scanning signal end, a first electrode of the fifth transistor is connected with the first node, and a second electrode of the fifth transistor is connected with the second scanning signal end.

In an exemplary embodiment, the signal collecting sub-circuit includes a sixth transistor and a seventh transistor, a control electrode of the sixth transistor is connected to the first node, a first electrode of the sixth transistor is connected to the first power source terminal, a second electrode of the sixth transistor is connected to the first electrode of the seventh transistor, a control electrode of the seventh transistor is connected to the second scan signal terminal, and a second electrode of the seventh transistor is connected to the output terminal.

In an exemplary embodiment, the pixel driving sub-circuit further includes a reset sub-circuit, wherein:

the compensation sub-circuit comprises: a control electrode of the first transistor is connected with the second scanning signal end, a first electrode of the first transistor is connected with the first power supply end, and a second electrode of the first transistor is connected with the fourth node;

the driving sub-circuit includes: a third transistor having a control electrode connected to the second node, a first electrode connected to the fourth node, and a second electrode connected to the third node;

the data write sub-circuit includes: a control electrode of the second transistor is connected with the second scanning signal end, a first electrode of the second transistor is connected with the data signal end, and a second electrode of the second transistor is connected with the second node;

the reset sub-circuit comprises a fourth transistor, a control electrode of the fourth transistor is connected with the first scanning signal end, a first electrode of the fourth transistor is connected with the reference signal end, and a second electrode of the fourth transistor is connected with the second node;

the first storage sub-circuit comprises: a first capacitor, a first pole of the first capacitor being connected to the second node, a second pole of the first capacitor being connected to the third node;

the second storage sub-circuit includes: a first electrode of the second capacitor is connected with the third node, and a second electrode of the second capacitor is connected with the second power supply end;

the ultrasonic drive sub-circuit includes: a control electrode of the fifth transistor is connected with the first scanning signal end, a first electrode of the fifth transistor is connected with the first node, and a second electrode of the fifth transistor is connected with the second scanning signal end;

the signal acquisition sub-circuit comprises: a control electrode of the sixth transistor is connected to the first node, a first electrode of the sixth transistor is connected to the first power source terminal, a second electrode of the sixth transistor is connected to the first electrode of the seventh transistor, a control electrode of the seventh transistor is connected to the second scan signal terminal, and a second electrode of the seventh transistor is connected to the output terminal.

In an exemplary embodiment, the first transistor is a P-type transistor, and the second to seventh transistors are N-type transistors.

In another aspect, an embodiment of the present application provides a display device including the pixel driving circuit.

In another aspect, an embodiment of the present application provides a pixel driving method, which is applied to the pixel driving circuit, where the pixel driving method includes:

in a second stage, under the control of the second scan signal terminal, turning on the power supply terminal of the first terminal and the third node, compensating the voltage of the third node, and under the control of the first scan signal terminal, providing the signal of the second scan signal terminal to the first node, under the control of the first node and the third power supply terminal, the ultrasonic sensing sub-circuit emitting ultrasonic waves;

in a third stage, receiving the reflected ultrasonic echo, generating a first induction signal at the first node, and rectifying the first induction signal by the ultrasonic drive sub-circuit under the control of the first scanning signal end and the second scanning signal end;

in a fourth phase, under the control of the second scanning signal terminal, writing the signal of the data signal terminal into the pixel driving sub-circuit to change the voltage of the third node, and under the control of the first sensing signal of the first node, outputting a second sensing signal to the output terminal;

in a fifth stage, the first power terminal and the third node are turned on under the control of the second scan signal terminal, and a driving signal is supplied to the light emitting unit through the third node.

In an exemplary embodiment, the pixel driving sub-circuit includes: the data writing circuit comprises a compensation sub-circuit, a driving sub-circuit, a data writing sub-circuit, a first storage sub-circuit, a second storage sub-circuit and a resetting sub-circuit;

the driving sub-circuit is respectively connected with the fourth node, the second node and the third node and is set to output driving current to the light-emitting unit through the third node under the control of the second node;

the second storage sub-circuit is respectively connected with the third node and the second power supply end and is set to store a voltage value between the third node and the second power supply end;

in the second stage, the turning on the power source terminal of the first terminal and the third node under the control of the second scan signal terminal, and the compensating the voltage of the third node includes:

under the control of the second scanning signal terminal, providing a signal of a first power supply terminal to the fourth node;

the writing the signal of the data signal terminal into the pixel driving sub-circuit to change the voltage of the third node under the control of the second scan signal terminal in the fourth stage includes:

and writing the signal of the data signal end into the second node under the control of the second scanning signal end, and jumping the voltage value of the third node under the action of the first energy storage sub-circuit and the second energy storage sub-circuit.

In an exemplary embodiment, the pixel driving sub-circuit further includes a reset sub-circuit, the reset sub-circuit is respectively connected to the first scan signal terminal, the reference signal terminal and the second node, and the reset sub-circuit is configured to provide a signal of the reference signal terminal to the second node under the control of the first scan signal terminal;

the driving method further includes, in a first stage, supplying a signal of the reference signal terminal to the second node under control of the first scan signal terminal.

An embodiment of the present application includes a pixel driving circuit, including: the pixel driving sub-circuit provides a driving signal to the light-emitting unit through the third node according to signals of the first power supply end and the data signal end under the control of the second scanning signal end; the ultrasonic sensing sub-circuit emits ultrasonic waves according to signals of the first node and the third power supply end, receives reflected ultrasonic echoes and generates a first sensing signal at the first node; the ultrasonic driving sub-circuit provides a signal of the second scanning signal end to the first node under the control of the first scanning signal end, and rectifies the first induction signal; the signal acquisition sub-circuit outputs a second sensing signal to the output terminal according to the first power end and the first sensing signal under the control of the first sensing signal of the first node. The pixel driving circuit provided by the embodiment integrates the ultrasonic fingerprint identification function into the pixel driving circuit, reduces the circuit complexity of the display area and the GOA area of the display panel under the condition of not increasing the pixel size, reduces the whole thickness of the display panel, reduces the power consumption of the display panel, and is favorable for realizing high PPI and narrow frame of the display panel.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and drawings.

Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.

FIG. 1 is a schematic structural diagram of a display module with an ultrasonic fingerprint sensor;

FIG. 2 is a schematic structural diagram of an OLED display module;

FIG. 3 is a schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a pixel driving sub-circuit provided in an exemplary embodiment;

FIG. 5 is a schematic diagram of a pixel driving sub-circuit provided in an exemplary embodiment;

FIG. 6 is a schematic diagram of a compensation sub-circuit provided in an exemplary embodiment;

FIG. 7 is a schematic diagram of a driving sub-circuit provided in an exemplary embodiment;

FIG. 8 is a schematic diagram of a data write sub-circuit provided in an exemplary embodiment;

FIG. 9 is a schematic diagram of a first memory sub-circuit provided in an exemplary embodiment;

FIG. 10 is a schematic diagram of a second memory sub-circuit provided in an exemplary embodiment;

FIG. 11 is a schematic diagram of a reset sub-circuit provided in an exemplary embodiment;

FIG. 12 is a schematic diagram of an ultrasonic drive sub-circuit provided in an exemplary embodiment;

FIG. 13 is a schematic diagram of an ultrasonic sensing sub-circuit provided in an exemplary embodiment;

FIG. 14 is a schematic diagram of a signal acquisition sub-circuit provided in an exemplary embodiment;

FIG. 15 is a schematic diagram of a signal acquisition sub-circuit provided in another exemplary embodiment;

FIG. 16 is a schematic diagram of a pixel driving circuit according to an exemplary embodiment;

FIG. 17 is a timing diagram of a pixel driving circuit according to an exemplary embodiment;

FIG. 18 is a schematic diagram of a pixel driving circuit at a first stage in accordance with an exemplary embodiment;

FIG. 19 is a schematic diagram of a pixel driving circuit at a first stage in accordance with an exemplary embodiment;

FIG. 20 is a schematic diagram of a pixel driving circuit at a first stage according to an exemplary embodiment;

FIG. 21 is a schematic diagram of a pixel driving circuit at a first stage in accordance with an exemplary embodiment;

FIG. 22 is a schematic diagram of a pixel driving circuit at a first stage in accordance with an exemplary embodiment;

fig. 23 is a flowchart of a pixel driving method according to an exemplary embodiment.

Detailed Description

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the present application, the embodiments and features of the embodiments may be arbitrarily combined with each other without conflict.

The steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.

Unless defined otherwise, technical or scientific terms used herein should have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

In the drawings, the size of each component, the thickness of a layer, or a region may be exaggerated for clarity. Therefore, the embodiments of the present disclosure are not necessarily limited to the dimensions, and the shapes and sizes of the respective components in the drawings do not reflect a true scale. Further, the drawings schematically show desirable examples, and the embodiments of the present disclosure are not limited to the shapes or numerical values shown in the drawings.

The ordinal numbers such as "first", "second", "third", etc., in this disclosure are provided to avoid confusion among the constituent elements, and do not indicate any order, number, or importance.

In the present disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.

In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors of opposite polarities, or in the case where the direction of current flow during circuit operation changes, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in the present disclosure, "source electrode" and "drain electrode" may be interchanged with each other. The transistor may be a P-type transistor, or an N-type transistor, and when the transistor is a P-type transistor, the transistor is turned on (i.e., turned on) when the control voltage of the transistor is a low signal, and is turned off (i.e., turned off) when the control voltage of the transistor is a high signal, and when the transistor is an N-type transistor, the transistor is turned on when the control voltage of the transistor is a high signal, and is turned off when the control voltage of the transistor is a low signal.

In the present disclosure, the connection includes an electrical connection, "electrical connection" includes a case where constituent elements are connected together through an element having some kind of electrical action. The "element having a certain electric function" is not particularly limited as long as it can transmit and receive an electric signal between connected components. Examples of the "element having some kind of electric function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

Fig. 1 is a schematic structural view of a display module with an ultrasonic fingerprint sensor. As shown in fig. 1, the display module includes a substrate 21 and an ultrasonic fingerprint sensor 20 disposed on the substrate 21. The ultrasonic fingerprint sensor 20 includes a first electrode layer 22 disposed on an upper side of a substrate 21, a piezoelectric material layer 23 disposed on a side of the first electrode layer 22 away from the substrate 21, and a second electrode layer 24 disposed on a side of the piezoelectric material layer 23 away from the substrate 21. The display module further comprises a flexible circuit board 11 which is located on one side of the substrate 21 far away from the ultrasonic fingerprint sensor 20 after being bent, and a signal processing chip 12 which is arranged on one side of the flexible circuit board 11 far away from the substrate 21. In the display module shown in fig. 1, the ultrasonic fingerprint sensor 20 is attached to the lower side of the display panel 10 in the form of a hanging module. The display module has an independent display circuit and logic circuit structure. Therefore, the display module assembly shown in fig. 1 not only increases the whole thickness of the display module assembly, but also increases the power consumption of the display module assembly.

Fig. 2 is a schematic structural diagram of an OLED display module. As shown in fig. 2, the Organic Light-Emitting Diode (OLED) display module includes a pixel driving module 30, an ultrasonic fingerprint sensor 20, and a flexible printed circuit 11. From being close to the pixel driving module 30 to being far away from the pixel driving module 30, the ultrasonic fingerprint sensor 20 comprises a first electrode layer 22, a piezoelectric material layer 23 and a second electrode layer 24 which are arranged in sequence. The flexible circuit board 11 is located on one side, away from the pixel driving module 30, of the second electrode layer 24 after being bent, and a signal processing chip 12 is arranged on one side, away from the pixel driving module 30, of the flexible circuit board 11. In the display module shown in fig. 2, the echo collection circuit and the pixel driving circuit of the ultrasonic fingerprint sensor are integrated in the display panel at the same time. The overall thickness of the display module shown in fig. 2 is much reduced compared to the overall thickness of the display module shown in fig. 1. However, the display area circuit and the gate driving circuit of the display module shown in fig. 2 are complicated, the thickness of the display module is still large, and it is difficult to implement high PPI (Pixels Per Inch) and narrow bezel.

Fig. 3 is a schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure. As shown in fig. 3, the pixel driving circuit provided in this embodiment may include: the pixel driving sub-circuit 40, the ultrasonic driving sub-circuit 60, the ultrasonic sensing sub-circuit 70, and the signal collecting sub-circuit 80 may further include a light emitting unit 50, wherein:

the pixel driving sub-circuit 40 is respectively connected to a first power source terminal VDD, a second SCAN signal terminal SCAN2, a Data signal terminal Data, a third node C, and a second power source terminal VSS, and is configured to provide a driving signal to the light emitting unit 50 through the third node C according to signals of the first power source terminal VDD and the Data signal terminal Data under the control of the second SCAN signal terminal SCAN2, so as to drive the light emitting unit 50 to emit light;

the first pole of the ultrasonic sensing sub-circuit 70 is connected to the first node a, the second pole is connected to the third power supply terminal Tx, and the ultrasonic sensing sub-circuit is configured to emit ultrasonic waves according to signals of the first node a and the third power supply terminal Tx and receive the reflected ultrasonic echo to generate a first sensing signal at the first node a;

the ultrasonic driving sub-circuit 60 is respectively connected to the first SCAN signal terminal SCAN1, the second SCAN signal terminal SCAN2 and the first node a, and is configured to provide a signal of the second SCAN signal terminal SCAN2 to the first node a under the control of the first SCAN signal terminal SCAN1, and rectify the first sensing signal;

the signal collecting sub-circuit 80 is respectively connected to the first power source end VDD, the first node a, and the output end OUT, and is configured to output a second sensing signal to the output end OUT according to the first power source end VDD and the first sensing signal under the control of the first sensing signal of the first node a.

And a light emitting unit 50 having a first electrode connected to the pixel driving sub-circuit 40 and a second electrode connected to the second power source terminal VSS, the light emitting unit 50 being configured to emit light under the control of the pixel driving sub-circuit 40 and the second power source terminal VSS. The first pole of the light emitting unit 50 may be an anode and the second pole may be a cathode. The light emitting unit 50 may be an organic electroluminescent device (OLED).

The pixel driving circuit provided by the embodiment integrates the ultrasonic fingerprint identification function into the pixel driving circuit, reduces the circuit complexity of the display area and the GOA area of the display panel under the condition of not increasing the pixel size, reduces the whole thickness of the display panel, reduces the power consumption of the display panel, and is favorable for realizing high PPI and narrow frame of the display panel.

Fig. 4 is a schematic diagram of a pixel driving circuit in an exemplary embodiment. As shown in fig. 4, in the present embodiment, the pixel driving sub-circuit may include: a compensation sub-circuit 41, a drive sub-circuit 42, a data write sub-circuit 43, a first storage sub-circuit 44, and a second storage sub-circuit 45, wherein:

the compensation sub-circuit 41 is respectively connected to the first power source terminal VDD, the second SCAN signal terminal SCAN2 and a fourth node D, and is configured to provide a signal of the first power source terminal VDD to the fourth node D under the control of the second SCAN signal terminal SCAN2;

the driving sub-circuit 42 is respectively connected to the fourth node D, the second node B, and the third node C, and is configured to output a driving current to the light emitting unit 50 through the third node C under the control of the second node B;

the Data writing sub-circuit 43 is respectively connected to the Data signal terminal Data, the second SCAN signal terminal SCAN2, and the second node B, and configured to write the voltage of the Data signal terminal Data to the second node B under the control of the second SCAN signal terminal SCAN2;

the first storage sub-circuit 44 is respectively connected to the second node B and the third node C, and is configured to store a voltage value between the second node B and the third node C;

the second storage sub-circuit 45 is respectively connected to the third node C and the second power source terminal VSS, and is configured to store a voltage value between the third node C and the second power source terminal VSS.

In an exemplary embodiment, the first power source terminal VDD may be continuously a high-level signal, and the second power source terminal VSS may be continuously a low-level signal.

Fig. 5 is a schematic diagram of a pixel driving sub-circuit according to an exemplary embodiment. As shown in fig. 5, the pixel driving sub-circuit may further include a reset sub-circuit 46, the reset sub-circuit 46 is respectively connected to the first SCAN signal terminal SCAN1, the reference signal terminal VREF, and the second node B, and the reset sub-circuit 46 is configured to provide the signal of the reference signal terminal VREF to the second node B under the control of the first SCAN signal terminal SCAN 1.

FIG. 6 is a schematic diagram of a compensation sub-circuit provided in an exemplary embodiment. As shown in fig. 6, in this embodiment, the compensation sub-circuit 41 may include: a control electrode of the first transistor T1 is connected to the second SCAN signal terminal SCAN2, a first electrode of the first transistor T1 is connected to the first power terminal VDD, and a second electrode of the first transistor T1 is connected to the fourth node D.

The structure of the compensation sub-circuit 41 in one exemplary embodiment is shown in fig. 6, but those skilled in the art will appreciate that the implementation of the compensation sub-circuit is not limited thereto as long as the function thereof can be achieved.

Fig. 7 is a schematic diagram of a driving sub-circuit provided in an exemplary embodiment. As shown in fig. 7, the driving sub-circuit 42 may include: and a third transistor T3, a control electrode of the third transistor T3 being connected to the second node B, a first electrode thereof being connected to the fourth node D, and a second electrode thereof being connected to the third node C.

The structure of the driving sub-circuit 42 in one exemplary embodiment is shown in fig. 7, but those skilled in the art will appreciate that the implementation of the driving sub-circuit is not limited thereto as long as the function thereof can be realized.

FIG. 8 is a schematic diagram of a data write sub-circuit provided in an exemplary embodiment. As shown in fig. 8, the data writing sub-circuit 43 may include: and a control electrode of the second transistor T2 is connected to the second SCAN signal terminal SCAN2, a first electrode is connected to the Data signal terminal Data, and a second electrode is connected to the second node B.

The structure of the data writing sub-circuit 43 in one exemplary embodiment is shown in fig. 8, but those skilled in the art will appreciate that the implementation of the data writing sub-circuit is not limited thereto as long as the function thereof can be realized.

FIG. 9 is a schematic diagram of a first memory sub-circuit provided in an exemplary embodiment. As shown in fig. 9, the first memory sub-circuit 44 may include: and a first capacitor C1, wherein a first pole of the first capacitor C1 is connected to the second node B, and a second pole is connected to the third node C.

The structure of the first memory sub-circuit 44 in one exemplary embodiment is shown in fig. 9, but those skilled in the art will appreciate that the implementation of the first memory sub-circuit is not limited thereto as long as the function thereof can be implemented.

FIG. 10 is a schematic diagram of a second memory sub-circuit provided in an exemplary embodiment. As shown in fig. 10, the second memory sub-circuit 45 may include: and a first pole of the second capacitor C2 is connected with the third node C, and a second pole of the second capacitor C2 is connected with the second power supply terminal VSS.

The structure of the second memory sub-circuit 45 in one exemplary embodiment is shown in fig. 10, but those skilled in the art will appreciate that the implementation of the second memory sub-circuit is not limited thereto as long as the function thereof can be implemented.

Fig. 11 is a schematic diagram of a reset sub-circuit provided in an exemplary embodiment. As shown in fig. 11, the reset sub-circuit 46 may include: and a fourth transistor T4, a control electrode of the fourth transistor T4 is connected to the first SCAN signal terminal SCAN1, a first electrode is connected to the reference signal terminal VREF, and a second electrode is connected to the second node B.

The structure of the reset sub-circuit 46 in one exemplary embodiment is shown in fig. 11, but those skilled in the art will appreciate that the implementation of the reset sub-circuit is not limited thereto as long as the function thereof can be achieved.

Fig. 12 is a schematic diagram of an ultrasonic drive sub-circuit provided in an exemplary embodiment. As shown in fig. 12, the ultrasonic drive sub-circuit 60 may include: and a control electrode of the fifth transistor T5 is connected to the first SCAN signal terminal SCAN1, a first electrode of the fifth transistor T5 is connected to the first node a, and a second electrode of the fifth transistor T5 is connected to the second SCAN signal terminal SCAN2.

The structure of the ultrasonic drive sub-circuit 60 in one exemplary embodiment is shown in fig. 12, but those skilled in the art will appreciate that the implementation of the ultrasonic drive sub-circuit is not limited thereto as long as the function thereof can be achieved.

In an exemplary embodiment, as shown in fig. 13, the ultrasonic sensing sub-circuit 70 may employ an ultrasonic fingerprint sensor to transmit ultrasonic waves and receive ultrasonic echoes, which are converted into electrical signals. The ultrasonic fingerprint sensor may include a first pole, a second pole, and a layer of piezoelectric material sandwiched between the first pole and the second pole. The layer of piezoelectric material may include a polyvinylidene fluoride (PVDF) material. When the ultrasonic fingerprint sensor is used, a first pole of the ultrasonic fingerprint sensor is connected with the first node a, and a second pole of the ultrasonic fingerprint sensor is connected with the third power supply terminal Tx.

In an exemplary embodiment, when the first node a is a stable low voltage signal and the third power terminal Tx is an alternating voltage, the ultrasonic sensing unit 70 can transmit ultrasonic waves; when the third power Tx is at a stable voltage, the ultrasonic sensing sub-circuit 70 can receive the reflected ultrasonic echo and generate a first sensing signal at the first node a. The ultrasonic sensing sub-circuit 70 may use PVDF (polyvinylidene fluoride) to convert the ultrasonic echoes into electrical signals, as shown in fig. 13. Of course, other materials may be used to convert the ultrasonic echo, and the specific material may be selected according to the actual use situation, which is not limited herein. The first sensing signal may be a sensing voltage.

Fig. 14 is a schematic diagram of a signal acquisition sub-circuit provided in an exemplary embodiment. As shown in fig. 14, the signal collecting sub-circuit 80 includes a sixth transistor T6, a control electrode of the sixth transistor T6 is connected to the first node a, a first electrode is connected to the first power source terminal VDD, and a second electrode is connected to the output terminal OUT.

Fig. 15 is a schematic diagram of a signal acquisition sub-circuit provided in an exemplary embodiment. As shown in fig. 15, the signal collecting sub-circuit 80 includes a sixth transistor T6 and a seventh transistor T7, a control electrode of the sixth transistor T6 is connected to the first node a, a first electrode thereof is connected to the first power source terminal VDD, a second electrode thereof is connected to a first electrode of the seventh transistor T7, a control electrode of the seventh transistor T7 is connected to the second SCAN signal terminal SCAN2, and a second electrode thereof is connected to the output terminal OUT.

An exemplary structure of the signal acquisition sub-circuit 80 is shown in fig. 14 and 15, respectively, but those skilled in the art will appreciate that the implementation of the signal acquisition sub-circuit is not limited thereto as long as the function thereof can be achieved.

Fig. 16 is a schematic diagram of a pixel driving circuit according to an exemplary embodiment. As shown in fig. 16, the pixel driving circuit may include a pixel driving sub-circuit 40, an ultrasonic driving sub-circuit 60, an ultrasonic sensing sub-circuit 70, and a signal collecting sub-circuit 80, and the pixel driving sub-circuit 40 may include a compensation sub-circuit 41, a driving sub-circuit 42, a data writing sub-circuit 43, a first storage sub-circuit 44, a second storage sub-circuit 45, and a resetting sub-circuit 46, wherein:

the compensation sub-circuit 41 may include: a first transistor T1, a control electrode of the first transistor T1 being connected to the second SCAN signal terminal SCAN2, a first electrode being connected to the first power terminal VDD, and a second electrode being connected to the fourth node D;

the driving sub-circuit 42 may include: a third transistor T3, a control electrode of the third transistor T3 being connected to the second node B, a first electrode thereof being connected to the fourth node D, and a second electrode thereof being connected to the third node C;

the data writing sub-circuit 43 may include: a second transistor T2, a control electrode of the second transistor T2 being connected to the second SCAN signal terminal SCAN2, a first electrode being connected to the Data signal terminal Data, and a second electrode being connected to the second node B;

the reset sub-circuit 46 may include: a fourth transistor T4, a control electrode of the fourth transistor T4 is connected to the first SCAN signal terminal SCAN1, a first electrode is connected to the reference signal terminal VREF, and a second electrode is connected to the second node B;

the first memory sub-circuit 44 may include: a first capacitor C1, wherein a first pole of the first capacitor C1 is connected to the second node B, and a second pole of the first capacitor C1 is connected to the third node C;

the second memory sub-circuit 45 may include: a second capacitor C2, a first pole of the second capacitor C2 being connected to the third node C, and a second pole being connected to the second power supply terminal VSS;

the ultrasonic drive sub-circuit 60 may include: a fifth transistor T5, a control electrode of the fifth transistor T5 is connected to the first SCAN signal terminal SCAN1, a first electrode is connected to the first node a, and a second electrode is connected to the second SCAN signal terminal SCAN2;

the signal acquisition sub-circuit 80 may include: a sixth transistor T6 and a seventh transistor T7, wherein a control electrode of the sixth transistor T6 is connected to the first node a, a first electrode is connected to the first power terminal VDD, a second electrode is connected to a first electrode of the seventh transistor T7, a control electrode of the seventh transistor T7 is connected to the second SCAN signal terminal SCAN2, and a second electrode is connected to the output terminal OUT.

It will be appreciated by those skilled in the art that the transistors employed in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices of the same characteristics. The thin film transistor may be an oxide semiconductor thin film transistor, a low temperature polycrystalline silicon thin film transistor, an amorphous silicon thin film transistor, or a microcrystalline silicon thin film transistor. In addition, considering that the leakage current of the ltps tft is small, all the transistors of the embodiments of the present disclosure may be ltps tfts. The thin film transistor may be specifically a thin film transistor of a bottom gate structure or a thin film transistor of a top gate structure as long as a switching function can be achieved.

The pixel driving circuit provided by the embodiment can realize the echo collection of the sensor and the display luminescence of the panel, realize the integration of the fingerprint identification circuit and the backboard circuit under the condition of not increasing the whole thickness of the panel, and reduce the complexity of the pixel and Array substrate Gate Drive (GOA) area circuit In an In cell (embedded) type module mode. In addition, the pixel driving circuit provided by the embodiment has a 7T2C structure, uses fewer devices, and can reduce the cost.

In an exemplary embodiment, the first transistor T1 may be a P-type transistor, and the second to seventh transistors T2 to T7 may be N-type transistors. However, the embodiment of the present application is not limited thereto, and T1 to T7 may be other types of transistors.

The operation of the pixel driving circuit is described below by way of an example. The pixel drive circuit of this embodiment is shown in fig. 16. The first transistor T1 is a P-type transistor, and the second to seventh transistors T2 to T7 are N-type transistors. Fig. 17 is an operation timing chart of the pixel driving circuit provided in this embodiment; fig. 18 is a working state diagram of the pixel driving circuit in a pixel resetting stage, fig. 19 is a working state diagram of the pixel driving circuit in a pixel compensation and ultrasonic signal emission stage, fig. 20 is a working state diagram of the pixel driving circuit in an ultrasonic echo signal acquisition stage, fig. 21 is a working state diagram of the pixel driving circuit in a pixel signal writing and ultrasonic signal reading stage, and fig. 22 is a working state diagram of the pixel driving circuit in a pixel light emitting stage. The first power terminal VDD continuously provides a high level signal, the second power terminal VSS continuously provides a low level signal, and the reference signal terminal VREF provides a reference voltage signal VREF.

In the first phase t1, i.e., the pixel reset phase, tx is a stable voltage, the first SCAN signal terminal SCAN1 provides a high level signal, and the second SCAN signal terminal SCAN2 provides a high level signal.

As shown in fig. 18, in the first phase T1, since the second SCAN signal terminal SCAN2 provides a high level signal, the second transistor T2 is turned on for the N-type transistor, the seventh transistor T7 is turned on for the N-type transistor, and the first transistor T1 is turned off for the P-type transistor; since the first SCAN signal terminal SCAN1 provides a high level signal, the fifth transistor T5 is turned on, the second SCAN signal terminal SCAN2 writes a potential into the first node a through the fifth transistor T5, and the sixth transistor T6 is turned on. The fourth transistor T4 is an N-type transistor, which is turned on by a high level signal provided by the first SCAN signal terminal SCAN1, the voltage of the second node B is the voltage Vref provided by the reference signal terminal REF, the upper plate of the first capacitor C1 is reset to clear the data voltage in the first capacitor C1, and the Vref is a high level signal, so that the third transistor T3 is turned on, and the third transistor T3 is turned on in the next stage by the first capacitor C1 capable of maintaining the difference between the voltage values of the second node B and the third node C, in preparation for threshold compensation.

The second stage t2, the pixel compensation and ultrasound signal transmission stage. Tx is an alternating voltage, the first SCAN signal terminal SCAN1 provides a high level signal, and the second SCAN signal terminal SCAN2 provides a low level signal.

As shown in fig. 19, the second SCAN signal terminal SCAN2 provides a low level signal, the second transistor T2 is turned off, the seventh transistor T7 is turned off, the first transistor T1 is turned on, the first power terminal VDD signal reaches the third node C through the first transistor T1 and the third transistor T3 to charge the first capacitor C1, the voltage of the third node C continuously increases, and when the voltage of the third node C rises to Vref-Vth, the third transistor T3 is turned off, where Vth is the threshold voltage of the third transistor T3. The first SCAN signal terminal SCAN1 provides a high level signal, the fourth transistor T4 is turned on, the fifth transistor T5 is turned on, the second SCAN signal terminal SCAN2 writes a potential into the first node a through the fifth transistor T5, the third power supply terminal Tx is an alternating voltage, and the ultrasonic sensing unit 70 emits an ultrasonic wave to the outside under the control of the first node a and the third power supply terminal Tx. The first node a is a low level signal, the sixth transistor T6 is turned off, and the output terminal OUT has no output signal.

And a third stage t3, namely an ultrasonic echo signal acquisition stage. Tx is a stable voltage, the first SCAN signal terminal SCAN1 provides a low level signal, and the second SCAN signal terminal SCAN2 provides a low level signal.

As shown in fig. 20, the first SCAN signal terminal SCAN1 provides a low level signal, the fourth transistor T4 is turned off, the second SCAN signal terminal SCAN2 provides a low level signal, the second transistor T2 is turned off, the seventh transistor T7 is turned off, the third transistor T3 is turned off, the ultrasonic sensing unit 70 receives the returned ultrasonic echo, and an induced voltage is generated at the first node a. The first scanning signal terminal SCAN1 and the second scanning signal terminal SCAN2 are both low level signals, so that the fifth transistor T5 forms a diode connection, the fifth transistor T5 rectifies, accumulates and receives the induced voltage of the first node a, the potential of the first node a can be raised, and the current received by the subsequent output terminal OUT is larger. The induced voltage of the first node a controls the conduction degree of the sixth transistor T6.

And a fourth stage t4, namely a pixel signal writing and ultrasonic signal reading stage. Tx is a stable voltage, the first SCAN signal terminal SCAN1 provides a low level signal, and the second SCAN signal terminal SCAN2 provides a high level signal.

As shown in fig. 21, the first SCAN signal terminal SCAN1 provides a low level signal, the fourth transistor T4 is turned off, the fifth transistor T5 is turned off, the second SCAN signal terminal SCAN2 provides a high level signal, the first transistor T1 is turned off, the seventh transistor T7 is turned on, the second transistor T2 is turned on, the signal Vdata of the Data signal terminal Data is written into the second node B, that is, the voltage of the second node B is Vdata, and in order to maintain the voltage difference between the second node B and the third node C, the voltage of the third node C under the bootstrap action of the first capacitor C1 and the second capacitor C2 becomes (C1) and (C2) ₂ ·Vref+C ₁ ·Vdata)/(C ₁ +C ₂ )-Vth，C ₁ Is the capacitance value of the first capacitor C1, C ₂ The capacitance of the second capacitor C2 is, and the third transistor T3 is turned on. In addition, the seventh transistor T7 is turned on, the potential of the first node a controls the turn-on degree of the sixth transistor T6, and the ultrasonic echo signal, i.e., the second sensing signal, which is, for example, a sensing current, is read from the output terminal OUT row by row.

In the fifth phase t5, i.e. the pixel emitting phase, tx is a stable voltage, the first SCAN signal terminal SCAN1 outputs a low level signal, and the second SCAN signal terminal SCAN2 outputs a low level signal.

As shown in fig. 22, the first SCAN signal terminal SCAN1 outputs a low level signal, the fourth transistor T4 is turned off, the fifth transistor T5 is turned off, the second SCAN signal terminal SCAN2 outputs a low level signal, the first transistor T1 is turned on, the second transistor T2 is turned off, and the seventh transistor T7 is turned off. The third transistor T3 is turned on, the sixth transistor T6 is turned on, the first power terminal VDD is turned on through the first transistor T1, the third transistor T3 and the second power terminal VSS, and the light emitting unit 50 is driven to emit light, wherein the voltage Vg = Vdata of the control electrode of the third transistor T3. A voltage Vs = (C) of a second pole (one pole connected to the third node C) of the third transistor T3 ₂ ·Vref+C ₁ ·Vdata)/(C ₁ +C ₂ ) -Vth. Then, the current of the light emitting unit 50 is:

I＝W*C*u/(2*L)*(Vg-Vs-Vth)^2

＝W*C*u/(2*L)*(Vdata-(C ₂ ·Vref+C ₁ ·Vdata)/(C ₁ +C ₂ ))^2

wherein, W/L is the width-to-length ratio of the active layer of the third transistor T3, C is the gate oxide capacitance per unit area, and u is the mobility of the third transistor T3. Since the third power source terminal Tx is a continuously stable voltage, the ultrasonic sensing unit 70 does not emit ultrasonic waves to the outside.

Fig. 23 is a flowchart of a pixel driving method according to an embodiment of the present application. As shown in fig. 23, an embodiment of the present application provides a pixel driving method, which is applied to the pixel driving circuits provided in the above embodiments, and includes:

step 2301, in the second phase, under the control of the second scan signal terminal, turning on the first terminal power terminal and the third node to compensate the voltage of the third node, and under the control of the first scan signal terminal, providing the signal of the second scan signal terminal to the first node, and under the control of the first node and the third power terminal, the ultrasonic sensing sub-circuit emits ultrasonic waves;

the phase is a pixel compensation and ultrasound transmission phase in which the third power terminal Tx is an alternating voltage, the first SCAN signal terminal SCAN1 is a high level signal, and the second SCAN signal terminal SCAN is a low level signal. Since the first SCAN signal terminal SCAN1 is a high level signal, the fifth transistor T5 is turned on, so that the signal (low level signal) of the second SCAN signal terminal SCAN2 is supplied to the first node a, and further, the third power source terminal Tx is an alternating voltage, so that the ultrasonic sensing sub-circuit 70 emits ultrasonic waves. The second SCAN signal terminal SCAN2 is a low level signal, the second transistor T2 is turned off, the first transistor T1 is turned on, the third transistor T3 is turned on, and the first power source terminal VDD performs voltage compensation on the third node C, in this embodiment, the voltage of the third node C is charged to Vref-Vth;

step 2302, in a third stage, receiving the reflected ultrasonic echo, generating a first sensing signal at the first node, and rectifying the first sensing signal by the ultrasonic driving sub-circuit under the control of the first scanning signal terminal and the second scanning signal terminal;

the phase is an ultrasonic echo signal acquisition phase, the third power supply end Tx is stable voltage, the first scanning signal end SCAN1 provides a low-level signal, and the second scanning signal end SCAN2 provides a low-level signal.

Step 2303, in the fourth phase, writing the signal of the data signal terminal into the pixel driving sub-circuit under the control of the second scan signal terminal to change the voltage of the third node, and outputting a second sensing signal to the output terminal under the control of the first sensing signal of the first node;

the phase is a pixel signal writing-in phase and an ultrasonic signal reading-out phase, in the phase, the third power supply end Tx is a stable voltage, the first SCAN signal end SCAN1 provides a low-level signal, and the second SCAN signal end SCAN2 provides a high-level signal. In this stage, the second SCAN signal terminal SCAN2 provides a high level signal, the second transistor T2 is turned on, and the voltage of the Data signal terminal Data is written into the pixel driving sub-circuit, so that the third node C generates a jump due to the bootstrap effect of the capacitor.

Step 2304, in a fifth phase, under the control of the second scan signal terminal, turning on the first power terminal and the third node, and providing a driving signal to the light emitting unit through the third node.

The phase is a pixel light emitting phase, in which the third power source terminal Tx is a stable voltage, the first SCAN signal terminal SCAN1 outputs a low level signal, and the second SCAN signal terminal SCAN2 outputs a low level signal. The second SCAN signal terminal SCAN2 outputs a low level signal, the first transistor T1 is turned on, the third node C generates a transition due to a capacitor bootstrap, the third transistor T3 is turned on, the first power terminal VDD is turned on with the second power terminal VSS through the first transistor T1 and the third transistor T3, and the light emitting unit 50 is driven to emit light.

The pixel driving method provided by the embodiment realizes the display luminescence of the panel and the echo collection of the ultrasonic signal.

the compensation sub-circuit is respectively connected with the first power supply terminal, the second scanning signal terminal and the fourth node, and is configured to provide a signal of the first power supply terminal to the fourth node under the control of the second scanning signal terminal;

the data writing sub-circuit is respectively connected with the data signal end, the second scanning signal end and the second node and is set to write the voltage of the data signal end into the second node under the control of the second scanning signal end;

the driving method further includes, in a first stage, supplying a signal of the reference signal terminal to the second node under the control of the first scan signal terminal.

An embodiment of the present application further provides a display device, including the pixel driving circuit of the foregoing embodiment. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

Although the embodiments disclosed in the present disclosure are described above, the descriptions are only for the purpose of understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art of the present disclosure that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the disclosure is to be limited only by the terms of the appended claims.

Claims

1. A pixel driving circuit comprising: the ultrasonic drive circuit comprises a pixel drive sub-circuit, an ultrasonic sensing sub-circuit and a signal acquisition sub-circuit, wherein the pixel drive sub-circuit comprises: first to fourth transistors, the ultrasonic drive sub-circuit including: a fifth transistor, the signal acquisition sub-circuit comprising: a sixth transistor and a seventh transistor, wherein:

a first pole of the ultrasonic sensing sub-circuit is connected with a first node, a second pole of the ultrasonic sensing sub-circuit is connected with a third power supply end, and the ultrasonic sensing sub-circuit is configured to emit ultrasonic waves according to signals of the first node and the third power supply end and receive reflected ultrasonic echoes to generate a first sensing signal at the first node;

the signal acquisition sub-circuit is respectively connected with the first power supply end, the first node, the second scanning signal end and the output end, and is set to output a second sensing signal to the output end according to the first power supply end and the first sensing signal under the control of the first sensing signal and the second scanning signal end of the first node;

the first transistor is a P-type transistor, and the second to seventh transistors are N-type transistors.

2. The pixel driving circuit according to claim 1, wherein the pixel driving sub-circuit comprises: a compensation sub-circuit, a drive sub-circuit, a data write sub-circuit, a first storage sub-circuit, and a second storage sub-circuit, wherein:

3. The pixel driving circuit of claim 2, wherein the compensation sub-circuit comprises: and a control electrode of the first transistor is connected with the second scanning signal end, a first electrode of the first transistor is connected with the first power supply end, and a second electrode of the first transistor is connected with the fourth node.

4. The pixel driving circuit according to claim 2, wherein the driving sub-circuit comprises: and a third transistor having a control electrode connected to the second node, a first electrode connected to the fourth node, and a second electrode connected to the third node.

5. The pixel driving circuit according to claim 2, wherein the data writing sub-circuit comprises: and a control electrode of the second transistor is connected with the second scanning signal end, a first electrode of the second transistor is connected with the data signal end, and a second electrode of the second transistor is connected with the second node.

6. The pixel driving circuit according to claim 2, wherein the first storage sub-circuit comprises: and a first pole of the first capacitor is connected with the second node, and a second pole of the first capacitor is connected with the third node.

7. The pixel driving circuit according to claim 2, wherein the second storage sub-circuit comprises: and a first pole of the second capacitor is connected with the third node, and a second pole of the second capacitor is connected with the second power supply end.

8. The pixel driving circuit according to claim 2, further comprising a reset sub-circuit, wherein the reset sub-circuit is respectively connected to the first scan signal terminal, the reference signal terminal and the second node, and the reset sub-circuit is configured to provide the signal of the reference signal terminal to the second node under the control of the first scan signal terminal.

9. The pixel driving circuit of claim 8, wherein the reset sub-circuit comprises: and a control electrode of the fourth transistor is connected with the first scanning signal end, a first electrode of the fourth transistor is connected with the reference signal end, and a second electrode of the fourth transistor is connected with the second node.

10. The pixel driving circuit according to claim 1, wherein a control electrode of the fifth transistor is connected to the first scan signal terminal, a first electrode is connected to the first node, and a second electrode is connected to the second scan signal terminal.

11. The pixel driving circuit according to claim 1, wherein a control electrode of the sixth transistor is connected to the first node, a first electrode of the sixth transistor is connected to the first power source terminal, a second electrode of the sixth transistor is connected to the first electrode of the seventh transistor, a control electrode of the seventh transistor is connected to the second scan signal terminal, and a second electrode of the seventh transistor is connected to the output terminal.

12. The pixel driving circuit of claim 2, wherein the pixel driving sub-circuit further comprises a reset sub-circuit, wherein:

the compensation sub-circuit comprises: a first transistor, a control electrode of which is connected to the second scan signal terminal, a first electrode of which is connected to the first power terminal, and a second electrode of which is connected to the fourth node;

the first storage sub-circuit comprises: a first capacitor, a first pole of which is connected to the second node and a second pole of which is connected to the third node;

the second storage sub-circuit comprises: a second capacitor, a first pole of the second capacitor being connected to the third node, and a second pole of the second capacitor being connected to the second power supply terminal;

a control electrode of the fifth transistor is connected with the first scanning signal end, a first electrode of the fifth transistor is connected with the first node, and a second electrode of the fifth transistor is connected with the second scanning signal end;

a control electrode of the sixth transistor is connected to the first node, a first electrode of the sixth transistor is connected to the first power terminal, a second electrode of the sixth transistor is connected to the first electrode of the seventh transistor, a control electrode of the seventh transistor is connected to the second scan signal terminal, and a second electrode of the seventh transistor is connected to the output terminal.

13. A display device comprising the pixel drive circuit according to any one of claims 1 to 12.

14. A pixel driving method applied to the pixel driving circuit according to any one of claims 1 to 12, the pixel driving method comprising:

in the second stage, under the control of the second scanning signal terminal, the first power terminal and the third node are conducted to compensate the voltage of the third node, and under the control of the first scanning signal terminal, the signal of the second scanning signal terminal is provided to the first node, and under the control of the first node and the third power terminal, the ultrasonic sensing sub-circuit emits ultrasonic waves;

in a fourth phase, under the control of the second scanning signal terminal, writing the signal of the data signal terminal into the pixel driving sub-circuit to change the voltage of the third node, and under the control of the first sensing signal of the first node and the second scanning signal terminal, outputting a second sensing signal to the output terminal;

15. The pixel driving method according to claim 14, wherein the pixel driving sub-circuit comprises: the data writing circuit comprises a compensation sub-circuit, a driving sub-circuit, a data writing sub-circuit, a first storage sub-circuit, a second storage sub-circuit and a resetting sub-circuit;

the second storage sub-circuit is respectively connected with the third node and the second power supply end and is configured to store a voltage value between the third node and the second power supply end;

in the second stage, the turning on the first power source terminal and the third node under the control of the second scan signal terminal, and the compensating the voltage of the third node includes:

and under the control of the second scanning signal end, writing the signal of the data signal end into the second node, and jumping the voltage value of the third node under the action of the first storage sub-circuit and the second storage sub-circuit.

16. The pixel driving method according to claim 15, wherein the pixel driving sub-circuit further comprises a reset sub-circuit, the reset sub-circuits are respectively connected to the first scan signal terminal, the reference signal terminal and the second node, the reset sub-circuit is configured to provide the signal of the reference signal terminal to the second node under the control of the first scan signal terminal;