CN112559425A - PCIE port splitting method, device, equipment and medium - Google Patents

PCIE port splitting method, device, equipment and medium Download PDF

Info

Publication number
CN112559425A
CN112559425A CN202011363559.2A CN202011363559A CN112559425A CN 112559425 A CN112559425 A CN 112559425A CN 202011363559 A CN202011363559 A CN 202011363559A CN 112559425 A CN112559425 A CN 112559425A
Authority
CN
China
Prior art keywords
pcie
target
port
splitting
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202011363559.2A
Other languages
Chinese (zh)
Inventor
张晨熙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Original Assignee
Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd filed Critical Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority to CN202011363559.2A priority Critical patent/CN112559425A/en
Publication of CN112559425A publication Critical patent/CN112559425A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4411—Configuring for operating with peripheral devices; Loading of device drivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Abstract

The application discloses a PCIE port splitting method which is applied to a target processor which cannot dynamically split a PCIE port; the method comprises the following steps: a PCIE bridge is connected to a PCIE port of a target processor in advance, and when the target PCIE device is connected with the PCIE bridge, backboard information of the target PCIE device is obtained; searching target port distribution information corresponding to the backboard information from the target configuration file; the target configuration file is a file which is written in advance according to PCIE ports needing to be allocated to different types of PCIE equipment; and splitting the PCIE port of the PCIE bridge according to the target port distribution information. Obviously, the method can realize the dynamic splitting of the PCIE port without re-burning the BIOS and modifying a hardware link of the processor, thereby obviously improving the convenience of the PCIE port processor which cannot be dynamically split in the using process.

Description

PCIE port splitting method, device, equipment and medium
Technical Field
The present invention relates to the technical field of servers, and in particular, to a method, an apparatus, a device, and a medium for splitting a PCIE port.
Background
In the prior art, only one type of PCIE (Peripheral Component Interconnect Express) port is provided in many processors. Because the PCIE port of the processor cannot be dynamically split, the application of the PCIE port in the market is greatly limited. In this case, if the PCIE ports in such a processor are to be split, the splitting of the PCIE ports can only be achieved by rewriting a BIOS (Basic Input Output System) and changing a hardware link of the processor, which greatly reduces the convenience of the processor in the actual use process.
Therefore, how to improve the convenience of the PCIE port processor incapable of being dynamically split in the using process is a technical problem to be urgently solved by those skilled in the art.
Disclosure of Invention
In view of this, an object of the present invention is to provide a method, an apparatus, a device and a medium for splitting a PCIE port, so as to improve convenience of a processor that cannot dynamically split the PCIE port in a using process. The specific scheme is as follows:
a PCIE port splitting method is applied to a target processor which cannot dynamically split a PCIE port; the method comprises the following steps:
a PCIE bridge is connected to a PCIE port of the target processor in advance, and when the target PCIE device is connected with the PCIE bridge, backboard information of the target PCIE device is obtained;
searching target port distribution information corresponding to the backboard information from a target configuration file; the target configuration file is a file which is written in advance according to PCIE ports needing to be allocated to different types of PCIE equipment;
and splitting the PCIE port of the PCIE bridge according to the target port distribution information.
Preferably, the PCIE bridge is specifically PM 8565.
Preferably, the target PCIE device includes a PCIE backplane and/or an NVME hard disk backplane.
Preferably, the process of acquiring backplane information of the target PCIE device includes:
and acquiring the backplane information of the target PCIE equipment through the GPIO of the PM 8565.
Preferably, the target configuration file is a file written by utilizing chiplink software.
Preferably, the process of splitting the PCIE port of the PCIE bridge according to the target port allocation information includes:
and performing X4 and/or X8 and/or X16 splitting on the PCIE ports of the PCIE bridge according to the target port distribution information.
Correspondingly, the invention also discloses a PCIE port splitting device, which is applied to a target processor which can not dynamically split the PCIE port; the method comprises the following steps:
the information acquisition module is used for connecting a PCIE bridge on a PCIE port of the target processor in advance, and acquiring the back plate information of the target PCIE device when the target PCIE device is connected with the PCIE bridge;
the information searching module is used for searching target port distribution information corresponding to the backboard information from a target configuration file; the target configuration file is a file which is written in advance according to PCIE ports needing to be allocated to different types of PCIE equipment;
and the port splitting module is used for splitting the PCIE port of the PCIE bridge according to the target port distribution information.
Correspondingly, the invention also discloses a device for splitting the PCIE port, which comprises:
a memory for storing a computer program;
a processor, configured to implement the steps of the method for splitting a PCIE port as disclosed in the foregoing when executing the computer program.
Correspondingly, the present invention also discloses a computer readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the steps of the method for splitting a PCIE port as disclosed above are implemented.
Therefore, in the present invention, a PCIE bridge is connected to a PCIE port of a target processor in advance, and a target configuration file is compiled according to PCIE ports required to be allocated by PCIE devices of different types; therefore, when the target PCIE device is connected with the PCIE bridge, the PCIE port of the target processor can be led out by using the PCIE bridge, then what type of PCIE port needs to be configured by the target PCIE device can be known by obtaining the back plate attribute information of the target PCIE device, then the target port distribution information corresponding to the back plate attribute information of the target PCIE device is searched from the target configuration file, the port setting program corresponding to the target PCIE device can be obtained, and finally the PCIE port of the PCIE bridge is split by using the target port distribution information, namely the PCIE port of the target processor is dynamically split. Obviously, the method can realize the dynamic splitting of the PCIE port without re-burning the BIOS and modifying a hardware link of the processor, thereby obviously improving the convenience of the PCIE port processor which cannot be dynamically split in the using process. Correspondingly, the device, the equipment and the medium for splitting the PCIE port provided by the invention also have the beneficial effects.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of a method for splitting a PCIE port according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating a splitting of a PCIE port of a CPU0 in a tenuous cloud S2500 according to an embodiment of the present invention;
fig. 3 is a structural diagram of a splitting apparatus of a PCIE port according to an embodiment of the present invention;
fig. 4 is a structural diagram of a splitting device of a PCIE port according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a flowchart of a method for splitting a PCIE port according to an embodiment of the present invention, where the method is applied to a target processor that cannot dynamically split the PCIE port; the method comprises the following steps:
step S11: a PCIE bridge is connected to a PCIE port of a target processor in advance, and when the target PCIE device is connected with the PCIE bridge, backboard information of the target PCIE device is obtained;
step S12: searching target port distribution information corresponding to the backboard information from the target configuration file;
the target configuration file is a file which is written in advance according to PCIE ports needing to be allocated to different types of PCIE equipment;
step S13: and splitting the PCIE port of the PCIE bridge according to the target port distribution information.
In this embodiment, in order to split a PCIE port of a target processor that cannot dynamically split a PCIE port, a PCIE bridge is connected to the PCIE port of the target processor in advance, and a target configuration file is written according to PCIE ports that need to be allocated by PCIE devices of different types in advance.
It can be understood that, when the target PCIE device establishes a connection with the PCIE bridge connected to the target processor, the PCIE bridge may be used to lead out the PCIE port of the target processor, and in this case, the backplane information of the target PCIE device is obtained. It can be understood that, when the backplane information of the target PCIE device is obtained, the type of the PCIE ports of the target PCIE device and the number of the corresponding PCIE ports can be known through the backplane information.
Then, target port allocation information corresponding to the backplane information is searched from the target configuration file, and the PCIE ports of the PCIE bridge are split according to the searched target port allocation information. It can be thought that, because the target configuration file is a file written in advance according to the PCIE ports that need to be allocated to different types of PCIE devices, the target configuration file stores therein configuration programs that are needed by PCIE ports corresponding to various PCIE devices. Therefore, when the target port allocation information corresponding to the backplane information is found from the target configuration file, the PCIE ports of the PCIE bridge can be split according to the target port allocation information, that is, the PCIE ports of the PCIE bridge are split into PCIE ports of different numbers and different types according to the target port allocation information. Obviously, after the PCIE ports of the PCIE bridge are split, it is equivalent to splitting the PCIE ports of the target processor.
Compared with the prior art, the method can realize the dynamic splitting of the PCIE port of the target processor without burning the BIOS again and modifying a hardware link of the processor, so that the convenience of the target processor in the use process can be obviously improved.
As can be seen, in this embodiment, a PCIE bridge is connected to a PCIE port of a target processor in advance, and a target configuration file is written according to PCIE ports required to be allocated by PCIE devices of different types; therefore, when the target PCIE device is connected with the PCIE bridge, the PCIE port of the target processor can be led out by using the PCIE bridge, then what type of PCIE port needs to be configured by the target PCIE device can be known by obtaining the back plate attribute information of the target PCIE device, then the target port distribution information corresponding to the back plate attribute information of the target PCIE device is searched from the target configuration file, the port setting program corresponding to the target PCIE device can be obtained, and finally the PCIE port of the PCIE bridge is split by using the target port distribution information, namely the PCIE port of the target processor is dynamically split. Obviously, the method can realize the dynamic splitting of the PCIE port without re-burning the BIOS and modifying a hardware link of the processor, thereby obviously improving the convenience of the PCIE port processor which cannot be dynamically split in the using process.
Based on the foregoing embodiments, this embodiment further describes and optimizes the technical solution, and as a preferred implementation, the target PCIE device includes a PCIE backplane and/or an NVME hard disk backplane.
In this embodiment, the target PCIE device includes a PCIE backplane and/or an NVME (Non Volatile Memory standard) hard disk backplane, and because the PCIE backplane and/or the NVME hard disk backplane are the most common PCIE devices in the practical operation process, when the target PCIE device is set as the PCIE backplane and/or the NVME hard disk backplane, the universality of the method provided by the present application in practical application can be relatively improved.
Based on the above embodiments, this embodiment further describes and optimizes the technical solution, and as a preferred implementation, the PCIE bridge is specifically the PM 8565.
It can be understood that, in this embodiment, the PCIE bridge is set as the PM8565, because the PM8565 has not only a stable data transmission function but also low manufacturing cost compared to other types of PCIE bridges.
As a preferred embodiment, the above steps: the process of obtaining backplane information of a target PCIE device includes:
and acquiring backplane information of the target PCIE device through the GPIO of the PM 8565.
In the actual operation process, the target PCIE device may be directly connected to a GPIO (General Purpose Input/Output) of the PM8565 through a cable, and the line connection process is convenient and flexible, so in this embodiment, the backplane information of the target PCIE device is obtained through the GPIO of the PM 8565.
Obviously, by the technical scheme provided by this embodiment, convenience in the process of establishing connection between the target PCIE device and the PM8565 can be relatively improved.
As a preferred embodiment, the target configuration file is specifically a file written by using chiplink software.
It can be understood that, because the chiplink software is file writing software used in cooperation with the PM8565, PCIE port programs required by PCIE devices of different types can be directly written by using the chiplink software, so that the compiling difficulty of the target configuration file in the writing process can be significantly reduced by using the chiplink software.
Based on the above embodiments, this embodiment further describes and optimizes the technical solution, and as a preferred implementation, the above steps: the process of splitting the PCIE port of the PCIE bridge according to the target port distribution information comprises the following steps:
and performing X4 and/or X8 and/or X16 splitting on the PCIE ports of the PCIE bridge according to the target port distribution information.
It can be understood that, in practical applications, the types of PCIE ports of PCIE devices that are relatively common are X4 and/or X8 and/or X16, and therefore, in the process of splitting the PCIE ports of the PCIE bridge according to the target port allocation information, the PCIE ports of the PCIE bridge may be split by X4 using the root target port allocation information, or the PCIE ports of the PCIE bridge may be split by X8 and/or X16 using the target port allocation information.
Based on the technical content disclosed in the above embodiments, the present embodiment will be described in detail through a practical application scenario. In practical applications, because the PCIE port resources of the feiteng processor are very small and the dynamic partition of the PCIE ports cannot be performed, in this case, the application of the feiteng processor in the market is greatly limited, so in this embodiment, a soar S2500 two-way interconnection server in the feiteng processor is taken as an example to be specifically described.
Because there are two CPUs in the Tengyun S2500 two-way interconnection server, that is, the CPU0 and the CPU1, and the PCIE port splitting methods of the CPU0 and the CPU1 are the same, in this embodiment, only the PCIE port splitting of the CPU0 is taken as an example for specific description.
Firstly, in order to split a PCIE port of the CPU0, the PM8565 is connected to the PCIE port of the CPU0 in advance, and two GPIO ports, that is, GPIO-01 and GPIO-02, are defined on the PCIE backplane and the NVME hard disk backplane, respectively. Specifically, referring to fig. 2, fig. 2 is a schematic diagram illustrating splitting of a PCIE port of a CPU0 in a tengyun S2500 according to an embodiment of the present invention. And GPIO-01 and GPIO-02 on the PCIE backplane and the NVME hard disk backplane are respectively connected with the PM8565 through slim lines. When the PCIE backplane and the NVME hard disk backplane establish communication connection with the PM8565, the PM8565 collects the board card state of the PCIE backplane or the NVME hard disk backplane through GPIO-01 and GPIO-02.
It can be understood that since the Slimline is an interface of a PCIE high-speed connector, the PM8565 and the PCIE backplane or the NVME hard disk backplane can be indirectly connected through the Slimline, and the purpose of this embodiment is to dynamically split the PCIE port of the CPU0 by setting the interface type of the Slimline.
Please refer to table 1, where table 1 is related configuration information when a PCIE backplane and an NVME hard disk backplane need to split a PCIE port. Wherein, 0 represents GPIO as low level, 1 represents GPIO as high level, Slimline-1 and Slimline-3 are respectively connectors on the mainboard, the uplink device of the connector is PM8565, and the downlink port of the connector is connected with the backplane through a cable. Therefore, Slimline-1 in Table 1 represents the split state of the Slimline1, and Slimline-3 represents the split state of the Slimline3, i.e., the PCIE split state of the backplane.
Figure BDA0002804735310000071
When the PCIE backplane and the NVME hard disk backplane are connected to the PM8565, it can be known what type of PCIE ports and how many PICE ports need to be configured by detecting the level state of the corresponding GPIO port of the PM 8565. In this case, the PCIE port of the PM8565 can be split and configured by downloading the corresponding firmware program from the target configuration file, so that the purpose of connecting the PCIE backplane, the NVME hard disk backplane and the CPU0 in the tengyun S2500 can be achieved.
Obviously, according to the technical scheme provided by this embodiment, the dynamic splitting of the PCIE port can be realized without burning the BIOS again and modifying the hardware link of the processor, so that the convenience of the tenue S2500 two-way interconnection server in the use process can be further improved.
Referring to fig. 3, fig. 3 is a structural diagram of a splitting device for PCIE ports according to an embodiment of the present invention, where the splitting device includes:
the information obtaining module 21 is configured to connect a PCIE bridge to a PCIE port of the target processor in advance, and when the target PCIE device is connected to the PCIE bridge, obtain backplane information of the target PCIE device;
the information searching module 22 is configured to search target port allocation information corresponding to the backplane information from the target configuration file; the target configuration file is a file which is written in advance according to PCIE ports needing to be allocated to different types of PCIE equipment;
the port splitting module 23 is configured to split a PCIE port of the PCIE bridge according to the target port allocation information.
The device for splitting the PCIE port provided by the embodiment of the invention has the beneficial effects of the method for splitting the PCIE port disclosed by the embodiment of the invention.
Referring to fig. 4, fig. 4 is a structural diagram of a splitting device of a PCIE port according to an embodiment of the present invention, where the splitting device includes:
a memory 31 for storing a computer program;
the processor 32 is configured to implement the steps of the method for splitting a PCIE port as disclosed in the foregoing when executing the computer program.
The splitting device for the PCIE port provided by the embodiment of the invention has the beneficial effects of the splitting method for the PCIE port disclosed by the embodiment of the invention.
Correspondingly, the embodiment of the present invention further discloses a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the method for splitting the PCIE port as disclosed above are implemented.
The computer-readable storage medium provided by the embodiment of the invention has the beneficial effects of the method for splitting the PCIE port disclosed above.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The method, the apparatus, the device and the medium for splitting a PCIE port provided by the present invention are described in detail above, a specific example is applied in the present disclosure to explain the principle and the implementation manner of the present invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims (9)

1. A PCIE port splitting method is characterized in that the method is applied to a target processor which cannot dynamically split the PCIE port; the method comprises the following steps:
a PCIE bridge is connected to a PCIE port of the target processor in advance, and when the target PCIE device is connected with the PCIE bridge, backboard information of the target PCIE device is obtained;
searching target port distribution information corresponding to the backboard information from a target configuration file; the target configuration file is a file which is written in advance according to PCIE ports needing to be allocated to different types of PCIE equipment;
and splitting the PCIE port of the PCIE bridge according to the target port distribution information.
2. The method for splitting according to claim 1, wherein said PCIE bridge is specifically a PM 8565.
3. The splitting method according to claim 1, wherein the target PCIE device includes a PCIE backplane and/or an NVME hard disk backplane.
4. The splitting method according to claim 2, wherein the process of obtaining backplane information of the target PCIE device includes:
and acquiring the backplane information of the target PCIE equipment through the GPIO of the PM 8565.
5. The splitting method according to claim 2, wherein the target configuration file is specifically a file written by using chiplink software.
6. The method according to any one of claims 1 to 5, wherein the process of splitting the PCIE ports of the PCIE bridge according to the target port allocation information includes:
and performing X4 and/or X8 and/or X16 splitting on the PCIE ports of the PCIE bridge according to the target port distribution information.
7. A splitting device of a PCIE port is characterized in that the device is applied to a target processor which cannot dynamically split the PCIE port; the method comprises the following steps:
the information acquisition module is used for connecting a PCIE bridge on a PCIE port of the target processor in advance, and acquiring the back plate information of the target PCIE device when the target PCIE device is connected with the PCIE bridge;
the information searching module is used for searching target port distribution information corresponding to the backboard information from a target configuration file; the target configuration file is a file which is written in advance according to PCIE ports needing to be allocated to different types of PCIE equipment;
and the port splitting module is used for splitting the PCIE port of the PCIE bridge according to the target port distribution information.
8. A split device of PCIE port is characterized by comprising:
a memory for storing a computer program;
a processor configured to implement the steps of the method for splitting a PCIE port according to any one of claims 1 to 6 when executing the computer program.
9. A computer-readable storage medium, having stored thereon a computer program which, when being executed by a processor, implements the steps of a method for splitting a PCIE port as recited in any one of claims 1 to 6.
CN202011363559.2A 2020-11-27 2020-11-27 PCIE port splitting method, device, equipment and medium Pending CN112559425A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011363559.2A CN112559425A (en) 2020-11-27 2020-11-27 PCIE port splitting method, device, equipment and medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011363559.2A CN112559425A (en) 2020-11-27 2020-11-27 PCIE port splitting method, device, equipment and medium

Publications (1)

Publication Number Publication Date
CN112559425A true CN112559425A (en) 2021-03-26

Family

ID=75046559

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011363559.2A Pending CN112559425A (en) 2020-11-27 2020-11-27 PCIE port splitting method, device, equipment and medium

Country Status (1)

Country Link
CN (1) CN112559425A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113849045A (en) * 2021-08-25 2021-12-28 苏州浪潮智能科技有限公司 Backplate and computer equipment
CN114185720A (en) * 2022-02-17 2022-03-15 浪潮(山东)计算机科技有限公司 Method, device, equipment and storage medium for server dynamic hot backup
CN114911740A (en) * 2022-06-02 2022-08-16 中国长城科技集团股份有限公司 PCIe splitting method and device, electronic equipment and readable storage medium
WO2023137963A1 (en) * 2022-01-18 2023-07-27 苏州浪潮智能科技有限公司 Pcie device positioning method and apparatus, and related device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106959932A (en) * 2017-04-14 2017-07-18 广东浪潮大数据研究有限公司 A kind of Riser card methods for designing of automatic switchover PCIe signals
CN109376106A (en) * 2018-09-18 2019-02-22 郑州云海信息技术有限公司 A kind of PCIE expansion system and method for server
CN110399217A (en) * 2019-06-27 2019-11-01 苏州浪潮智能科技有限公司 A kind of memory source distribution method, device and equipment
CN211062037U (en) * 2019-12-30 2020-07-21 苏州浪潮智能科技有限公司 PCIE Switch product architecture capable of improving production efficiency

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106959932A (en) * 2017-04-14 2017-07-18 广东浪潮大数据研究有限公司 A kind of Riser card methods for designing of automatic switchover PCIe signals
CN109376106A (en) * 2018-09-18 2019-02-22 郑州云海信息技术有限公司 A kind of PCIE expansion system and method for server
CN110399217A (en) * 2019-06-27 2019-11-01 苏州浪潮智能科技有限公司 A kind of memory source distribution method, device and equipment
CN211062037U (en) * 2019-12-30 2020-07-21 苏州浪潮智能科技有限公司 PCIE Switch product architecture capable of improving production efficiency

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113849045A (en) * 2021-08-25 2021-12-28 苏州浪潮智能科技有限公司 Backplate and computer equipment
CN113849045B (en) * 2021-08-25 2023-06-16 苏州浪潮智能科技有限公司 Backboard and computer equipment
WO2023137963A1 (en) * 2022-01-18 2023-07-27 苏州浪潮智能科技有限公司 Pcie device positioning method and apparatus, and related device
CN114185720A (en) * 2022-02-17 2022-03-15 浪潮(山东)计算机科技有限公司 Method, device, equipment and storage medium for server dynamic hot backup
CN114185720B (en) * 2022-02-17 2022-05-10 浪潮(山东)计算机科技有限公司 Method, device, equipment and storage medium for dynamic hot backup of server
CN114911740A (en) * 2022-06-02 2022-08-16 中国长城科技集团股份有限公司 PCIe splitting method and device, electronic equipment and readable storage medium

Similar Documents

Publication Publication Date Title
CN112559425A (en) PCIE port splitting method, device, equipment and medium
CN108712457B (en) Method and device for adjusting dynamic load of back-end server based on Nginx reverse proxy
CN108763124B (en) PCIE Riser card
CN111901164B (en) Adaptive control method, device, equipment and system of OCP NIC network card
US20070139898A1 (en) System motherboard having expansibility and variability
CN109947682B (en) Server mainboard and server
CN212135411U (en) IO module and OCP keysets
US20170215296A1 (en) Multi-bay apparatus
TW200537315A (en) PCI express computer system
CN211427338U (en) Server mainboard based on explain majestic treaters
CN111625356A (en) PCIe device resource pooling method, device, equipment and medium
KR102265653B1 (en) Socket interposer and computer system using the socket interposer
US10831590B2 (en) Error handling
CN211506475U (en) Connecting device of OCP network card mutil-host
CN109002373A (en) Database connects abnormality eliminating method and device
US11356383B2 (en) Cloud translation mechanism
CN204189089U (en) A kind of server
CN114780436A (en) Method and device for directionally cleaning system data
CN110753082B (en) Service calling method and terminal equipment
CN112818336A (en) Data access method, data access device and computer readable storage medium
CN114490475A (en) PCI-E adapter card, network card access method, device, equipment and medium
CN214896408U (en) Mainboard and computer equipment
CN111273747A (en) System for 2U case rear window multi-PCIE external plug-in card
CN112818267A (en) Data processing method and device, computer readable storage medium and electronic equipment
CN114020668B (en) Signal processing system, mainboard and server

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20210326