CN112543349B - Multi-port high-speed data synchronous transmission method - Google Patents
Multi-port high-speed data synchronous transmission method Download PDFInfo
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- CN112543349B CN112543349B CN202011364620.5A CN202011364620A CN112543349B CN 112543349 B CN112543349 B CN 112543349B CN 202011364620 A CN202011364620 A CN 202011364620A CN 112543349 B CN112543349 B CN 112543349B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/236—Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator] into a video stream, multiplexing software data into a video stream; Remultiplexing of multiplex streams; Insertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rate; Assembling of a packetised elementary stream
- H04N21/23602—Multiplexing isochronously with the video sync, e.g. according to bit-parallel or bit-serial interface formats, as SDI
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/242—Synchronization processes, e.g. processing of PCR [Program Clock References]
Abstract
A multi-port high-speed data synchronous transmission method belongs to the technical field of gigabit high-speed data transmission. The method comprises the following steps: 1. designing a data frame structure according to the data volume of the effective load and the transmission rate; 2. establishing a link overhead codeword in a transmission frame structure; 3. calculating the byte length of a data transmission frame; 4. and carrying out multi-port synchronous transmission processing by using the synchronous signal. The method can realize the decision of various data transmission frame types and the synchronous sending capability of multi-port data, has higher effective load data occupation ratio due to the adoption of a self-defined lightweight transmission protocol, has flexible configuration of parameters such as effective load data quantity, overhead code words and the like in a frame structure, is suitable for high-speed data transmission systems with different transmission rates and different port quantities, and has wide application range.
Description
Technical Field
The invention relates to a multiport high-speed data synchronous transmission method, in particular to a multiport high-speed data synchronous transmission method which can be applied to a digital transparent processor system, a high-throughput satellite system and various multipoint-to-multipoint high-speed data transmission systems and belongs to the technical field of gigabit high-speed data transmission.
Background
Compared with an analog transparent processor system, the digital transparent processor system has the characteristics of large port data volume, large single-port bandwidth, large single-port channelized sub-band scale, strong sub-band exchange flexibility and the like, and can support the function of sub-band data exchange between any sub-channels. The characteristics lead the characteristics of large exchange data volume and high data rate in the multi-port ultra-large capacity sub-band route exchange process, and the total amount of transmitted data is up to dozens, even hundreds of Gbps. At present, the hardware level is difficult to bear such huge data transmission in a single port, and the data transmission is usually completed after the hardware level is split into multiple ports. In order to meet the requirement of miniaturization of products, the number of the data links after splitting needs to be reduced as much as possible, which requires that the transmission capacity on each data link needs to be improved as much as possible, and therefore it is very important to design a link transmission frame format with high robustness. In the multi-port switching process of the digital transparent processor, sub-band transmission data from external input has a plurality of different frame types, and in the transmission process, the sequence of the frame types at a receiving end is strictly ensured to be consistent with that at a sending end, so that the abnormal states such as dislocation and the like of the sub-band sequence before and after switching can be ensured. The multi-port sub-band data received at the exchange end must be from the transmission data of the same frame, and multi-port synchronous reception processing is required to ensure the sub-band data received by the multi-port. In the data transmission process, the reason for causing the asynchronous receiving of the multi-port data is mainly divided into two parts: firstly, the multi-port of the sending end is asynchronous; secondly, the time delay in the multi-port data transmission path is inconsistent. Aiming at the problem of asynchronous receiving of multi-port links, a synchronization mechanism can be adopted at a receiving end for processing, but the processing capacity of the synchronization mechanism is limited, and in order to reduce the complexity of the synchronization mechanism of the receiving end, data of multiple ports need to be ensured to be kept synchronous at the transmitting end as much as possible. The patent provides a multiport high-speed data synchronous transmission method, which can synchronously complete frame type judgment and link code word synchronization under the condition of not increasing overhead code words, has multiport data sending synchronization capability, greatly reduces the complexity of receiving end synchronous processing, and reduces the additional overhead in the link transmission process. The existing high-speed data transmission method mostly adopts a mainstream data frame format, and cannot perfectly fit with the system requirements of a digital transparent processor, so that the hardware structure design of the system has more redundancy, the universality of a hardware platform is lower, and the application range of the system is reduced.
Document 1: "design and implementation of inter-board high-speed data transmission interface" (shang sha, li Feng, radio engineering, vol 47, no. 11, 2017) provides an inter-board high-speed data transmission method based on aurora serial transmission protocol, which can meet the requirements of high capacity and high speed in the data transmission process. However, the aurora protocol has a large link overhead for a digital transparent processor system, and the protocol has good universality on an FPGA platform of XILINX company, but cannot be applied to an ASIC platform and the like. The aurora protocol does not distinguish the data frame types, and extra overhead codes are needed to judge the frame types, so the protocol efficiency in the digital transparent processor system is low.
Document 2: "design and realization of a kind of inter-board high-speed transmission system" (Liu Lige, li Tianbao, radio communication technology, 2011 volume 37, stage 4) gives the realization principle and concrete scheme of the high-speed parallel data transmission bus, the method adopts the parallel transmission line, and puts forward the strict requirement of equal-length wiring to the hardware design under the high transmission rate, and the hardware has many connecting lines, and is not easy to realize the miniaturization of the product. The method is suitable for point-to-point data transmission and cannot be applied to a multi-port data transmission system.
Document 3: the realization of a multichannel high-speed transmission link based on FPGA (Gu Jianchao, the university of Western-An electronic technology, 2014) provides a high-speed data transmission method based on a PCI Express bus structure, and the method focuses on considering the specific realization of a physical layer parallel-serial conversion module and does not analyze the problems of link layer data frame format, data frame type judgment, multi-port data synchronization and the like in detail.
Document 4: a system (CN 201520537432.6) for realizing inter-board communication based on SPI serial peripheral interface protocol provides a transmission system based on SPI protocol, the method realizes data transmission through a third party main control board, and the architecture is different from the application scene of data transmission in a digital transparent processor system.
The above 4 documents in the prior art provide transmission methods of high-speed data in different scenes, different hardware platforms and different transmission protocols, all of which adopt the existing main stream communication protocol and have no application requirements of data frame type judgment and multi-port synchronization. For example, document 1 discloses an aurora protocol for data transmission, but the protocol relies on the FPGA platform of XILINX corporation, and is not applicable to systems using other hardware platforms. The data transmission application scenarios of documents 2 and 4 are greatly different from the digital transparent processor system, and document 3 focuses on analyzing the physical layer transmission method without considering the processing requirements of the data frame of the link layer.
Disclosure of Invention
The technical problem solved by the invention is as follows: the method overcomes the defects of the prior art, can finish the data frame type judgment under the condition of not increasing extra expenses, has the multi-port synchronous sending capability, and can be suitable for the effective transmission load with any data bit width because the patch code is added in the data frame format designed by the method. In addition, the method is not dependent on a specific hardware platform, so that the method can be compatible with various system designs and has a wide application range.
The technical solution of the invention is as follows: a multi-port high-speed data synchronous transmission method comprises the following steps:
determining the data volume N and the data bit width B of an effective load in a data transmission link, and adjusting the byte length M of a load data patch;
step (2), determining a data transmission frame structure according to the data quantity of the effective load determined in the step (1);
step (3), determining the link overhead code word in the frame structure in the step (2);
step (4), calculating the byte length of each frame of data according to the data transmission frame structure and the link overhead code word;
step (5), calculating the period T of the multi-port synchronous control signal according to the data transmission rate S;
and (6) framing of the transmitted data is completed according to the data transmission frame structure in the step (2), and the frame data of the multiple ports are synchronously transmitted under the control of the synchronous signal.
Further, the link overhead code word comprises a frame header, a frame sequence number, a frame tail, a check code, a patch code and an idle code; wherein the frame sequence number is a transmission sequence number of the current frame; the check code is a check result of current frame data; the patch code is used for link transmission bit width matching; the frame head, the frame tail and the idle codes are all 4 bytes in length, and each frame of data comprises two idle codes.
Furthermore, the coding mode of the idle code is 1K code plus 3D codes.
Further, in the byte length of each frame of data, the link overhead code has 24 bytes, and each frame of data has L bytes, where L = N + M +24.
Further, the period T of the multi-port synchronization control signal is T =8L/S.
Further, the byte length M of the payload data patch is adjusted, so that the length of the patched payload data satisfies N + M = pk, where k =1,2,3.
Further, in the step (1), the data bit width of the payload is arbitrary, and when framing the payload into the link transmission frame structure, the length of the patch code is determined according to the bit width after the bit width conversion.
Further, the frame data of the multiple ports completes synchronous transmission under the control of the synchronization signal, specifically: the synchronous data transmission method comprises the steps of controlling the reading time of the sending buffer areas of a plurality of ports by using a synchronous signal, and simultaneously reading the sending buffer areas of the plurality of ports at the edge of the synchronous signal, namely the rising edge or the falling edge, so that the synchronous data transmission of the plurality of ports is completed.
Compared with the prior art, the invention has the advantages that:
(1) The invention adopts overhead codes with the length of 4 bytes, wherein 1 byte at the upper position is used for link code word synchronization, and 3 bytes at the lower position are used for frame type judgment, and the invention has two functions of link synchronization and frame type judgment;
(2) The invention adopts the synchronous control signal to finish the synchronous sending processing of the data of multiple ports, and the transmitted data frame structure is irrelevant to a hardware platform, thereby having stronger platform compatibility and application scene adaptability.
Drawings
FIG. 1 is a diagram illustrating a data transmission frame structure according to the present invention;
FIG. 2 is a 4-byte format of overhead codes (frame header, frame trailer, idle codes) designed by the present invention;
FIG. 3 is a schematic diagram of the data transmission framing and data reception de-framing processes in the present invention;
FIG. 4 is a flow chart of data frame transmission according to the present invention;
FIG. 5 is a diagram illustrating the relationship between multi-port synchronization control signals and ports according to the present invention;
FIG. 6 is a diagram illustrating a relationship between a synchronization control signal and a data frame structure according to the present invention.
Detailed Description
In order to better understand the technical solutions, the technical solutions of the present application are described in detail below with reference to the drawings and specific embodiments, and it should be understood that the specific features in the embodiments and examples of the present application are detailed descriptions of the technical solutions of the present application, and are not limitations of the technical solutions of the present application, and the technical features in the embodiments and examples of the present application may be combined with each other without conflict.
The following describes in further detail a multi-port high-speed data synchronous transmission method provided in the embodiments of the present application with reference to the drawings of the specification, and specific implementations may include (as shown in fig. 1 to fig. 6):
(1) Determining the data volume N and the data bit width B of a payload in a data transmission link, and then adjusting the byte length M of a payload data patch so that the length of the patched payload data meets N + M = pk, wherein k =1,2,3, p is the link transmission data bit width with the byte as a unit, and generally p =2,4,8;
(2) Defining a data transmission frame structure according to the data volume of the effective load determined in the step (1);
(3) Determining a link overhead code word in the frame structure in the step (2), wherein the link overhead code word comprises a frame head, a frame sequence number, a frame tail, a check code, a patch code and an idle code; wherein the frame sequence number is a transmission sequence number of the current frame; the check code is a check result of current frame data, and a check mode can be adopted according to actual requirements; the patch code is used for link transmission bit width matching and has no practical meaning; the frame head, the frame tail and the idle codes are all 4 bytes in length, each frame of data comprises two idle codes, and a uniform coding format is adopted, namely a mode of adding 1K code and 3D codes;
(4) Combining the step (2) and the step (3), calculating the byte length of each frame of data, wherein the link overhead code has 24 bytes in total, and each frame of data has L bytes in total, wherein L = N + M +24;
(5) Calculating a period T (ns) of the multi-port synchronous control signal according to a data transmission rate S (Gbps), wherein T =8L/S;
(6) Completing framing of the transmitted data according to the transmission frame structure in the step (2), and completing synchronous transmission of frame data of a plurality of ports under the control of a synchronous signal;
further, in the scheme provided in this embodiment of the present application, in step (1), since the patch code is appended to the end of the payload data, the data bit width of the payload may be arbitrary, and when framing the payload data into the link transmission frame structure, only bit width conversion needs to be performed, and the length of the patch code is determined according to the converted bit width.
Further, in the multi-port high-speed data synchronous transmission method, in step (2), the defined data transmission frame structure needs to adjust the byte length of the payload data accordingly according to the actually required data transmission rate and data transmission amount.
Preferably, in the multi-port high-speed data synchronous transmission method, in step (3), overhead codewords of the link, i.e., a frame header, a frame tail, and idle codes, adopt a mode of adding 3D codes to 1K code, and can judge the type of the data transmission frame while completing the synchronization of the link codewords, and theoretically, the 3D codes can support the judgment of frame data of 8 different types.
Optionally, in step (5), in order to implement synchronous transmission of multi-port data, a fixed relation exists between a cycle of a synchronization control signal and a data frame length and a data transmission rate, that is, T =8L/S, where L is the data frame length in bytes, and S is the data transmission rate in Gbps.
Further, in a possible implementation manner, in the multi-port high-speed data synchronous transmission method, in step (6), the synchronous control signal has a specific transmission relationship with the data frame structure, the synchronous control signals of the plurality of ports are consistent, and the plurality of ports synchronously perform the transmission processing of the data frame under the control of the synchronous control signal.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.
Claims (6)
1. A multi-port high-speed data synchronous transmission method is characterized by comprising the following steps:
determining the data volume N and the data bit width B of an effective load in a data transmission link, and adjusting the byte length M of a load data patch;
step (2), determining a data transmission frame structure according to the data quantity of the effective load determined in the step (1);
step (3), determining the link overhead code word in the frame structure in the step (2);
step (4), calculating the byte length of each frame of data according to the data transmission frame structure and the link overhead code word;
step (5), calculating the period T of the multi-port synchronous control signal according to the data transmission rate S;
step (6), framing of the transmitted data is completed according to the data transmission frame structure in the step (2), and the frame data of the multiple ports are synchronously transmitted under the control of the synchronous signals;
the link overhead code word comprises a frame head, a frame sequence number, a frame tail, a check code, a patch code and an idle code; wherein the frame sequence number is a transmission sequence number of the current frame; the check code is a check result of current frame data; the patch code is used for link transmission bit width matching; the frame head, the frame tail and the idle codes are all 4 bytes in length, and each frame of data comprises two idle codes;
the coding mode of the idle code is 1K code plus 3D codes.
2. The method for multi-port high-speed data synchronous transmission according to claim 1, characterized in that: in the byte length of each frame of data, the link overhead code has 24 bytes, and each frame of data has L bytes, where L = N + M +24.
3. The method for multi-port high-speed data synchronous transmission according to claim 1, characterized in that: the period T of the multi-port synchronous control signal is T =8L/S.
4. The method for multi-port high-speed data synchronous transmission according to claim 1, characterized in that: the byte length M of the payload data patch is adjusted, so that the length of the payload data after patching meets N + M = p · k, wherein k =1,2,3.
5. The method for multi-port high-speed data synchronous transmission according to claim 1, characterized in that: in the step (1), the data bit width of the payload is arbitrary, and when the payload is framed in a link transmission frame structure, the length of the patch code is determined according to the bit width after the bit width conversion.
6. The method for multi-port high-speed data synchronous transmission according to claim 1, characterized in that: the frame data of the multiple ports completes synchronous transmission under the control of the synchronous signal, and specifically comprises the following steps: the synchronous data transmission method comprises the steps of controlling the reading time of the sending buffer areas of a plurality of ports by using a synchronous signal, and simultaneously reading the sending buffer areas of the plurality of ports at the edge of the synchronous signal, namely the rising edge or the falling edge, so that the synchronous data transmission of the plurality of ports is completed.
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| CN1241361C (en) * | 2002-09-23 | 2006-02-08 | 华为技术有限公司 | Transparent transmission method of mutiple manufacturer SDH device management information |
| CN106576267B (en) * | 2015-08-11 | 2020-06-26 | 华为技术有限公司 | Method, device and system for transmitting digital forward data |
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| CN111884753A (en) * | 2017-12-29 | 2020-11-03 | 华为技术有限公司 | Data transmission method, communication equipment and storage medium |
| CN110944022A (en) * | 2019-12-31 | 2020-03-31 | 重庆源联信息科技有限公司 | Frame structure applied to Chirp modulation mode in Internet of things system |
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