CN112536535A

CN112536535A - Cutting method of silicon wafer of insulator and chip

Info

Publication number: CN112536535A
Application number: CN202011432144.6A
Authority: CN
Inventors: 李豪; 吴庆才
Original assignee: Suzhou Industrial Park Nano Industry Technology Research Institute Co ltd
Current assignee: Suzhou Industrial Park Nano Industry Technology Research Institute Co ltd
Priority date: 2020-12-09
Filing date: 2020-12-09
Publication date: 2021-03-23

Abstract

The application relates to a cutting method and a chip of an insulator silicon wafer, which comprises the following steps: s1, providing an insulator silicon wafer and laser, wherein the insulator silicon wafer is provided with a bottom silicon, an insulating layer and a top silicon which are sequentially arranged from bottom to top; s2, focusing the laser into the silicon-on-insulator wafer to form one or more self-crack modified layers; and S3, cutting the silicon insulator wafer along the self-cracking modified layer. According to the cutting method and the chip of the silicon-on-insulator wafer, laser is focused inside the silicon-on-insulator wafer in a laser invisible cutting mode, a modified layer is formed inside the silicon-on-insulator wafer, and finally the silicon-on-insulator wafer is divided into the chips through methods such as glue film expanding and the like. And moreover, the dry processing technology is adopted, a water treatment procedure is not needed, the chip does not need to be contacted with other parts of the chip, edge breakage, silicon slag and debris in the chip cutting process can be obviously inhibited, the performance of the chip is ensured, and the subsequent packaging is facilitated.

Description

Cutting method of silicon wafer of insulator and chip

Technical Field

The invention relates to a cutting method of an insulator silicon wafer and a chip, belonging to the field of semiconductor devices.

Background

After the integrated circuit formation process, the chip is "diced" and separated into individual dies for packaging or application in unpackaged form in large circuits. The two most commonly used techniques for dicing chips are scribing (scribing) and sawing (sawing). Scribing is performed by scribing the chip surface along a pre-formed scribe line (scriber line) using a diamond tip. The scribe lines extend along the spaces between the dies. These spaces are commonly referred to as "streets". When the diamond is scribed, a shallow scratch is formed on the surface of the chip along the scribe line. When pressure is applied, for example with a roller, the chip may separate along the scribe lines. The fracture of the chip follows the lattice structure of the chip. Scribing can be used for chips having a thickness of about 10 mils (thousandths of an inch) or less. For thicker chips, sawing is the preferred method of dicing.

The dicing of a Silicon-On-Insulator (SOI) wafer has been a difficult point in the whole process. At present, the existing cutting method mainly comprises cutter wheel cutting, and the principle of the method is that a blade directly acts on the surface of a chip, the chip is broken through the impact of diamond particles, and then powder is removed through a cutter edge. The chip cut by the method is easy to generate edge breakage and silicon slag, and has great influence on the performance of the chip and the subsequent manufacturing process. Meanwhile, when the cutter wheel is used for cutting, blade cooling water and cutting water are needed, and other parts of the chip are easily affected.

Disclosure of Invention

The invention aims to provide a method and a chip for cutting an insulator silicon wafer, which are used for solving the problems of edge breakage, silicon slag, water stain and the like generated when the traditional cutter wheel is used for cutting the insulator silicon wafer, ensuring that the cut chip is clean and free of damage, and being beneficial to reducing the width of a cutting path and improving the cutting efficiency.

In order to achieve the purpose, the invention provides the following technical scheme: a method for cutting an insulator silicon wafer comprises the following steps:

s1, providing an insulator silicon wafer and laser, wherein the insulator silicon wafer is provided with a bottom silicon, an insulating layer and a top silicon which are sequentially arranged from bottom to top;

s2, focusing the laser into the silicon-on-insulator wafer to form one or more self-crack modified layers;

and S3, cutting the silicon insulator wafer along the self-cracking modified layer.

Further, the laser light is infrared light.

Further, the wavelength of the laser is 1342 nm.

And further, cutting the insulator silicon wafer by adopting an extended glue film method.

Further, the method also comprises the step of arranging a glue film on the bottom silicon.

Further, in step S1, a plurality of functional layers are disposed on the top silicon, and the self-cracking modified layer is disposed below the upper surface of the top silicon.

Further, marks are arranged on the base silicon and are arranged between the adjacent functional layers.

Further, the laser forms a self-crack modified layer in the silicon-on-insulator wafer along the mark.

Further, in step S2, the laser light is focused through a lens into the bottom silicon and the insulating layer.

The application also provides a chip manufactured by the cutting method.

Compared with the prior art, the invention has the beneficial effects that: according to the cutting method and the chip of the silicon-on-insulator wafer, laser is focused inside the silicon-on-insulator wafer in a laser invisible cutting mode, the modified layer is formed inside the silicon-on-insulator wafer, and finally the silicon-on-insulator wafer is divided into the chips through methods such as glue film expanding and the like. And moreover, the dry processing technology is adopted, a water treatment procedure is not needed, the chip does not need to be contacted with other parts of the chip, edge breakage, silicon slag and debris in the chip cutting process can be obviously inhibited, the performance of the chip is ensured, and the subsequent packaging is facilitated.

The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical solutions of the present invention more clearly understood and to implement them in accordance with the contents of the description, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.

Drawings

FIG. 1 is a schematic structural diagram of an SOI wafer according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a self-cracking modified layer inside an SOI wafer according to an embodiment of the present invention;

fig. 3 and 4 are electron micrographs of a silicon-on-insulator wafer according to an embodiment of the present invention.

Detailed Description

The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.

It should be noted that: the terms "upper", "lower", "left", "right", "inner" and "outer" of the present invention are used for describing the present invention with reference to the drawings, and are not intended to be limiting terms.

Referring to fig. 1, the silicon-on-insulator wafer 10 of the present embodiment sequentially comprises a bottom silicon 1, an insulating layer 2 and a top silicon 3 from bottom to top, in the present embodiment, the thickness of the bottom silicon 1 is 392 μm, the thickness of the insulating layer 2 is 500nm, the thickness of the top silicon 3 is 10 μm, and the specific material is the conventional material and will not be described in detail.

In the present embodiment, the silicon on insulator wafer 10 is cut by the following steps:

referring to fig. 2, infrared light with a wavelength of 1342nm is focused into (inside) an insulator silicon wafer 10 by a lens 5, so that single crystal silicon inside the silicon wafer is modified to form a self-crack modified layer 6, the insulator silicon wafers 10 with different thicknesses need different cutting times, a plurality of modified layers are formed at different positions inside the insulator silicon wafer 10 by controlling the focusing depth of laser 4, so that the modified layers naturally crack under the action of the internal stress of the insulator silicon wafer 10, and finally the insulator silicon wafer 10 is divided into chips by a method of expanding a glue film. Specifically, a plurality of functional layers are arranged on the top silicon 3, and corresponding marks are correspondingly arranged on the bottom silicon 1 and between adjacent functional layers, so that the laser 4 is guided.

Referring to FIG. 3, in this embodiment, the bottom silicon 1 is cut at distances of 312 μm, 235 μm, 157 μm, 32 μm and 94 μm from the surface of the top silicon 3. When the bottom silicon 1 cracks, the top silicon 3 also cracks under the action of residual stress. And arranging a glue film on the bottom silicon 1, and cutting the insulator silicon wafer 10 by adopting an extended glue film method to obtain a chip as shown in fig. 4.

In summary, the following steps: according to the cutting method and the chip of the silicon-on-insulator wafer, laser is focused inside the silicon-on-insulator wafer in a laser invisible cutting mode, the modified layer is formed inside the silicon-on-insulator wafer, and finally the silicon-on-insulator wafer is divided into the chips through methods such as glue film expanding and the like. And moreover, the dry processing technology is adopted, a water treatment procedure is not needed, the chip does not need to be contacted with other parts of the chip, edge breakage, silicon slag and debris in the chip cutting process can be obviously inhibited, the performance of the chip is ensured, and the subsequent packaging is facilitated.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A method for cutting an insulator silicon wafer is characterized by comprising the following steps:

2. The method for cutting a silicon on insulator wafer according to claim 1, wherein the laser light is infrared light.

3. The method for cutting an insulator silicon wafer according to claim 2, wherein the wavelength of the laser is 1342 nm.

4. The method for cutting an insulator silicon wafer according to claim 1, wherein the insulator silicon wafer is cut by an extended glue film method.

5. The method for cutting an insulator silicon wafer according to claim 4, further comprising providing an adhesive film on the base silicon.

6. The method for cutting an soi wafer according to claim 1, wherein a plurality of functional layers are provided on the top silicon, and the self-crack modified layer is provided below an upper surface of the top silicon in step S1.

7. The silicon on insulator wafer dicing method according to claim 6, wherein a mark is provided on the base silicon, the mark being provided between adjacent functional layers.

8. The silicon-on-insulator wafer dicing method according to claim 6, wherein the laser forms a self-crack modified layer in the silicon-on-insulator wafer along the mark.

9. The method for cutting a silicon on insulator wafer according to claim 1, wherein the laser is focused into the bottom silicon and the insulating layer through a lens in step S2.

10. A chip produced by the dicing method according to any one of claims 1 to 9.