CN112534824B

CN112534824B - Method and apparatus for video encoding

Info

Publication number: CN112534824B
Application number: CN201980048568.1A
Authority: CN
Inventors: 王悦名; 郑萧桢
Original assignee: SZ DJI Technology Co Ltd
Current assignee: SZ DJI Technology Co Ltd
Priority date: 2019-12-31
Filing date: 2019-12-31
Publication date: 2022-09-23
Anticipated expiration: 2039-12-31
Also published as: CN112534824A; WO2021134654A1

Abstract

A method and apparatus for video encoding, comprising: encoding a first image and a first boundary image block in an image to be encoded by using a first processor, wherein the first boundary image block is a boundary image block of a second image in the image to be encoded, and the first image is adjacent to the second image; encoding the second image and a second boundary image block by using a second processor, wherein the second boundary image block is a boundary image block in the first image, and the first boundary image block is adjacent to the second boundary image block; filtering an adjacent boundary between the first image and the second image using the first image and the first boundary image block encoded by the first processor, and/or filtering an adjacent boundary between the first image and the second image using the second image and the second boundary image block encoded by the second processor.

Description

Method and apparatus for video encoding

Copyright declaration

The disclosure of this patent document contains material which is subject to copyright protection. The copyright is owned by the copyright owner. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the patent and trademark office official records and records.

Technical Field

The present application relates to the field of image processing, and more particularly, to a method and apparatus for video encoding.

Background

At present, in practical applications, as the demands for video resolution and frame rate are increasing, a single-core hardware encoder cannot meet the demands, and a multi-core hardware encoder can provide higher encoding performance, so as to meet the demands for higher resolution and frame rate. A multi-core hardware encoder typically divides an image or video into a plurality of tiles (tiles) or Slice Segments (SS) (which may be referred to simply as slices), with each core responsible for encoding one or more of the tiles or slices.

Since the image is divided into a plurality of cores for encoding, a more obvious boundary blocking effect occurs at the divided boundary of the image, thereby resulting in poor image display quality and reduced user experience of watching video.

Therefore, how to eliminate the boundary blocking effect caused by different cores encoding different images in the same video is a problem to be solved.

Disclosure of Invention

The embodiment of the application provides a video coding method and device, which can eliminate boundary blocking effect caused by coding different images in the same video by different cores, improve image display quality, and further improve video watching experience of a user.

In a first aspect, a method for video coding is provided, including: encoding a first image and a first boundary image block in an image to be encoded by using a first processor, wherein the first boundary image block is a boundary image block of a second image in the image to be encoded, and the first image is adjacent to the second image; encoding the second image and a second boundary image block by using a second processor, wherein the second boundary image block is a boundary image block in the first image, and the first boundary image block is adjacent to the second boundary image block; wherein the encoding information used by the first processor when encoding the first boundary image block is the same as the encoding information used by the second processor when encoding the first boundary image block, and the encoding information used by the second processor when encoding the second boundary image block is the same as the encoding information used by the first processor when encoding the second boundary image block; filtering an adjacent boundary between the first image and the second image using the first image and the first boundary image block encoded by the first processor, and/or filtering an adjacent boundary between the first image and the second image using the second image and the second boundary image block encoded by the second processor.

In a second aspect, an apparatus for video encoding is provided and includes a first processor and a second processor; the first processor is used for encoding a first image and a first boundary image block in an image to be encoded, wherein the first boundary image block is a boundary image block of a second image in the image to be encoded, and the first image is adjacent to the second image; the second processor is configured to encode the second image and a second boundary image block, where the second boundary image block is a boundary image block in the first image, and the first boundary image block is adjacent to the second boundary image block; wherein the encoding information used by the first processor when encoding the first boundary image block is the same as the encoding information used by the second processor when encoding the first boundary image block, and the encoding information used by the second processor when encoding the second boundary image block is the same as the encoding information used by the first processor when encoding the second boundary image block; the first processor is further configured to filter an adjacent boundary between the first image and the second image using the encoded first image and the encoded first boundary image block, and/or the second processor is further configured to filter an adjacent boundary between the first image and the second image using the encoded second image and the encoded second boundary image block.

In a third aspect, a video encoding apparatus is provided that includes a processor and a memory. The memory is used for storing a computer program, and the processor is used for calling and running the computer program stored in the memory, and executing the method in the first aspect or each implementation manner thereof.

In a fourth aspect, a chip is provided for implementing the method in the first aspect or its implementation manners.

Specifically, the chip includes: a processor configured to call and run the computer program from the memory, so that the device on which the chip is installed performs the method according to the first aspect or the implementation manner thereof.

In a fifth aspect, there is provided a computer readable storage medium for storing a computer program comprising instructions for performing the method of the first aspect or any possible implementation manner of the first aspect.

In a sixth aspect, a computer program product is provided, which comprises computer program instructions for causing a computer to perform the method of the first aspect or the implementation manners of the first aspect.

In the method for encoding video provided by the embodiment of the present application, when the first and second processors are used to encode the first and second images, the first and second processors are used to encode more first boundary image blocks, and the second processor is used to encode more second boundary image blocks, and the encoding information used by the first processor to encode the first boundary image blocks is the same as the encoding information used by the second processor to encode the first boundary image blocks in the second image, and the encoding information used by the second processor to encode the second boundary image blocks is the same as the encoding information used by the boundary image blocks in the first image. The adjacent boundary between the first image and the second image can be filtered through the encoded first image and the encoded first boundary image block, and/or the adjacent boundary between the first image and the second image can be filtered through the encoded second image and the encoded second boundary image block, so that the boundary blocking effect between the images caused by encoding of different processors can be eliminated, the image display quality is improved, and further, the viewing experience of a user can be improved.

Drawings

The drawings used in the embodiments will be briefly described below.

FIG. 1 is an architecture diagram of a solution applying an embodiment of the present application;

FIG. 2 is a schematic diagram of a video coding framework 2 according to an embodiment of the present application;

fig. 3 is a schematic flow chart of a video encoding method provided by an embodiment of the present application;

fig. 4a is a schematic diagram of a partition of a video to be encoded according to an embodiment of the present application;

fig. 4b is a schematic diagram of a partition of a video to be encoded according to another embodiment of the present application;

fig. 4c is a schematic diagram of a partition of video to be encoded according to yet another embodiment of the present application;

fig. 4d is a schematic diagram of a partition of a video to be encoded according to another embodiment of the present application;

fig. 4e is a schematic diagram of a partition of a video to be encoded according to another embodiment of the present application;

fig. 5a is a schematic diagram of a partition of a video to be encoded according to another embodiment of the present application;

fig. 5b is a schematic diagram of a partition of a video to be encoded provided by a further embodiment of the present application;

FIG. 6 is a schematic diagram of a partition of a video to be encoded provided by a further embodiment of the present application;

FIG. 7 is a schematic diagram of a partition of a video to be encoded provided by a further embodiment of the present application;

fig. 8 is a schematic diagram of a partition of a video to be encoded provided by a further embodiment of the present application;

fig. 9 is a schematic diagram of partitioning a video to be encoded according to another embodiment of the present application;

fig. 10 is a schematic structural diagram of a video encoding apparatus provided in an embodiment of the present application;

fig. 11 is a schematic structural diagram of a chip provided in an embodiment of the present application.

Detailed Description

The following describes technical solutions in the embodiments of the present application.

Unless otherwise defined, all technical and scientific terms used in the examples of this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to limit the scope of the present application.

Fig. 1 is an architecture diagram of a solution to which an embodiment of the present application is applied.

As shown in FIG. 1, the system 100 can receive the data 102 to be processed, process the data 102 to be processed, and generate processed data 108. For example, the system 100 may receive data to be encoded, encoding the data to be encoded to produce encoded data, or the system 100 may receive data to be decoded, decoding the data to be decoded to produce decoded data. In some embodiments, the components in system 100 may be implemented by one or more processors, which may be processors in a computing device or in a mobile device (e.g., a drone). The processor may be any kind of processor, which is not limited in this embodiment of the present invention. In some possible designs, the processor may include an encoder, a decoder, a codec, or the like. One or more memories may also be included in the system 100. The memory may be used to store instructions and data, such as computer-executable instructions to implement aspects of embodiments of the invention, pending data 102, processed data 108, and the like. The memory may be any kind of memory, which is not limited in this embodiment of the present invention.

The data to be encoded may include text, images, graphical objects, animation sequences, audio, video, or any other data that needs to be encoded. In some cases, the data to be encoded may include sensory data from sensors, which may be visual sensors (e.g., cameras, infrared sensors), microphones, near-field sensors (e.g., ultrasonic sensors, radar), position sensors, temperature sensors, touch sensors, and so forth. In some cases, the data to be encoded may include information from the user, e.g., biometric information, which may include facial features, fingerprint scans, retinal scans, voice recordings, DNA samples, etc.

Fig. 2 is a schematic diagram of a video coding framework 2 according to an embodiment of the present application. As shown in fig. 2, after receiving the video to be encoded, each frame of the video to be encoded is encoded in turn, starting from the first frame of the video to be encoded. Wherein, the current coding frame mainly passes through: prediction (Prediction), transformation (Transform), Quantization (Quantization), Entropy Coding (Entropy Coding), and the like, and finally outputting the code stream of the current Coding frame. Correspondingly, the decoding process generally decodes the received code stream according to the inverse process of the above process to recover the video frame information before decoding.

Specifically, as shown in fig. 2, the video coding framework 2 includes a coding control module 201 for performing decision control actions and parameter selection during the coding process. For example, as shown in fig. 2, the encoding control module 201 controls parameters used in transformation, quantization, inverse quantization, and inverse transformation, and controls the selection of intra-frame or inter-frame modes, and the parameter control of motion estimation and filtering, and the control parameters of the encoding control module 201 are also input to the entropy encoding module and encoded to form a part of the encoded code stream.

When the current coding frame is coded, the coding frame is divided 202, specifically, slice division is performed on the coding frame first, and then block division is performed. Optionally, in an example, the Coding frame is divided into a plurality of non-overlapping largest Coding Tree Units (CTUs), each CTU may be further iteratively divided into a series of smaller Coding Units (CUs) in a quadtree, binary Tree, or ternary Tree manner, respectively, and in some examples, a CU may further include a Prediction Unit (PU) and a Transform Unit (TU) associated therewith, where PU is a Prediction basic Unit and TU is a Transform and quantization basic Unit. In some examples, a PU and a TU are each divided into one or more blocks on a CU basis, where a PU includes multiple Prediction Blocks (PBs) and associated syntax elements. In some examples, the PU and TU may be the same or derived from the CU by different partitioning methods. In some examples, at least two of the CU, PU, and TU are the same, e.g., CU, PU, and TU are not distinguished, all predicted, quantized, and transformed in units of CUs. For convenience of description, the CTUs, CUs, or other formed data units are hereinafter referred to as encoded blocks.

It should be understood that in the embodiments of the present application, the data unit for video coding may be a frame, a slice, a coding tree unit, a coding block or a group of any of the above. The size of the data units may vary in different embodiments.

Specifically, as shown in fig. 2, after the encoded frame is divided into a plurality of encoded blocks, a prediction process is performed to remove redundant information in spatial domain and temporal domain of the current encoded frame. The current commonly used prediction methods include intra-frame prediction and inter-frame prediction. Intra-prediction uses only the reconstructed information in the current frame image to predict the current coding block, while inter-prediction uses information in other frame images (also called reference frames) that have been reconstructed before to predict the current coding block. Specifically, in the embodiment of the present application, the encoding control module 201 is configured to decide to select intra prediction or inter prediction.

When the intra-frame prediction mode is selected, the intra-frame prediction 203 includes obtaining reconstructed blocks of the neighboring blocks that have been coded around the current coding block as reference blocks, calculating a predicted value to generate a predicted block by using a prediction mode method based on the pixel values of the reference blocks, subtracting the corresponding pixel values of the current coding block and the predicted block to obtain a residual error of the current coding block, and transforming 204, quantizing 205 and entropy coding 210 the residual error of the current coding block to form a code stream of the current coding block. Furthermore, after all the coding blocks of the current coding frame are subjected to the coding process, a part of the coding code stream of the coding frame is formed. In addition, the control and reference data generated in intra prediction 203 is also entropy encoded 210, forming part of the encoded code stream.

In particular, the transform 204 is used to remove correlation of the residuals of the image blocks in order to improve coding efficiency. For the transformation of the residual data of the current coding block, two-dimensional Discrete Cosine Transform (DCT) transformation and two-dimensional Discrete Sine Transform (DST) transformation are usually adopted, for example, at the encoding end, the residual information of the coding block is multiplied by an N × M transformation matrix and its transpose matrix, respectively, and the Transform coefficient of the current coding block is obtained after multiplication.

After the transform coefficients are generated, quantization 205 is used to further improve the compression efficiency, the transform coefficients are quantized to obtain quantized coefficients, and then entropy Coding 210 is performed on the quantized coefficients to obtain the residual code stream of the current Coding block, wherein the entropy Coding method includes, but is not limited to, Content Adaptive Binary Arithmetic Coding (CABAC) entropy Coding. And finally, storing the bit stream obtained by entropy coding and the coded coding mode information or sending the bit stream and the coded coding mode information to a decoding end. At the encoding end, the quantized result is also dequantized 206 and the dequantized result is inverse transformed 207. After the inverse transformation 207, the reconstructed pixel is obtained using the inverse transformation result and the motion compensation result. The reconstructed pixels are then filtered (i.e., loop filtered) 211. After 211, the filtered reconstructed image (belonging to the reconstructed video frame) is output. Subsequently, the reconstructed image can be used as a reference frame image of other frame images for inter-frame prediction. In the embodiment of the present application, the reconstructed image may also be referred to as a reconstructed image or a reconstructed image.

Specifically, the encoded neighboring blocks in the intra prediction 203 process are: before the current coding block is coded, the residual error generated in the coding process of the adjacent block is transformed 204, quantized 205, dequantized 206 and inversely transformed 207, and then is added with the prediction block of the adjacent block to obtain the reconstructed block. Correspondingly, inverse quantization 206 and inverse transform 207 are inverse processes of quantization 206 and transform 204, and are used to recover residual data prior to quantization and transformation.

The intra prediction mode may include a Direct Current (DC) prediction mode, a flat (Planar) prediction mode, and different angle prediction modes (e.g., 33 angle prediction modes may be included).

As shown in fig. 2, when the inter prediction mode is selected, the inter prediction process includes Motion Estimation (ME) 208 and Motion Compensation (MC) 209. Specifically, Motion estimation 208 is performed according to a reference frame image in the reconstructed video frame, an image block most similar to the current coding block is searched in one or more reference frame images according to a certain matching criterion as a matching block, and a relative displacement between the matching block and the current coding block is a Motion Vector (MV) of the current coding block. The current encoding block is then motion compensated 209 based on the motion vector and the reference frame to obtain a prediction block for the current encoding block. And subtracting the original value of the pixel of the coding block from the corresponding pixel value of the prediction block to obtain the residual error of the coding block. The residual of the current coding block is transformed 204, quantized 205 and entropy coded 210 to form a part of the coded stream of the coded frame. In addition, the control and reference data generated in motion compensation 209 is also encoded by entropy coding 210, forming part of the encoded code stream.

As shown in fig. 2, the reconstructed video frame is a video frame obtained after being filtered 211. The reconstructed video frame includes one or more reconstructed images. The filtering 211 is used to reduce compression distortion such as blocking effect and ringing effect generated in the encoding process, the reconstructed video frame is used to provide a reference frame for inter-frame prediction in the encoding process, and in the decoding process, the reconstructed video frame is output as a final decoded video after post-processing.

In particular, the inter Prediction mode may include an Advanced Motion Vector Prediction (AMVP) mode, a Merge (Merge) mode, or a skip (skip) mode.

For the AMVP mode, Motion Vector Prediction (MVP) may be determined first, after obtaining MVP, a start point of Motion estimation may be determined according to MVP, Motion search may be performed near the start point, an optimal MV may be obtained after the search is completed, a position of a reference block in a reference image is determined by the MV, a residual block is obtained by subtracting a current block from the reference block, a Motion Vector Difference (MVD) is obtained by subtracting MVP from the MV, and an index of the MVD and the MVP is transmitted to a decoding end through a code stream.

For the Merge mode, the MVP may be determined first, and directly determined as the MV of the current block. In order to obtain the MVP, a candidate MVP list (merge candidate list) may be first constructed, where the candidate MVP list may include at least one candidate MVP, each candidate MVP may correspond to an index, after the encoding end selects an MVP from the candidate MVP list, the MVP index may be written into a code stream, and then the decoding end may find the MVP corresponding to the index from the candidate MVP list according to the index, so as to implement decoding of the image block.

It should be understood that the above process is just one specific implementation of the Merge mode. The Merge mode may also have other implementations.

For example, Skip mode is a special case of Merge mode. After obtaining the MV according to the Merge mode, if the encoding side determines that the current block and the reference block are substantially the same, it is not necessary to transmit residual data, only the index of the MVP needs to be transmitted, and further, a flag may be transmitted, which may indicate that the current block may be directly obtained from the reference block.

That is, the Merge mode is characterized by: MV ═ MVP (MVD ═ 0); and Skip mode has one more feature, namely: the reconstructed value rec is the predicted value pred (residual value resi is 0).

The Merge mode can be applied to the triangle prediction technology. In the triangle prediction technology, an image block to be encoded may be divided into two sub image blocks having a triangle shape, a motion vector may be determined for each sub image block from a motion information candidate list, a predictor block corresponding to each sub image block may be determined based on the motion vector of each sub image block, and a prediction block of a current image block may be constructed based on the predictor block corresponding to each sub image block, thereby implementing encoding of the current image block.

For the decoding end, the operation corresponding to the encoding end is performed. Firstly, residual error information is obtained by utilizing entropy decoding, inverse quantization and inverse transformation, and whether the current image block uses intra-frame prediction or inter-frame prediction is determined according to a decoded code stream. If the prediction is intra-frame prediction, the reconstructed image block in the current frame is utilized to construct prediction information according to an intra-frame prediction method; if the inter-frame prediction is carried out, motion information needs to be analyzed, and a reference block is determined in the reconstructed image by using the analyzed motion information to obtain prediction information; and then, superposing the prediction information and the residual information, and obtaining the reconstruction information through filtering operation.

In practical applications, as the demands for video resolution and frame rate are increasing, a single-core hardware encoder cannot meet the demands, and a multi-core hardware encoder can provide higher encoding performance, so that the demands for higher resolution and frame rate can be met. A multi-core hardware encoder will typically divide an image or video into multiple tiles and/or multiple slices, with each core being responsible for encoding one or more of the tiles or slices.

It should be understood that, in the embodiment of the present application, a plurality of tiles or slices obtained by dividing an image or a video may also be referred to as image blocks, and the present application is not limited in this respect.

Since the image is divided into a plurality of cores for encoding, a more obvious boundary may appear at the boundary where the image is divided, thereby resulting in a reduction in the viewing experience of the user.

The embodiment of the application provides a video coding method, which can eliminate the boundary caused by coding and further improve the watching experience of a user.

The method 300 for video encoding provided by the embodiment of the present application will be described in detail below with reference to fig. 3.

As shown in fig. 3, a method 300 for video encoding according to an embodiment of the present application is provided, the method 300 may include

steps

310 and 330.

And 310, encoding a first image and a first boundary image block in an image to be encoded by using a first processor, wherein the first boundary image block is a boundary image block of a second image in the image to be encoded, and the first image is adjacent to the second image.

In the embodiment of the present application, the first image and the second image are images of images to be encoded, and in a specific encoding process, the image to be encoded may be divided into at least two images, and then one of the images may be encoded by using the first processor.

The first image and the second image in the embodiment of the application may be images with the same size, that is, when the image to be encoded is divided, the image to be encoded may be divided vertically or horizontally from the center of the image to be encoded; the first image and the second image may also be images of different sizes, that is, when the image to be encoded is divided, the image to be encoded may not be divided vertically or horizontally from the center of the image to be encoded.

For example, as shown in fig. 4a, there is provided a schematic diagram of division of a frame image of a video to be encoded according to an embodiment of the present application. Two slice segments, respectively slice segment 1 and slice segment 2, can be obtained by dividing the video to be encoded, each slice segment being in the form of a slice. In encoding, slice segment 1 may be encoded using a first processor and slice segment 2 may be encoded using a second processor.

Fig. 4b is a schematic diagram of a partition of a frame of image in a video to be encoded according to another embodiment of the present application. Two tiles, tile 1 and tile 2, can be obtained by horizontally dividing the image to be encoded, each tile being rectangular.

Where each tile may include an integer number of CTUs, tile 1 may be encoded using a first processor and tile 2 may be encoded using a second processor when encoding. Similarly, the image to be encoded may be divided vertically.

It should be understood that the horizontal division in the embodiment of the present application may refer to division of an image to be encoded from the horizontal direction, and the vertical division may refer to division of an image to be encoded from the vertical direction.

In the embodiment of the present application, when dividing an image to be coded, some basic principles need to be followed, and at least one of the following two conditions is satisfied between each slice segment and a tile:

(1) all CTUs in a slice segment belong to the same tile;

(2) all CTUs in a tile belong to the same slice segment.

Fig. 4c is a schematic diagram of a division of a frame of image in a video to be encoded according to another embodiment of the present application. As shown in fig. 4c, an image of a certain frame in a video to be coded may be divided horizontally to obtain two tiles, which are tile 1 and tile 2, respectively, and then the two tiles are divided to obtain 4 slice segments, which are slice segment 1, slice segment 2, slice segment 3, and slice segment 4, respectively. It can be seen that all CTUs in the same slice segment belong to the same tile, e.g., all CTUs in slice segment 1 belong to tile 1, all CTUs in slice segment 2 belong to tile 1, all CTUs in slice segment 3 belong to tile 2, and all CTUs in slice segment 4 belong to tile 2, which satisfies the above conditions.

Fig. 4d is a schematic diagram of a division of an image of a frame in a video to be encoded according to another embodiment of the present application. As shown in fig. 4d, a certain frame of image in the video to be coded may be divided vertically to obtain two tiles, which are respectively tile 1 and tile 2, and then divided to obtain 4 slices, which are respectively slice 1 and slice 2, slice 3, and slice 4. It can be seen that all CTUs in the same stripe segment belong to the same tile, e.g., all CTUs in stripe segment 1 belong to tile 1, all CTUs in stripe segment 2 belong to tile 1, all CTUs in stripe segment 3 belong to tile 2, and all CTUs in stripe segment 4 also belong to tile 2, satisfying the above condition.

In the embodiment of the present application, when the tile is divided irregularly, it should be noted that the coding order of the CTUs in the divided slice segment may be continuous. For example, as shown in fig. 4e, when tile 2 is divided irregularly to obtain a stripe segment, the division may be performed based on the solid thicker black line in fig. 4e to obtain stripe segment 3 and stripe segment 4. Wherein, the strip segment 3 comprises CTUs with the coding sequence of 1 to 8; the CTUs with the coding order of 9 to 35 are included in the slice segment 4.

Encoding the second image and a second boundary image block by using a second processor, wherein the second boundary image block is a boundary image block in the first image, and the first boundary image block is adjacent to the second boundary image block; the first processor uses the same encoding information when encoding the first boundary image block as the second processor uses when encoding the first boundary image block, and the second processor uses the same encoding information when encoding the second boundary image block as the first processor uses when encoding the second boundary image block.

In the embodiment of the present application, the first boundary image block may be a boundary image block in the second image, and the second boundary image block may be a boundary image block in the first image. The first processor may refer to the predetermined image coding information when encoding the first boundary image, and the second processor may refer to the predetermined image coding information when encoding the second boundary image block.

It should be noted that, when the first boundary image block is encoded by the first processor, the preset image encoding information used may be the same as the encoding information used when the first boundary image block is encoded by the second processor; the image coding information used when encoding the second boundary image block using the second processor may be the same as the coding information used when encoding the second boundary image block using the first processor.

It should be understood that the first boundary image block is adjacent to the second boundary image block in the embodiment of the present application, that is, the boundary image block in the second image is adjacent to the boundary image block in the first image. In other words, when the image to be encoded is divided, if the image to be encoded is divided horizontally or vertically through the center of the image to be encoded, the image blocks adjacent to the horizontal center line or the vertical center line of the image to be encoded are the first boundary image block and the second boundary image block in the embodiment of the present application.

As shown in fig. 5a, the image to be encoded is divided horizontally to obtain a first image and a second image in the embodiment of the present application. Referring to fig. 5a, tile 1 and tile 2 in the figure are the first image and the second image, respectively, in the embodiment of the present application, i.e. 5a-1 and 5a-2 in the figure are the first image and the second image, respectively, in the embodiment of the present application. In the figure, 5a-3 is the first boundary image block in the embodiment of the present application, and 5a-4 is the second boundary image block in the embodiment of the present application. The first image 5a-1 in the figure is an image including an image block a displayed by a thick black solid line, and the second image 5a-2 in the figure is an image including an image block D displayed by a thick black solid line; the image blocks 5a-3 in the figure are image blocks adjacent to the division line comprising image block B and the image blocks 5a-4 in the figure are image blocks adjacent to the division line comprising image block C.

In the encoding process, the encoding information used by the first processor in encoding the first boundary image block 5a-3 may be the same as the encoding information used by the second processor in encoding the first boundary image block 5 a-3; the encoding information employed by the second processor in encoding the second boundary image block 5a-4 may be the same as the encoding information employed by the first processor in encoding the second boundary image block 5 a-4.

It should be understood that the first boundary image block 5a-3 in the embodiment of the present application includes a plurality of image blocks B, wherein for each image block B, the division into a plurality of small image blocks may be continued, and assuming that the division into one of the image blocks B results in a plurality of small image blocks, which are respectively B1, B2, B3 and B4, the encoding information of the four small image blocks may be different from each other. Similarly, for an image block D comprised in the second image 5a-2, the division into a plurality of small image blocks may also be continued, for example, an image block D corresponding to the above-mentioned image block B divided into a plurality of small image blocks may be divided into 4 small image blocks, D1, D2, D3 and D4 respectively, and the encoding information of these four small image blocks may be different from each other.

The values are illustrative, among others, the encoding information employed in encoding image block B1 with the first processor may be the same as the encoding information employed in encoding image block D1 with the second processor; the encoding information used when encoding tile B2 with the first processor may be the same as the encoding information used when encoding tile D2 with the second processor; the encoding information used when encoding tile B3 with the first processor may be the same as the encoding information used when encoding tile D3 with the second processor; the encoding information used when encoding image block B4 with the first processor may be the same as the encoding information used when encoding image block D4 with the second processor.

As shown in fig. 5b, the first image and the second image in the embodiment of the present application can also be obtained by performing irregular division on the image to be encoded, refer to fig. 5b, that is, 5b-1 and 5b-2 in the figure are the first image and the second image, respectively, in the embodiment of the present application. In the figure, 5b-3 is a first boundary image block in the embodiment of the present application, and 5b-4 is a second boundary image block in the embodiment of the present application. The first image 5b-1 in the figure is an image including the image block a displayed by a thick black solid line, and the second image 5b-2 in the figure is an image including the image block D displayed by a thick black solid line; the image block 5B-3 in the figure is an image block comprising image block B adjacent to the division line and the image block 5B-4 in the figure is an image block comprising image block C adjacent to the division line.

In the encoding process, the encoding information used by the first processor in encoding the first boundary image block 5b-3 may be the same as the encoding information used by the second processor in encoding the first boundary image block 5 b-3; the encoding information employed by the second processor in encoding the second boundary image block 5b-4 may be the same as the encoding information employed by the first processor in encoding the second boundary image block 5 b-4.

In some embodiments, tile A0, tile B0, tile C0, and tile D0 in FIG. 5B may also belong to a boundary tile. In other words, the first border image block 5B-3 may comprise image block B and image block B0 and the second border image block may comprise image block C and image block C0. Wherein the encoding information and the parameter information of the image block B0 may be the same as the encoding information and the parameter information of the image block D0 included in the second image 5B-2; the encoding information and parameter information of the image block C0 may be the same as the encoding information and parameter information of the image block a0 included in the second picture 5 b-2.

In the embodiment of the present application, the number of processors and the number of images obtained by dividing an image to be encoded may also be other values, for example, if the number of divided images includes 4 images, the number of processors may also be 4, and the 4 divided images are encoded respectively. This is not a particular limitation of the present application.

And filtering 330 adjacent boundaries between the first image and the second image using the first image and the first boundary tiles encoded by the first processor, and/or filtering adjacent boundaries between the first image and the second image using the second image and the second boundary tiles encoded by the second processor.

The filtering in the embodiment of the present application may include deblocking filtering, pixel Adaptive Offset (SAO), or Adaptive Loop Filtering (ALF). Wherein, the deblocking filtering is mainly used for eliminating the blocking effect between images caused by different processor coding; the SAO and ALF are mainly used to compensate for distortions of the original pixels and the reconstructed pixels due to encoding.

It should be understood that in the embodiment of the present application, when the adjacent boundary between the first image and the second image is filtered by the first image and the first boundary image block encoded by the first processor, the included filtering types may be different for different encoding standards.

It should also be understood that the first boundary image block and the first image that are multi-coded using the first processor in the embodiments of the present application may be used to eliminate blocking artifacts between images due to the first image and the second image being coded using different processors, and similarly, the second boundary image block and the second image that are multi-coded using the second processor may also be used to eliminate blocking artifacts between images due to the first image and the second image being coded using different processors.

Thus, after filtering an adjacent boundary between the first image and the second image with the first boundary image block and the second boundary image block, the multi-coded first boundary image block may be discarded with the first processor and the multi-coded second boundary image block may be discarded with the second processor. In other words, after the first processor and the second processor are used to obtain the processed reconstructed pixels, the first processor may discard the coding information of the first boundary image block, and the second processor may discard the coding information of the second boundary image block, so as to ensure the integrity of the image to be coded.

In the method for encoding video provided by the embodiment of the present application, when the first and second processors are used to encode the first and second images, the first and second processors are used to encode more first boundary image blocks, and the second processor is used to encode more second boundary image blocks, and encoding information used by the first processor when encoding the first boundary image blocks is the same as encoding information used by the second processor when encoding the second boundary image blocks. The adjacent boundary between the first image and the second image can be filtered through the encoded first image and the encoded first boundary image block, and/or the adjacent boundary between the first image and the second image can be filtered through the encoded second image and the encoded second boundary image block, so that the boundary blocking effect between the images caused by encoding of different processors can be eliminated, the image display quality is improved, and further, the viewing experience of a user can be improved.

It is noted above that the encoding information used by the first processor when encoding the first boundary image block is the same as the encoding information used by the second processor when encoding the first boundary image block, and the encoding information used by the second processor when encoding the second boundary image block is the same as the encoding information used by the first processor when encoding the second boundary image block. The encoded information may include a variety of information, which will be described in detail below.

Optionally, in some embodiments, the encoding information includes an encoding mode and an encoding parameter.

Optionally, in some embodiments, the encoding mode comprises one or more of an inter prediction mode, an intra prediction mode, or a lossless encoding mode.

The encoding information in the embodiment of the present application may include an encoding mode and an encoding parameter. Specifically, the encoding mode in the encoding information used when the first processor is used to encode the first boundary image block and the encoding mode used when the second processor is used to encode the first boundary image block may both be an inter prediction mode; or, both the encoding mode in the encoding information used when the first processor is used to encode the first boundary image block and the encoding mode used when the second processor is used to encode the first boundary image block may be intra-frame prediction modes; alternatively, the encoding mode in the encoding information used when the first boundary image block is encoded by the first processor and the encoding mode used when the first boundary image block is encoded by the second processor may both be a lossless encoding mode or the like.

Similarly, for the second boundary image block, the encoding mode in the encoding information adopted when the second boundary image block is encoded by the second processor and the encoding mode in the encoding information adopted when the second boundary image block is encoded by the first processor may both be an inter-frame prediction mode; or both the coding mode in the coding information adopted when the second boundary image block is coded by the second processor and the coding mode in the coding information adopted when the second boundary image block is coded by the first processor may be an intra-frame prediction mode; alternatively, the coding mode in the coding information employed when the second boundary image block is coded by the second processor and the coding mode in the coding information employed when the second boundary image block is coded by the first processor may both be a lossless coding mode or the like.

In other alternative implementations, the encoding mode in the encoding information used when the first processor is used to encode the first boundary image block and the encoding mode used when the second processor is used to encode the first boundary image block may be any two or three of an inter-prediction mode, an intra-prediction mode, or a lossless encoding mode.

The encoding mode in the encoding information used when the first processor encodes the first boundary image block and the encoding mode used when the first processor encodes the second boundary image block may be the same or different. Similarly, the encoding mode in the encoding information used when the first boundary image block is encoded by the second processor may be the same as or different from the encoding mode used when the second boundary image block is encoded by the second processor.

The encoding parameters may be determined according to boundary image blocks included in the first image and the second image, for example, the encoding mode and the encoding parameters of the boundary image block adjacent to the first image and the second image may be preset in the memory, the encoding mode and the encoding parameters used when the first processor encodes the first boundary image block may be obtained from the memory, and it is required to ensure that the encoding mode and the encoding parameters used when the first processor encodes the first boundary image block are the same as the encoding mode and the encoding parameters used when the second processor encodes the first boundary image block; the encoding parameters used by the second processor to encode the second boundary image block may also be obtained from the memory, and it is required to ensure that the encoding parameters used by the second processor to encode the second boundary image block may be the same as the encoding parameters used by the first processor to encode the second boundary image block.

The lossless coding mode in this embodiment may be a Pulse Code Modulation (PCM) mode, or may also be a transform quantization bypass (transform bypass) mode, which is not specifically limited in this application.

Optionally, in some embodiments, the encoding, with the first processor, a first image of the images to be encoded includes: encoding the second boundary image block by using first preset encoding information by using the first processor; the encoding the second boundary image block with the second processor includes: and encoding the second boundary image block by using the first preset encoding information by using the second processor.

Optionally, in some embodiments, the encoding, with the first processor, the first boundary image block includes: encoding the first boundary image block by using second preset encoding information by using the first processor; said encoding, with a second processor, the second image comprising: and encoding the first boundary image block by using the second preset encoding information by using the second processor.

In the embodiment of the present application, since the second boundary image block is a boundary image block in the first image, when the first processor is used to encode the first image, the first processor may use the first preset encoding information to encode the second boundary image block in the first image; similarly, when the second boundary image block is encoded by the second processor, the same first preset encoding information may be used to encode the second boundary image block, so that it may be ensured that when the two processors respectively encode the second boundary image block, the employed encoding information is the same, and the reconstructed pixels of the finally obtained second boundary image block are the same.

In the embodiment of the application, because the first boundary image block is a boundary image block in the second image, when the second processor is used for encoding the second image, the second processor can adopt the second preset encoding information to encode the boundary image block in the second image, including the first boundary image block; similarly, when the first processor is used to encode the first boundary image block, the second predetermined encoding information may be used to encode the first boundary image block, so as to ensure that the encoding information used by the two processors is the same when encoding the first boundary image block.

Optionally, in some embodiments, if the coding mode in the preset coding information includes an intra prediction mode, the coding parameters in the preset coding information include: the method comprises the steps of presetting a first preset coding mode, presetting information of a reference image block and presetting a transformation quantization parameter; if the coding mode in the preset coding information includes an inter-frame prediction mode, the coding parameters in the preset coding information include: a second preset encoding mode, information of a preset reference frame, a preset motion vector and a preset transformation quantization parameter; if the coding mode in the preset coding information includes a transform quantization bypass mode in a lossless coding mode, the coding parameters in the preset coding information include: the intra-frame prediction mode and the information of a preset reference image block, or the inter-frame prediction mode, the information of a preset reference frame and a preset motion vector; if the coding mode in the preset coding information includes a pulse code modulation mode in the lossless coding mode, the coding parameters in the preset coding information include: a pixel bit depth of the pulse code modulation pattern.

In this embodiment, the encoding parameters in the first preset encoding information may be determined by an encoding mode, for example, if the encoding mode includes an intra prediction mode, the encoding parameters in the first preset encoding information may include: and the first preset coding mode is used for presetting the information of the reference image block and the transformation quantization parameter. The first preset coding mode may be a vertical prediction mode (including but not limited to the mode 26 of 35 intra prediction modes defined in the HEVC standard) or a horizontal prediction mode (including but not limited to the mode 10 of 35 intra prediction modes defined in the HEVC standard), and the information of the prediction reference image block may be information of an upper image block or a left image block located on the current image block.

If the encoding mode is an inter-frame prediction mode, the encoding parameters in the second predetermined encoding information may include: the second preset coding mode, information of a preset reference frame, a preset motion vector and a preset transformation quantization parameter. The second predetermined encoding mode may be an AMVP mode, a merge mode, or a skip mode in the inter-frame prediction mode, and the information of the predetermined reference frame may be a forward frame or a backward frame of the current frame.

If the encoding mode includes a transform quantization bypass mode in the lossless encoding mode, the encoding parameters in the preset encoding information may include an intra prediction mode and an inter prediction mode. For specific other encoding parameters related to the intra-frame prediction mode or the inter-frame prediction mode, reference may be made to the parameters of the intra-frame prediction mode or the inter-frame prediction mode, which are not described herein again.

The transform quantization bypass mode in the embodiment of the present application may refer to: there is no transform quantization process in the encoding process. That is, the residual error obtained after the prediction of the current image block may not be subjected to transform quantization processing.

If the coding mode comprises a pulse code modulation mode, the coding parameter may comprise a pixel bit depth. The pulse code modulation mode in the embodiment of the present application may refer to encoding an original pixel of a current image block without performing prediction, transformation, and quantization processes.

The above indicates that the first image and the second image in the embodiment of the present application can be obtained by dividing the image to be encoded, and the encoding information of the boundary image block in the embodiment of the present application may be different for different dividing manners, which will be described in detail below.

Optionally, in some embodiments, if the first image and the second image are obtained by vertically dividing the image to be encoded, the first preset encoding mode adopted by a first boundary image block satisfies a first preset condition, and the first preset encoding mode adopted by a second boundary image block satisfies a second preset condition, where the first preset condition is that an intra-frame prediction reconstructed pixel adopted by the first boundary image block is obtained according to a left, lower-left, upper-left, or upper neighboring block of the first boundary image block or according to a Direct Current (DC) prediction mode, and the second preset condition is that an intra-frame prediction reconstructed pixel adopted by the second boundary image block is obtained according to an upper or upper-right neighboring block of the second boundary image block; or if the first image and the second image are obtained by horizontally dividing the image to be encoded, the first preset encoding mode adopted by the first boundary image block satisfies a third preset condition, the first preset encoding mode adopted by the second boundary image block satisfies a fourth preset condition, the third preset condition is that the intra-frame prediction reconstruction pixels adopted by the first boundary image block are obtained according to adjacent blocks above, above left, above right or on the left of the first boundary image block, or according to a direct current prediction mode or according to a flat (planar) prediction mode, and the fourth preset condition is that the intra-frame prediction reconstruction pixels adopted by the second boundary image block are obtained according to adjacent blocks on the left or below the left of the second boundary image block.

In the embodiment of the present application, as shown in fig. 6, a first image 6-1 and a second image 6-2 can be obtained by vertically dividing an image to be encoded, and when a first image 6-1 and a second image 6-2 are encoded by using different processors, the first image 6-1 and a first boundary image block 6-3 can be encoded by using the first processor, and the second image 6-2 and a second boundary image block 6-4 can be encoded by using the second processor. The encoding information used when the first processor is used to encode the image block B included in the first boundary image block 6-3 may be the same as the encoding information used when the second processor is used to encode the image block D included in the second image 6-2; the encoding information used when encoding the image block C included in the second boundary image block 6-4 by the second processor may be the same as the encoding information used when encoding the image block a included in the first image 6-1 by the first processor.

In the embodiment of the present application, the first image 6-1 is an image including the image block a displayed by a thick black solid line, and the second image 6-2 is an image including the image block D displayed by a thick black solid line.

Specifically, when the first image 6-1 and the first boundary image block 6-3 are encoded by the first processor, the encoding information used when the first boundary image block 6-3 is encoded may be the same as the encoding information of the image block D included in the second image 6-2 by the second processor. If the image to be encoded is vertically divided into the first image 6-1 and the second image 6-2, the first preset encoding mode included in the second preset encoding information used by the first boundary image block 6-3 may satisfy a first preset condition, where the first preset condition may be that the intra-prediction reconstructed pixels used by the first boundary image block 6-3 may be obtained according to different angle prediction modes (for example, the intra-prediction reconstructed pixels may be based on the left, lower left, upper left, or upper neighboring blocks of the first boundary image block, including the mode 2-26 of the 35 intra-prediction modes defined in the HEVC standard) or according to a direct current prediction mode (including the mode 1 of the 35 intra-prediction modes defined in the HEVC standard). The first predetermined coding modes included in the first predetermined coding information used by the second boundary tile 6-4 may satisfy a second predetermined condition that the intra-predicted reconstructed pixels used by the second boundary tile 6-4 may be predicted according to different angle prediction modes (which may be based on the upper or upper-right neighboring blocks of the first boundary tile, including the modes 26-34 of the 35 intra-prediction modes defined in the HEVC standard).

Based on this, when the first processor is encoding the first boundary image block 6-3 and the second processor is encoding the image block D included in the second image 6-2, the first processor may encode the first boundary image block 6-3 by using the first preset encoding mode included in the second preset encoding information, and the second processor may also encode the image block D included in the second image 6-2 by using the first preset encoding mode included in the second preset encoding information.

When the second processor encodes the second boundary image block 6-4 and the first processor encodes the image block a included in the first image 6-1, the second processor may encode the second boundary image block 6-4 using a first preset encoding mode included in the first preset encoding information, and the first processor may also encode the image block a included in the first image 6-1 using the first preset encoding mode included in the first preset encoding information.

It should be understood that, in this embodiment of the application, if the first image and the second image are obtained by vertically dividing the image to be encoded, and the first preset encoding information may also include an AMVP mode, a Merge mode, a skip mode, or a lossless encoding mode of an inter prediction mode, the first processor may use the first preset encoding information to encode the first boundary image block, and similarly, the second processor may also use the first preset encoding information to encode the first boundary image block included in the second image; the second preset encoding information may also include an AMVP mode, a Merge mode, a skip mode, or a lossless encoding mode of the inter prediction mode, and the second processor may use the second preset encoding information to encode the second boundary image block, and similarly, the first processor may also use the second preset encoding information to encode the second boundary image block included in the first image.

When the AMVP mode, the Merge mode, or the skip mode in the inter prediction mode is adopted, the reference image block may be a left image block or a right image block of the current image block.

It is understood that the first preset encoding information and the second preset encoding information in the embodiment of the present application may be different. For example, the first preset encoding information may include an AMVP mode of an inter prediction mode, and the second preset encoding information may include a lossless encoding mode; or the first preset encoding information may include a lossless encoding mode, and the second preset encoding information may include a Merge mode of an inter prediction mode.

In the embodiment of the present application, the image to be encoded may be divided in different manners, for example, as shown in fig. 7, a first image 7-1 and a second image 7-2 obtained by horizontally dividing the image to be encoded provided in the embodiment of the present application are provided, in the embodiment of the present application, the first image 7-1 is an image including the image block a displayed by a thick black solid line, and the second image 7-2 is an image including the image block D displayed by a thick black solid line.

In this division manner, the first preset coding mode included in the second preset coding information employed by the first boundary image block 7-3 may satisfy a third preset condition, and the third preset condition may be that the intra-prediction reconstructed pixels employed by the first boundary image block 7-3 may be obtained according to different angular prediction modes (for example, based on the above, upper-left, upper-right, or left neighboring blocks of the first boundary image block, including modes 10-34 in the 35 intra-prediction modes defined in the HEVC standard), or according to a direct current prediction mode (including mode 1 in the 35 intra-prediction modes defined in the HEVC standard), or according to a flat prediction mode (including mode 0 in the 35 intra-prediction modes defined in the HEVC standard). The first preset coding modes included in the first preset coding information adopted by the second boundary image block 7-4 may satisfy a fourth preset condition, where the fourth preset condition may be that the intra-prediction reconstructed pixels adopted by the second boundary image block 7-4 may be predicted according to different angle modes (which may be based on adjacent blocks on the left or lower left of the first boundary image block, including mode 2-mode 10 among 35 intra-prediction modes defined in the HEVC standard).

Based on this, when the first processor is used to encode the first boundary image block 7-3, the first boundary image block 7-3 may be encoded by using the first encoding mode included in the second preset encoding information, and when the second processor is used to encode the image block D included in the second image 7-2, the image block D may also be encoded by using the first encoding mode included in the second preset encoding information.

Similarly, when the second boundary image block 7-4 is encoded by the second processor, the second boundary image block 7-4 may be encoded by using the first encoding mode included in the second preset encoding information, and when the first processor encodes the first image 7-1 including the image block a, the first processor may also encode the image block a by using the first encoding mode included in the second preset encoding information.

It should also be understood that, in the embodiment of the present application, the image to be encoded may be vertically divided multiple times or horizontally divided multiple times to obtain multiple image blocks, for example, as shown in fig. 8, the image to be encoded may be vertically divided twice to obtain three image blocks, which are the first image 8-1, the second image 8-2 and the third image 8-3. In the embodiment of the present application, the first image 8-1 is an image including the image block a displayed by a thick black solid line, the second image 8-2 is an image including the image block D and the image block E displayed by a thick black solid line, and the third image 8-3 is an image including the image block H displayed by a thick black solid line.

The first image 8-1, the second image 8-2 and the third image 8-3 may be encoded by different processors, respectively, and when the three images are encoded by different processors, they may be encoded in a similar manner as described above with reference to fig. 6. For example, when the first image 8-1 is encoded by the first processor, one more column of image blocks may be encoded, the one more encoded column of image blocks may be referred to as a first boundary image block 8-4, and the encoding information used when the first boundary image block 8-4 is encoded by the first processor may be the same as the encoding information used when the second image 8-2 includes an image block D adjacent to the first image 8-1.

Similarly, since the second image 8-2 is adjacent to both the first image 8-1 and the third image 8-3, two more columns of image blocks, such as the image block C included in the second boundary image block 8-5 and the image block F included in the third boundary image block 8-6 in the figure, may be encoded when the second image 8-2 is encoded. The encoding information used when the second processor is used to encode the image block C included in the second boundary image block 8-5 may be the same as the encoding information used when the first processor is used to encode the image block a included in the first image 8-1; the encoding information used when encoding the image block F comprised by the third boundary image block 8-6 with the second processor may be the same as the encoding information used when encoding the image block H comprised by the third image 8-3 with the third processor.

For the third image 8-3, when encoding it, one more column of image blocks may be encoded, the one more column of image blocks may be referred to as a fourth boundary image block 8-7, and the encoding information used when encoding the fourth boundary image block 8-7 by the third processor may be the same as the encoding information used when encoding the image block E included in the second image 8-2 by the second processor.

It can be understood that, in the embodiment of the present application, if the image to be encoded is divided into a plurality of images through multiple horizontal divisions, the plurality of images may be encoded based on a method similar to the above method, and for brevity, no further description is given here.

It is described above that a plurality of images can be obtained by vertically dividing or horizontally dividing an image to be encoded a plurality of times, and a boundary image block of each image is combined, so that the obtained plurality of images and the boundary image block can be encoded by using different processors, and further, a boundary between the plurality of images can be filtered based on the plurality of images and the boundary image block. In some implementations, the image to be encoded may be a plurality of images obtained by dividing the image into a plurality of vertical and a plurality of horizontal partitions, in which manner, there may be some differences from the encoding manner described above, which will be described in detail below.

Optionally, in some embodiments, the images to be encoded further include a third image and a fourth image, and if the first image, the second image, the third image, and the fourth image are obtained by horizontally and vertically dividing the images to be encoded, the encoding mode in the preset encoding information includes one or more of a vertical prediction mode in an intra-frame prediction mode, a horizontal prediction mode in an intra-frame prediction mode, an inter-frame prediction mode, or a lossless encoding mode.

In the embodiment of the present application, if a first image, a second image, a third image, and a fourth image are obtained by vertically and horizontally dividing an image to be encoded, when the four images are encoded by using different processors, a column of image blocks or a row of image blocks may be encoded in combination with an image adjacent to the four images. And the encoding mode for a multi-encoded column of image blocks or a multi-encoded row of image blocks may be determined as a vertical prediction mode or a horizontal prediction mode based on the division manner.

In the embodiment of the present application, the encoding mode for a column of multi-encoded image blocks or a row of multi-encoded image blocks may also be an inter prediction mode or a lossless encoding mode; the coding mode of the image block located at the intersection of the first image, the second image, the third image and the fourth image may be an inter-frame prediction mode or a lossless coding mode, which is not specifically limited in this application.

Optionally, in some embodiments, the encoding, with the first processor, the first image and the first boundary image block in the image to be encoded includes: encoding, with the first processor, the first image and the first boundary image block based on the vertical prediction mode or one or more of the horizontal prediction mode, the inter prediction mode, the lossless encoding mode; and encoding, by the first processor, intersection point images included in the image blocks to be encoded based on the inter-frame prediction mode or the lossless encoding mode, where the intersection point images are images at intersection points of the first image, the second image, the third image, and the fourth image.

Optionally, in some embodiments, the encoding, with the second processor, the second image and the second boundary image block includes: encoding, with the second processor, the second image and the second boundary image block based on one or more of the vertical prediction mode, the horizontal prediction mode, the inter prediction mode, the lossless encoding mode; and encoding, by the second processor, intersection point images included in the image blocks to be encoded based on the inter-frame prediction mode or the lossless encoding mode, where the intersection point images are images at intersection points of the first image, the second image, the third image, and the fourth image.

As shown in fig. 9, a schematic diagram is provided for the embodiment of the present application by dividing an image to be encoded vertically and horizontally once. In the embodiment of the present application, the first image 9-1 is an image including the image block a, the image block C, and the image block 9-13, which is displayed by a thick black solid line, the second image 9-2 is an image including the image block F, the image block G, and the image block 9-13, which is displayed by a thick black solid line, the third image 9-3 is an image including the image block J, the image block K, and the image block 9-13, which is displayed by a thick black solid line, and the fourth image 9-4 is an image including the image block P, the image block N, and the image block 9-13, which is displayed by a thick black solid line.

In the embodiment of the present application, when the first image 9-1 is encoded, the first processor may encode a boundary image block included in a second image 9-2 adjacent to the first image 9-1 and a boundary image block included in a third image 9-3. In particular, the first image 9-1, the first boundary patch 9-5, and the third boundary patch 9-6 may be encoded using the first processor. The encoding information used when the image block B included in the first boundary image block 9-5 is encoded by the first processor may be the same as the encoding information used when the image block F included in the second image 9-2 is encoded by the second processor, and the encoding information used when the image block D included in the third boundary image block 9-6 is encoded by the first processor may be the same as the encoding information used when the image block J included in the third image 9-3 is encoded by the third processor.

The image blocks F comprised by the first boundary image block 9-5 and the second image 9-2 may be encoded based on preset first preset encoding information. Specifically, the first boundary image block 9-5 may be encoded by using the first preset encoding information when being encoded by the first processor, and the image block F included in the second image 9-2 may also be encoded by using the first preset encoding information when being encoded by the second processor. The third boundary image block 9-6 and the image block J included in the third image may be encoded based on preset third preset encoding information. Specifically, when the first processor is used to encode the third boundary image block 9-6, the third preset encoding information may be used to encode the third boundary image block, and when the third processor is used to encode the image block J included in the second image 9-3, the third preset encoding information may also be used to encode the third boundary image block.

In this embodiment, the first preset encoding information may include a vertical prediction mode, an inter-frame prediction mode, or a lossless encoding mode in an intra-frame prediction mode; the third preset encoding information may include a horizontal prediction mode, an inter prediction mode, or a lossless encoding mode among the intra prediction modes.

Similarly, when the second processor encodes the second image 9-2, it may also encode in combination an image block comprised by the first image 9-1 and an image block comprised by the fourth image 9-4 adjacent to the second image 9-2. In particular, the second image 9-2 and the second border image block 9-7, as well as the fourth border image block 9-8, may be encoded by the second processor. The encoding information used when the second processor is used to encode the image block E included in the second boundary image block 9-7 may be the same as the encoding information used when the first processor is used to encode the image block a included in the first image 9-1; the encoding information used when encoding the image block H comprised by the fourth boundary image block 9-8 with the second processor may be the same as the encoding information used when encoding the image block N comprised by the fourth image 9-4 with the fourth processor.

The second boundary image block 9-7 and the image block a included in the first image 9-1 may be encoded based on preset second preset encoding information. Specifically, the second boundary image block 9-7 may be encoded by using the second preset encoding information when encoded by using the second processor, and the image block a included in the first image 9-1 may also be encoded by using the second preset encoding information when encoded by using the first processor. For the image block N included in the fourth boundary image block 9-8 and the fourth image 9-4, the fourth boundary image block 9-8 may be encoded by using the fourth preset encoding information when the second processor is used to encode the fourth boundary image block 9-8, and the image block N included in the fourth image 9-4 may also be encoded by using the fourth preset encoding information.

In this embodiment, the second preset encoding information may include a vertical prediction mode, an inter-frame prediction mode, or a lossless encoding mode in the intra-frame prediction mode; the fourth preset encoding information may include a horizontal prediction mode, an inter prediction mode, or a lossless encoding mode among the intra prediction modes.

Similarly, when the third processor encodes the third image 9-3, it may also encode in combination the image blocks comprised by the first image 9-1 and the image blocks comprised by the fourth image 9-4 adjacent to the third image 9-3. In particular, the third image 9-2 and the fifth border patch 9-9, as well as the sixth border patch 9-10 can be encoded with the third processor. The encoding information used when the third processor encodes the image block I included in the fifth boundary image block 9-9 may be the same as the encoding information used when the first processor encodes the image block C included in the first image 9-1, for example, the fifth preset encoding information may be used for all the image blocks; the encoding information used when encoding the image block L included in the sixth boundary image block 9-10 by the third processor may be the same as the encoding information used when encoding the image block P included in the fourth image 9-4 by the fourth processor, for example, the sixth preset encoding information may be used.

In this embodiment of the application, the fifth preset encoding information may include a horizontal prediction mode, an inter prediction mode, or a lossless encoding mode in the intra prediction mode; the sixth preset encoding information may include a vertical prediction mode, an inter prediction mode, or a lossless encoding mode among the intra prediction modes.

Similarly, when the fourth processor encodes the fourth image 9-4, it may also encode in combination the image blocks comprised by the second image 9-2 and the image blocks comprised by the third image 9-3 adjacent to the fourth image 9-2. In particular, the fourth image 9-4 and the seventh border image block 9-11, as well as the eighth border image block 9-12 can be encoded with the fourth processor. The encoding information used when the fourth processor is used to encode the image block O included in the seventh boundary image block 9-11 may be the same as the encoding information used when the third processor is used to encode the image block K included in the third image 7-3, for example, the seventh preset encoding information may be used; the encoding information used for encoding the image block M included in the eighth boundary image block 9-12 by using the fourth processor may be the same as the encoding information used for encoding the image block G included in the second image 9-2 by using the second processor, for example, the eighth preset encoding information may be used.

In this embodiment of the application, the seventh preset encoding information may include a vertical prediction mode, an inter-frame prediction mode, or a lossless encoding mode in an intra-frame prediction mode; the eighth preset encoding information may include a horizontal prediction mode, an inter prediction mode, or a lossless encoding mode among the intra prediction modes.

In the embodiment of the present application, if an image to be encoded is subjected to one vertical division and one horizontal division to obtain four images, as shown in fig. 9, the four images are respectively a first image 9-1, a second image 9-2, a third image 9-3, and a fourth image 9-4. The first image 9-1, the first boundary patch 9-5 and the third boundary patch 9-6 may be encoded with a first processor. In the encoding process, the first image 9-1 may be encoded by using a plurality of encoding methods, for example, a horizontal prediction mode in an intra-frame prediction mode, a vertical prediction mode in an intra-frame prediction mode, or an inter-frame prediction mode or a lossless encoding mode; for the image block F included in the first boundary image block 9-5 and the second image, the first boundary image block 9-5 may be encoded by using the first preset encoding information by the first processor, and the image block F may also be encoded by using the first preset encoding information by the second processor, where the first preset encoding information may include a vertical prediction mode, an inter prediction mode, or a lossless coding mode in an intra prediction mode. For the third boundary image block 9-6 and the image block J included in the third image, the first processor may encode the third boundary image block 9-6 by using third preset encoding information, and the third processor may also encode the image block J by using the third preset encoding information, where the third preset encoding information may include a horizontal prediction mode, an inter prediction mode, or a lossless encoding mode in an intra prediction mode.

Similarly, the second image 9-2, the second border patch 9-7 and the fourth border patch 9-8 may be encoded with the second processor. In the encoding process, for the second image 9-2, a plurality of encoding manners may be adopted, for example, a horizontal prediction mode in an intra-frame prediction mode, a vertical prediction mode in an intra-frame prediction mode, or an inter-frame prediction mode or a lossless encoding mode; for the image block a included in the second boundary image block 9-7 and the first image 9-1, the second boundary image block 9-7 may be encoded by the second processor using second preset encoding information, and the image block a may also be encoded by the first processor using the second preset encoding information, where the second preset encoding information may include a vertical prediction mode, an inter prediction mode, or a lossless encoding mode in an intra prediction mode. For the image blocks N included in the fourth boundary image block 9-8 and the fourth image 9-4, the fourth boundary image block 9-8 may be encoded by the second processor using fourth preset encoding information, and the fourth processor may also encode the image block N using the fourth preset encoding information, where the fourth preset encoding information may include a horizontal prediction mode, an inter prediction mode, or a lossless coding mode in an intra prediction mode.

Similarly, the encoding modes of the third image, the fourth image and the boundary image block are similar to the above-mentioned encoding modes, and for brevity, the description thereof is omitted here.

Further, for image blocks located at the intersection positions of the first image 9-1, the second image 9-2, the third image 9-3, and the fourth image 9-4, an inter prediction mode or a lossless coding mode may be employed. As shown in fig. 9, the intersection point image in the embodiment of the present application may be 9-13 in fig. 9, and when the image block 9-13 is encoded, the image block may be encoded in an inter prediction mode or a lossless encoding mode.

Optionally, in some embodiments, the preset motion vector is a preset fixed motion vector; or the preset motion vector is used for searching in a preset searching area and/or based on a preset searching mode.

Optionally, in some embodiments, the target transform quantization Parameter includes a preset Quantization Parameter (QP) and a preset Transform Unit (TU) division manner.

In an implementation manner, the preset motion vector in the embodiment of the present application may be a preset fixed motion vector, and as shown in fig. 6, for the image blocks D included in the first boundary image block 6-3 and the second image 6-2, the MV in the first preset coding information used by the image blocks D may be the preset fixed motion vector. For example, assuming that the MV set includes a plurality of MVs, the MV in the first preset coding information may be an MV located at a first position in the MV set, or an MV pointing to a certain direction in the MV set, which is not specifically limited in this application.

Optionally, in some embodiments, the method further comprises: and if the coding information comprises a plurality of coding modes, selecting a coding mode of the first boundary image block or the second boundary image block based on a preset coding cost algorithm.

In the embodiment of the present application, as shown in fig. 6, the encoding information used when the first processor is used to encode the image block B included in the first boundary image block 6-3 is the same as the encoding information used when the second processor is used to encode the image block D included in the second image 6-2, where the encoding modes may be the same. That is, if the first predetermined encoding includes a vertical prediction mode, the encoding method of the image block D included in the second image 6-2 is the vertical prediction mode, and the encoding method when the first processor encodes the image block B included in the first boundary image block 6-3 may also adopt the vertical prediction mode.

In the embodiment of the present application, the encoding information used when the second processor is used to encode the image block C included in the second boundary image block 6-4 is the same as the encoding information used when the first processor is used to encode the image block a included in the first image 6-1, where the encoding modes may be the same. For example, if the second preset encoding mode is a vertical prediction mode, the encoding mode adopted by the second processor to encode the image block C included in the second boundary image block 6-4 may be the vertical prediction mode, and the encoding mode adopted by the first processor to encode the image block a included in the first image 6-1 may also be the vertical prediction mode; if the second predetermined encoding mode is the horizontal prediction mode, the encoding mode used when the second processor encodes the image block C included in the second boundary image block 6-4 may be the horizontal prediction mode, and the encoding mode used when the first processor encodes the image block a included in the first image 6-1 may also be the horizontal prediction mode.

For the second boundary image block 6-4, since the second preset encoding mode may be a vertical prediction mode or a horizontal prediction mode, in some embodiments, the encoding mode of the second boundary image block 6-4 may be determined based on a preset encoding cost algorithm, for example, rate distortion optimization. For example, if the vertical prediction mode is adopted, so that the loss cost of the second boundary image block 6-4 is relatively low, the vertical prediction mode may be adopted; if the loss cost of the second boundary image block 6-4 can be made small by using the horizontal prediction mode, the horizontal prediction mode can be used.

Optionally, in some embodiments, the first processor and the second processor belong to the same encoder or different encoders.

In the embodiment of the present application, the first processor and the second processor may belong to the same encoder or may belong to different encoders. In the case where the first processor and the second processor belong to the same encoder, the first processor and the second processor may be different processing cores in the encoder; in the case where the first processor and the second processor belong to different encoders, the first processor and the second processor may be different encoders in the same encoding apparatus.

The method embodiment of the present application is described in detail above with reference to fig. 1 to 9, and the apparatus embodiment of the present application is described below with reference to fig. 10 to 11, which correspond to the method embodiment, so that the method embodiment of the present application can be referred to in the non-detailed portions.

Fig. 10 provides an encoding apparatus 1000 for an embodiment of the present application, where the encoding apparatus 1000 may include a first processor 1010 and a second processor 1020.

The first processor 1010 is configured to: encoding a first image and a first boundary image block in an image to be encoded by using a first processor, wherein the first boundary image block is a boundary image block of a second image in the image to be encoded, and the first image is adjacent to the second image; the second processor 1020 encodes the second image and a second boundary image block, the second boundary image block being a boundary image block in the first image, the first boundary image block being adjacent to the second boundary image block; wherein, the encoding information used by the first processor 1010 when encoding the first boundary image block is the same as the encoding information used by the second processor 1020 when encoding the first boundary image block, and the encoding information used by the second processor 1020 when encoding the second boundary image block is the same as the encoding information used by the first processor 1010 when encoding the second boundary image block; the first processor 1010 is further configured to filter an adjacent boundary between the first image and the second image using the encoded first image and the encoded first boundary image block, and/or the second processor 1020 is configured to filter an adjacent boundary between the first image and the second image using the encoded second image and the encoded second boundary image block.

Optionally, in some embodiments, the first processor 1010 is further configured to: encoding the second boundary image block by using first preset encoding information by using the first processor; the second processor 1020 is further configured to: and encoding the second boundary image block by adopting the first preset encoding information.

Optionally, in some embodiments, the first processor 1010 is further configured to: encoding the first boundary image block by using second preset encoding information by using the first processor; the second processor 1020 is further configured to: and encoding the first boundary image block by adopting the second preset encoding information.

Optionally, in some embodiments, if the first image and the second image are obtained by vertically dividing the image to be encoded, the first preset encoding mode adopted by the first boundary image block satisfies a first preset condition, and the first preset encoding mode adopted by the second boundary image block satisfies a second preset condition, where the first preset condition is that the intra-frame prediction reconstructed pixels adopted by the first boundary image block are obtained according to a left, lower-left, upper-left, or upper neighboring block of the first boundary image block or according to a direct current prediction mode, and the second preset condition is that the intra-frame prediction reconstructed pixels adopted by the second boundary image block are obtained according to an upper or upper-right neighboring block of the second boundary image block; or if the first image and the second image are obtained by horizontally dividing the image to be encoded, the first preset encoding mode adopted by the first boundary image block satisfies a third preset condition, the first preset encoding mode adopted by the second boundary image block satisfies a fourth preset condition, the third preset condition is that the intra-frame prediction reconstruction pixels adopted by the first boundary image block are obtained according to adjacent blocks above, above left, above right or on the left of the first boundary image block or according to a direct current prediction mode or according to a flat prediction mode, and the fourth preset condition is that the intra-frame prediction reconstruction pixels adopted by the second boundary image block are obtained according to adjacent blocks on the left or below the left of the second boundary image block.

Optionally, in some embodiments, the first processor 1010 is further configured to: encoding the first image and the first boundary image block based on one or more of the vertical prediction mode or the horizontal prediction mode, the inter prediction mode, the lossless encoding mode; and encoding intersection point images included in the image blocks to be encoded based on the inter-frame prediction mode or the lossless encoding mode, wherein the intersection point images are images at intersection point positions of the first image, the second image, the third image and the fourth image.

Optionally, in some embodiments, the second processor 1020 is further configured to: encoding the second image and the second boundary image block based on one or more of the vertical prediction mode, the horizontal prediction mode, the inter-prediction mode, and the lossless encoding mode; and encoding intersection point images included in the image blocks to be encoded based on the inter-frame prediction mode or the lossless encoding mode, wherein the intersection point images are images at intersection point positions of the first image, the second image, the third image and the fourth image.

Optionally, in some embodiments, the target transform quantization parameter includes a preset quantization parameter QP and a preset transform unit TU partition manner.

Optionally, in some embodiments, the first processor 1010 or the second processor 1020 is further configured to: and if the coding information comprises a plurality of coding modes, selecting the coding mode of the first boundary image block or the second boundary image block based on a preset coding cost algorithm.

Optionally, in some embodiments, the first processor 1010 and the second processor 1020 belong to the same encoder or different encoders.

Optionally, the encoding apparatus 1000 may further include a memory 1030. The first processor 1010 and the second processor 1020 may call and run a computer program from the memory 1030 to implement the method in the embodiment of the present application.

The memory 1030 may be a separate device from the first processor 1010 and/or the second processor 1020, or may be integrated in the first processor 1010 and/or the second processor 1020.

Optionally, the encoding device may be, for example, an encoder and a terminal (including but not limited to a mobile phone, a camera, an unmanned aerial vehicle, etc.), and the encoding device may implement corresponding processes in each method of the embodiments of the present application, and for brevity, details are not described herein again.

Fig. 11 is a schematic structural diagram of a chip of the embodiment of the present application. The chip 1100 shown in fig. 11 includes a first processor 1110 and a second processor 1120, and the first processor 1110 and the second processor 1120 can call and run a computer program from a memory to implement the method in the embodiment of the present application.

Optionally, as shown in fig. 11, the chip 1100 may further include a memory 1130. The first processor 1110 and/or the second processor 1120 may call and run a computer program from the memory 1130 to implement the method in the embodiment of the present application.

The memory 1130 may be a separate device independent of the first processor 1110 and/or the second processor 1120, or may be integrated in the first processor 1110 and/or the second processor 1120.

Optionally, the chip 1100 may further include an input interface 1140. The first processor 1110 and/or the second processor 1120 can control the input interface 1140 to communicate with other devices or chips, and in particular, can obtain information or data transmitted by other devices or chips.

Optionally, the chip 1100 may further include an output interface 1150. The first processor 1110 and/or the second processor 1120 can control the output interface 1150 to communicate with other devices or chips, and particularly, can output information or data to other devices or chips.

It should be understood that the chips mentioned in the embodiments of the present application may also be referred to as a system-on-chip, a system-on-chip or a system-on-chip, etc.

It should be understood that the processor of the embodiments of the present application may be an integrated circuit image processing system having signal processing capabilities. In implementation, the steps of the above method embodiments may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The Processor may be a general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, or discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and completes the steps of the method in combination with hardware of the processor.

It will be appreciated that the memory in the embodiments of the present application can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. The non-volatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable PROM (EEPROM), or a flash Memory. Volatile Memory can be Random Access Memory (RAM), which acts as external cache Memory. By way of example but not limitation, many forms of RAM are available, such as Static random access memory (Static RAM, SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic random access memory (Synchronous DRAM, SDRAM), Double Data Rate Synchronous Dynamic random access memory (DDR SDRAM), Enhanced Synchronous SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

It should be understood that the above memories are exemplary but not limiting, for example, the memories in the embodiments of the present application may also be static random access memory (static RAM, SRAM), dynamic random access memory (dynamic RAM, DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Direct Rambus RAM (DR RAM), and the like. That is, the memory in the embodiments of the present application is intended to comprise, without being limited to, these and any other suitable types of memory.

The memory in embodiments of the present application may provide instructions and data to the processor. The portion of memory may also include non-volatile random access memory. For example, the memory may also store device type information. The processor may be configured to execute the instructions stored in the memory, and when the processor executes the instructions, the processor may perform the steps corresponding to the terminal device in the above method embodiment.

In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in a processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in a memory, and a processor executes instructions in the memory, in combination with hardware thereof, to perform the steps of the above-described method. To avoid repetition, it is not described in detail here.

It should also be understood that, in the embodiment of the present application, the pixel points in the image may be located in different rows and/or columns, where the length of a may correspond to the number of pixel points in the same row included in a, and the height of a may correspond to the number of pixel points in the same column included in a. In addition, the length and the height of a may also be referred to as the width and the depth of a, respectively, which is not limited in this application.

It should also be understood that, in this embodiment of the present application, the "boundary interval distribution with a" may refer to at least one pixel point that is spaced from the boundary of a, and may also be referred to as "not adjacent to the boundary of a" or "not located at the boundary of a", which is not limited in this embodiment of the present application, where a may be an image, a rectangular region, a sub-image, or the like.

It should also be understood that the foregoing descriptions of the embodiments of the present application focus on highlighting differences between the various embodiments, and that the same or similar elements that are not mentioned may be referred to one another and, for brevity, are not repeated herein.

The embodiment of the application also provides a computer readable storage medium for storing the computer program.

Optionally, the computer-readable storage medium may be applied to the encoding apparatus in the embodiment of the present application, and the computer program enables the computer to execute the corresponding process implemented by the encoding apparatus in each method in the embodiment of the present application, which is not described herein again for brevity.

Embodiments of the present application also provide a computer program product comprising computer program instructions.

Optionally, the computer program product may be applied to the encoding apparatus in the embodiment of the present application, and the computer program instructions enable the computer to execute the corresponding processes implemented by the encoding apparatus in the methods in the embodiment of the present application, which are not described herein again for brevity.

The embodiment of the application also provides a computer program.

Optionally, the computer program may be applied to the encoding apparatus in the embodiment of the present application, and when the computer program runs on a computer, the computer executes the corresponding process implemented by the encoding apparatus in each method in the embodiment of the present application, and for brevity, details are not described here again.

It should be understood that, in the embodiment of the present application, the term "and/or" is only one kind of association relation describing an associated object, and means that three kinds of relations may exist. For example, a and/or B, may represent: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter associated objects are in an "or" relationship.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described in a functional general in the foregoing description for the purpose of illustrating clearly the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the systems, apparatuses and units described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus, and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one type of logical functional division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may also be an electrical, mechanical or other form of connection.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, that is, may be located in one place, or may also be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiments of the present application.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented as a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially or partially contributed by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

While the invention has been described with reference to specific embodiments, the scope of the invention is not limited thereto, and those skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the invention. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method of video encoding, comprising:

encoding a first image and a first boundary image block in an image to be encoded by using a first processor, wherein the first boundary image block is a boundary image block of a second image in the image to be encoded, and the first image is adjacent to the second image;

encoding the second image and a second boundary image block by using a second processor, wherein the second boundary image block is a boundary image block in the first image, and the first boundary image block is adjacent to the second boundary image block; wherein the encoding information used by the first processor when encoding the first boundary image block is the same as the encoding information used by the second processor when encoding the first boundary image block, and the encoding information used by the second processor when encoding the second boundary image block is the same as the encoding information used by the first processor when encoding the second boundary image block;

filtering an adjacent boundary between the first image and the second image using the first image and the first boundary image block encoded by the first processor, and/or filtering an adjacent boundary between the first image and the second image using the second image and the second boundary image block encoded by the second processor.

2. The method of claim 1, wherein the coding information comprises coding modes and coding parameters.

3. The method of claim 2, wherein the coding mode comprises one or more of an inter-prediction mode, an intra-prediction mode, or a lossless coding mode.

4. The method of claim 1, wherein encoding, with a first processor, a first image of the images to be encoded comprises:

encoding the second boundary image block by using first preset encoding information by using the first processor;

the encoding the second boundary image block with the second processor includes:

and encoding the second boundary image block by using the first preset encoding information by using the second processor.

5. The method of claim 1, wherein encoding the first boundary image block using the first processor comprises:

encoding the first boundary image block by using second preset encoding information by using the first processor;

said encoding, with a second processor, the second image comprising:

and encoding the first boundary image block by using the second preset encoding information by using the second processor.

6. The method of claim 5,

if the coding mode in the preset coding information includes an intra-frame prediction mode, the coding parameters in the preset coding information include: the method comprises the steps of presetting a first preset coding mode, presetting information of a reference image block and presetting a transformation quantization parameter;

if the coding mode in the preset coding information includes an inter-frame prediction mode, the coding parameters in the preset coding information include: a second preset encoding mode, information of a preset reference frame, a preset motion vector and a preset transformation quantization parameter;

if the coding mode in the preset coding information includes a transform quantization bypass mode in a lossless coding mode, the coding parameters in the preset coding information include: the intra-frame prediction mode and the information of a preset reference image block, or the inter-frame prediction mode, the information of a preset reference frame and a preset motion vector;

if the coding mode in the preset coding information includes a pulse code modulation mode in the lossless coding mode, the coding parameters in the preset coding information include: a pixel bit depth of the pulse code modulation pattern.

7. The method according to claim 6, wherein if the first image and the second image are obtained by vertically dividing the image to be encoded, the first predetermined encoding mode adopted by the first boundary image block satisfies a first predetermined condition, the first predetermined encoding mode adopted by the second boundary image block satisfies a second predetermined condition, the first predetermined condition is that intra-frame prediction reconstructed pixels adopted by the first boundary image block are obtained from left, lower left, upper left, or upper neighboring blocks of the first boundary image block or from a direct current prediction mode, and the second predetermined condition is that intra-frame prediction reconstructed pixels adopted by the second boundary image block are obtained from upper or upper right neighboring blocks of the second boundary image block; or

If the first image and the second image are obtained by horizontally dividing the image to be encoded, the first preset encoding mode adopted by the first boundary image block meets a third preset condition, the first preset encoding mode adopted by the second boundary image block meets a fourth preset condition, the third preset condition is that the intra-frame prediction reconstruction pixels adopted by the first boundary image block are obtained according to adjacent blocks above, above left, above right or on the left of the first boundary image block or according to a direct current prediction mode or according to a flat prediction mode, and the fourth preset condition is that the intra-frame prediction reconstruction pixels adopted by the second boundary image block are obtained according to adjacent blocks on the left or below the left of the second boundary image block.

8. The method according to claim 4, characterized in that the images to be encoded further comprise a third image and a fourth image,

if the first image, the second image, the third image, and the fourth image are obtained by horizontally and vertically dividing the image to be encoded, the encoding mode in the preset encoding information includes one or more of a vertical prediction mode in an intra-frame prediction mode, a horizontal prediction mode in an intra-frame prediction mode, an inter-frame prediction mode, or a lossless encoding mode.

9. The method of claim 8, wherein encoding, with the first processor, the first image and the first boundary image block in the image to be encoded comprises:

encoding, with the first processor, the first image and the first boundary image block based on the vertical prediction mode or one or more of the horizontal prediction mode, the inter prediction mode, the lossless encoding mode;

encoding, by the first processor, an intersection point image included in the image to be encoded based on the inter prediction mode or the lossless encoding mode, the intersection point image being an image of an intersection point position of the first image, the second image, the third image, and the fourth image.

10. The method of claim 8, wherein encoding the second image and the second boundary image block using the second processor comprises:

encoding, with the second processor, the second image and the second boundary image block based on one or more of the vertical prediction mode, the horizontal prediction mode, the inter prediction mode, the lossless encoding mode;

encoding, by the second processor, an intersection point image included in the image to be encoded based on the inter prediction mode or the lossless encoding mode, the intersection point image being an image of an intersection point position of the first image, the second image, the third image, and the fourth image.

11. The method according to claim 6 or 7, wherein the preset motion vector is a preset fixed motion vector; or

The preset motion vector is used for searching in a preset searching area and/or based on a preset searching mode.

12. The method according to claim 6 or 7, wherein the predetermined transform quantization parameter comprises a predetermined quantization parameter QP and a predetermined transform unit TU partition.

13. The method according to any one of claims 1 to 10, further comprising:

and if the coding information comprises a plurality of coding modes, selecting a coding mode of the first boundary image block or the second boundary image block based on a preset coding cost algorithm.

14. The method of any of claims 1 to 10, wherein the first processor and the second processor belong to the same encoder or different encoders.

15. An apparatus for video encoding comprising a first processor and a second processor;

the first processor is used for encoding a first image and a first boundary image block in an image to be encoded, wherein the first boundary image block is a boundary image block of a second image in the image to be encoded, and the first image is adjacent to the second image;

the second processor is configured to encode the second image and a second boundary image block, where the second boundary image block is a boundary image block in the first image, and the first boundary image block is adjacent to the second boundary image block; wherein the encoding information used by the first processor when encoding the first boundary image block is the same as the encoding information used by the second processor when encoding the first boundary image block, and the encoding information used by the second processor when encoding the second boundary image block is the same as the encoding information used by the first processor when encoding the second boundary image block;

the first processor is further configured to filter an adjacent boundary between the first image and the second image using the encoded first image and the first boundary image block, and/or,

the second processor is further configured to filter an adjacent boundary between the first image and the second image using the encoded second image and the second boundary image block.

16. The apparatus of claim 15, wherein the coding information comprises a coding mode and a coding parameter.

17. The apparatus of claim 16, wherein the coding modes comprise one or more of inter-prediction modes, intra-prediction modes, or lossless coding modes.

18. The apparatus of claim 15, wherein the first processor is further configured to: encoding the second boundary image block by adopting first preset encoding information;

the second processor is further configured to: and encoding the second boundary image block by adopting the first preset encoding information.

19. The apparatus of claim 15, wherein the first processor is further configured to: encoding the first boundary image block by adopting second preset encoding information;

the second processor is further configured to: and encoding the first boundary image block by adopting the second preset encoding information.

20. The apparatus of claim 18,

21. The apparatus according to claim 20, wherein if the first image and the second image are obtained by vertically dividing the image to be encoded, the first predetermined encoding mode adopted by the first boundary image block satisfies a first predetermined condition, the first predetermined encoding mode adopted by the second boundary image block satisfies a second predetermined condition, the first predetermined condition is that intra-prediction reconstructed pixels adopted by the first boundary image block are obtained from left, lower left, upper left, or upper neighboring blocks of the first boundary image block or from a dc prediction mode, and the second predetermined condition is that intra-prediction reconstructed pixels adopted by the second boundary image block are obtained from upper or upper right neighboring blocks of the second boundary image block; or

22. The apparatus of claim 18, wherein the image to be encoded further comprises a third image and a fourth image,

23. The apparatus of claim 22, wherein the first processor is further configured to:

encoding the first image and the first boundary image block based on one or more of the vertical prediction mode or the horizontal prediction mode, the inter prediction mode, the lossless encoding mode;

and encoding intersection point images included in the images to be encoded based on the inter-frame prediction mode or the lossless encoding mode, wherein the intersection point images are images at intersection point positions of the first image, the second image, the third image and the fourth image.

24. The apparatus of claim 22, wherein the second processor is further configured to:

encoding the second image and the second boundary image block based on one or more of the vertical prediction mode, the horizontal prediction mode, the inter-prediction mode, and the lossless encoding mode;

25. The apparatus according to claim 20 or 21, wherein the preset motion vector is a preset fixed motion vector; or

26. The apparatus of claim 20 or 21, wherein the predetermined transform quantization parameter comprises a predetermined quantization parameter QP and a predetermined transform unit TU partition.

27. The apparatus of any of claims 15 to 24, wherein the first processor or the second processor is further configured to:

28. The apparatus of any of claims 15 to 24, wherein the first processor and the second processor belong to the same encoder or different encoders.

29. A computer-readable storage medium comprising program instructions which, when executed by a computer, cause the computer to perform the method of any one of claims 1 to 14.