CN112527585A - Back plate applied to communication equipment - Google Patents
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- CN112527585A CN112527585A CN202011580860.9A CN202011580860A CN112527585A CN 112527585 A CN112527585 A CN 112527585A CN 202011580860 A CN202011580860 A CN 202011580860A CN 112527585 A CN112527585 A CN 112527585A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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Abstract
The embodiment of the application provides a backboard applied to communication equipment, which is used for solving the problem of low test efficiency of a hard disk in the related technology. In the embodiment of the application, the signals of the slots can be analyzed and disassembled, so that the same slot can accommodate different types of hard disks simultaneously, and therefore the testing for different types of hard disks can be completed based on the same slot, and the testing efficiency is improved.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a backplane for a communications device.
Background
In the related art, an external device needs to be accessed for testing. For example, when the same socket supports two types of hard disks, the first type of hard disk is tested first, and then the second type of hard disk is tested.
The testing method has low efficiency, so how to improve the testing efficiency needs to be solved.
Disclosure of Invention
The application aims to provide a backboard applied to communication equipment, which is used for solving the problem of low efficiency of interface test based on a hard disk slot in the related art.
The embodiment of the application provides a backboard applied to communication equipment, wherein a source slot on the communication equipment supports different types of hard disks, the backboard comprises a conversion part and a plurality of hard disk connectors, and each hard disk connector supports one of the different types of hard disks;
one end of the conversion component is connected with the source slot, and the other end of the conversion component is connected with each hard disk connector and is used for separating signals of different types of hard disk connectors from the source slot.
In some embodiments, the conversion component comprises a first backplane component and a second backplane component, wherein:
the first backboard component is connected with the source slot and used for converting signals of the source slot into high-speed signal connector signals;
and the second back board component is used for separating signals of different hard disk connectors from the signals of the high-speed signal connector.
In some embodiments, the first backplane component comprises a hard disk male connector, a first backplane, and a high-speed signal connector;
the hard disk male connector is connected with the source slot;
one end of the first back plate is connected with the hard disk male connector, the other end of the first back plate is connected with the high-speed signal connector, and the first back plate is used for converting a signal of the hard disk male connector into a signal of the high-speed signal connector.
In some embodiments, the signals of the hard disk male connector include a first hard disk stray signal, a first power signal, a first PCIE differential signal, and a first designation signal, where the first designation signal is a differential signal of a SATA signal or a differential signal of a SAS signal;
the first backplane is specifically configured to connect the first hard disk stray signal to a first type of stray pin of the high-speed signal connector corresponding to the first hard disk stray signal, connect the first power signal to a first type of power pin of the high-speed signal connector corresponding to the first power signal, connect the first PCIE differential signal to a first type of PCIE pin of the high-speed signal connector corresponding to the first PCIE (peripheral component interconnect express) differential signal, and connect the first designation signal to a first type of designation pin of the high-speed signal connector corresponding to the first designation signal.
In some embodiments, the first type of stray pins comprises: an A8 pin corresponding to a SSD (Solid State Disk or Solid State Drive) reset signal, an a9 pin corresponding to an SSD hard Disk control signal, an a10 pin corresponding to an SSD detection signal, an a23 pin corresponding to an SSD hard Disk type signal;
the first type of power pin comprises: an a17 pin, an a18 pin, an a20 pin, and an a21 pin corresponding to the first power supply, an a30 pin, an a32 pin, an a33 pin, an a35 pin, and an a36 pin corresponding to the second power supply; wherein the first power supply value is lower than the second power supply value;
the first class of PCIE pins comprises: a pin B5, a pin B6, a pin B8, a pin B9, a pin B17, a pin B18, a pin B20, a pin B21, a pin B23, a pin B24, a pin B26, a pin B27, a pin B29, a pin B30, a pin B32 and a pin B33;
the first type designation pin: pin A2, pin A3, pin A5, pin A6.
In some embodiments, the plurality of hard disk connectors includes an NVME hard disk connector;
the high-speed signal connector comprises a second hard disk stray signal, a second hard disk power signal and a second PCIE differential signal, wherein the second hard disk stray signal is used for an NVME (Non-Volatile Memory host controller interface specification) hard disk;
the second backplane component includes a second backplane, and is specifically configured to connect the second hard disk stray signal to a second type of stray pin of the NVME hard disk connector corresponding to the second hard disk stray signal, connect the second power signal to a second type of power pin of the NVME hard disk connector corresponding to the second power signal, and connect the second PCIE differential signal to a second type of PCIE pin of the NVME hard disk connector corresponding to the second PCIE differential signal.
In some embodiments, the second type of stray pins comprises: an E5 pin corresponding to an SSD reset signal, a P3 pin corresponding to an SSD hard disk control signal, a P4 pin corresponding to an SSD detection signal, and a P10 pin corresponding to an SSD hard disk type signal;
the second type of power pin comprises: an E4 pin, a P4 pin, a P11 pin, and an E25 pin corresponding to a third power supply; a P14 pin and a P15 pin corresponding to a fourth power supply; wherein the third power supply value is less than the fourth power supply value;
the second type of PCIE pin includes: the pin comprises an E10 pin, an E11 pin, an E13 pin, an E14 pin, an S17 pin, an S18 pin, an S20 pin, an S21 pin, an S23 pin, an S24 pin, an S26 pin, an S27 pin, an E17 pin, an E18 pin, an E20 pin and an E21 pin.
In some embodiments, the plurality of hard disk connectors includes a designated hard disk connector of a designated hard disk, the designated hard disk supporting SATA signals or SAS signals;
the high-speed signal connector comprises a third hard disk power supply signal and a second designated signal for the designated hard disk, the second designated signal being a differential signal of a Serial Advanced Technology Attachment (SATA) signal or a differential signal of a Serial Attached Small Computer System Interface (SAS) signal;
the second backplane is specifically configured to connect the third power signal to a third type power pin of the designated hard disk connector corresponding to the third power signal, and connect the second designated signal to a second type designated pin of the designated hard disk connector corresponding to the second designated signal.
In some embodiments, the third class of power supply pins comprises: a P10 pin corresponding to the third power supply, a P7 pin, a P8 pin, and a P9 pin corresponding to the fifth power supply, a P13 pin, a P14 pin, and a P15 pin corresponding to the fourth power supply; the third power supply value is smaller than the fifth power supply value, and the fifth power supply value is smaller than the fourth power supply value;
the second type of designated pin comprises: an S2 pin, an S3 pin, an S5 pin, and an S6 pin.
In some embodiments, the high-speed signal connector comprises any one of the following connectors:
standard SlimSAS connectors, MiniSAS HD connectors and Oculink connectors.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic view of a backplate structure according to an embodiment of the present application;
FIG. 2 is a schematic view of another embodiment of a backplate structure according to the present application;
FIG. 3 is a schematic diagram of a high speed signal connector according to one embodiment of the present application;
FIG. 4 is a schematic diagram of a NVME hard disk connector separated from a high-speed signal connector according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a SAS/SATA hard disk connector separated from a high-speed signal connector according to an embodiment of the present application.
Detailed Description
In order to make the technical solutions of the present application better understood by those of ordinary skill in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.
It is noted that the terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples consistent with certain aspects of the present application, as detailed in the appended claims.
In the related art, when the same slot supports two kinds of hard disks, the first kind of hard disk is tested first, and then the second kind of hard disk is tested, and the testing efficiency is low in the method. In this embodiment, signals of the slots can be analyzed and disassembled, so that the same slot can accommodate different types of hard disks, and therefore, tests for different types of hard disks can be completed based on the same slot, and test efficiency is improved.
As shown in fig. 1, a schematic structural diagram of a backplane provided in the embodiments of the present application is shown. The source slot 00 on the communication device in the embodiment of the present application supports different types of hard disks, and the backplane 10 includes a conversion component 101 and a plurality of hard disk connectors 102, where each hard disk connector 102 supports one of the different types of hard disks; wherein:
one end of the conversion component 101 is connected to the source slot 00, and the other end is connected to each of the hard disk connectors 102, so as to separate signals of different types of the hard disk connectors 102 from the source slot 00.
In the embodiment of the application, the same slot is separated out of the hard disk connectors supporting different types of hard disks based on the conversion component, so that the same slot can be used for testing various types of hard disks simultaneously, and the testing efficiency can be improved.
In some embodiments, as shown in fig. 2, the conversion component 101 comprises a first backplane component 1011 and a second backplane component 1012, wherein:
the first backplane component 1011 is connected to the source socket 00, and is configured to convert signals of the source socket 00 into high-speed signal connector signals;
the second backplane component 1012 is used for separating signals of different hard disk connectors 102 from the high-speed signal connector signals.
In the embodiment of the application, different hard disk connectors can be obtained by converting the high-speed signal connector and classifying signals of the high-speed signal connector.
In some embodiments, as shown in FIG. 2, the first backplane component 1012 comprises a hard disk male connector 21, a first backplane 22, and a high-speed signal connector 23;
the hard disk male connector 21 is connected with the source slot 00;
one end of the first backplane 22 is connected to the hard disk male connector 21, and the other end is connected to the high-speed signal connector 23, and is configured to convert a signal of the hard disk male connector 21 into a signal of the high-speed signal connector 23.
Therefore, in the embodiment of the application, the hard disk male connector is used for converting the source slot signal into the signal of the high-speed signal connector through the first back plate, so that the subsequent signal analysis and disassembly are facilitated. The high-speed signal connector may be, for example, a standard high-speed signal connector such as SlimSAS, MiniSAS HD, or Oculink.
In some embodiments, the signals of the hard disk male connector 21 shown in fig. 2 include a first hard disk stray signal, a first power signal, a first PCIE differential signal, and a first designation signal, where the first designation signal is a differential signal of a SATA signal or a differential signal of a SAS signal;
for example, the first hard disk spurious signal includes at least one of: SSD _ RST (reset signal),/SSD _ IFDET (detection signal not inserted into connector),/SSDPrsnt (hard disk type signal),/PWRDIS (hard disk control signal supplied from outside, power is off inside after hard disk is pulled up).
The first power supply signal comprises at least one of: STBY _3V 3/12V/5V.
The first PCIE differential signal includes at least one of: CPU _ SSD _ D _ P/CPU _ SSD _ D _ N (differential pair).
The first designated signal includes SATA/SAS signals such as: RAID _ SAS _ P/RAID _ SAS _ N (differential pair).
The first back plate 22 is specifically configured to:
connecting the first hard disk stray signal to a first stray pin of the high-speed signal connector 23 corresponding to the first hard disk stray signal; as shown in fig. 3, the first type of stray pins include: an A8 pin corresponding to an SSD reset signal, an A9 pin corresponding to an SSD hard disk control signal, an A10 pin corresponding to an SSD detection signal, and an A23 pin corresponding to an SSD hard disk type signal;
the first back plate 22 is specifically configured to: connecting the first power supply signal to a first class power supply pin of the high-speed signal connector 23 corresponding to the first power supply signal; as shown in fig. 3, the first type power supply pin includes: an a17 pin, an a18 pin, an a20 pin, and an a21 pin corresponding to the first power supply, an a30 pin, an a32 pin, an a33 pin, an a35 pin, and an a36 pin corresponding to the second power supply; the first power value is lower than the second power value, for example, the first power value is 5V, and the second power value is 12V.
The first back plate 22 is specifically configured to: connecting the first PCIE differential signal to a first class PCIE pin of the high-speed signal connector 23 corresponding to the first PCIE differential signal; as shown in fig. 3, the first type of PCIE pins include: a pin B5, a pin B6, a pin B8, a pin B9, a pin B17, a pin B18, a pin B20, a pin B21, a pin B23, a pin B24, a pin B26, a pin B27, a pin B29, a pin B30, a pin B32 and a pin B33.
The first back plate 22 is specifically configured to: the first designation signal is connected to a first-class designation pin of the high-speed signal connector 23 corresponding to the first designation signal. The first type designation pin: pin A2, pin A3, pin A5, pin A6.
Based on the implementation of the embodiment of the application, the stray signal, the power signal and the differential signal can be converted to the high-speed signal connector.
In some embodiments, the plurality of hard disk connectors 102 includes an NVME hard disk connector. Based on this, as shown in fig. 2, the high-speed signal connector 23 includes a second hard disk stray signal, a second hard disk power signal, and a second PCIE differential signal for the NVME hard disk;
the second backplane component includes a second backplane 301, and the second backplane 301 is specifically configured to:
connecting the second hard disk stray signal to a second type of stray pin of the NVME hard disk connector 102 corresponding to the second hard disk stray signal; as shown in fig. 4, the second type of stray pin includes: an E5 pin corresponding to an SSD reset signal, a P3 pin corresponding to an SSD hard disk control signal, a P4 pin corresponding to an SSD detection signal, and a P10 pin corresponding to an SSD hard disk type signal;
the second backplane 301 is specifically configured to: and connecting the second power supply signal to a second type power supply pin, corresponding to the second power supply signal, of the NVME hard disk connector 102. As shown in fig. 4, the second type power supply pin includes: an E4 pin, a P4 pin, a P11 pin, and an E25 pin corresponding to a third power supply; a P14 pin and a P15 pin corresponding to a fourth power supply; wherein the third power supply value is less than the fourth power supply value.
The second backplane 301 is specifically configured to: and connecting the second PCIE differential signal to a second PCIE class PCIE pin of the NVME hard disk connector 102 corresponding to the second PCIE differential signal. As shown in fig. 4, the PCIE pins of the second type include: the pin comprises an E10 pin, an E11 pin, an E13 pin, an E14 pin, an S17 pin, an S18 pin, an S20 pin, an S21 pin, an S23 pin, an S24 pin, an S26 pin, an S27 pin, an E17 pin, an E18 pin, an E20 pin and an E21 pin.
Thus, based on the above connection method, the hard disk connector supporting the NVME hard disk can be separated from the high-speed signal connector.
In other embodiments, the designated hard disk supports SATA signals or SAS signals; the plurality of hard disk connectors 102 include a designated hard disk connector of a designated hard disk. As shown in fig. 2, the high-speed signal connector 23 includes a third hard disk power signal and a second designated signal for the designated hard disk, where the second designated signal is a differential signal of a SATA signal or a differential signal of an SAS signal;
the second backplane 31 is specifically configured to connect the third power signal to a third type power pin of the designated hard disk connector 102, where the third type power pin corresponds to the third power signal. As shown in fig. 5, the third type power supply pin includes: a P10 pin corresponding to the third power supply, a P7 pin, a P8 pin, and a P9 pin corresponding to the fifth power supply, a P13 pin, a P14 pin, and a P15 pin corresponding to the fourth power supply; and the third power supply value is smaller than the fifth power supply value, and the fifth power supply value is smaller than the fourth power supply value.
The second backplane 31 is specifically configured to connect the second specific signal to a second type specific pin of the specific hard disk connector 102, where the second type specific pin corresponds to the second specific signal. As shown in fig. 5, the second type designation pin includes: an S2 pin, an S3 pin, an S5 pin, and an S6 pin.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (10)
1. A backplane for use in a communication device, the source slots on the communication device supporting different types of hard disks, the backplane comprising a conversion component and a plurality of hard disk connectors, wherein each hard disk connector supports one of the different types of hard disks;
one end of the conversion component is connected with the source slot, and the other end of the conversion component is connected with each hard disk connector and is used for separating signals of different types of hard disk connectors from the source slot.
2. The backplane of claim 1, wherein the conversion component comprises a first backplane component and a second backplane component, wherein:
the first backboard component is connected with the source slot and used for converting signals of the source slot into high-speed signal connector signals;
and the second back board component is used for separating signals of different hard disk connectors from the signals of the high-speed signal connector.
3. The backplane of claim 2, wherein the first backplane component comprises a hard disk male connector, a first backplane, and a high-speed signal connector;
the hard disk male connector is connected with the source slot;
one end of the first back plate is connected with the hard disk male connector, the other end of the first back plate is connected with the high-speed signal connector, and the first back plate is used for converting a signal of the hard disk male connector into a signal of the high-speed signal connector.
4. The backplane according to claim 3, wherein the signals of the hard disk male connector include a first hard disk spurious signal, a first power signal, a first high-speed serial computer expansion bus (PCIE) differential signal, and a first designation signal, and the first designation signal is a differential signal of a SATA signal or a differential signal of a SAS signal;
the first backplane is specifically configured to connect the first hard disk stray signal to a first type of stray pin of the high-speed signal connector corresponding to the first hard disk stray signal, connect the first power signal to a first type of power pin of the high-speed signal connector corresponding to the first power signal, connect the first PCIE differential signal to a first type of PCIE pin of the high-speed signal connector corresponding to the first PCIE differential signal, and connect the first designation signal to a first type of designation pin of the high-speed signal connector corresponding to the first designation signal.
5. The backing sheet of claim 4,
the first type of stray pins comprises: an A8 pin corresponding to a Solid State Disk (SSD) reset signal, an A9 pin corresponding to an SSD control signal, an A10 pin corresponding to an SSD detection signal and an A23 pin corresponding to an SSD type signal;
the first type of power pin comprises: an a17 pin, an a18 pin, an a20 pin, and an a21 pin corresponding to the first power supply, an a30 pin, an a32 pin, an a33 pin, an a35 pin, and an a36 pin corresponding to the second power supply; wherein the first power supply value is lower than the second power supply value;
the first class of PCIE pins comprises: a pin B5, a pin B6, a pin B8, a pin B9, a pin B17, a pin B18, a pin B20, a pin B21, a pin B23, a pin B24, a pin B26, a pin B27, a pin B29, a pin B30, a pin B32 and a pin B33;
the first type designation pin: pin A2, pin A3, pin A5, pin A6.
6. The backplane of claim 2, wherein the plurality of hard disk connectors comprises NVME hard disk connectors;
the high-speed signal connector comprises a second hard disk stray signal, a second hard disk power supply signal and a second PCIE differential signal, wherein the second hard disk stray signal, the second hard disk power supply signal and the second PCIE differential signal are used for the NVME hard disk of the nonvolatile memory host controller interface specification;
the second backplane component includes a second backplane, and is specifically configured to connect the second hard disk stray signal to a second type of stray pin of the NVME hard disk connector corresponding to the second hard disk stray signal, connect the second power signal to a second type of power pin of the NVME hard disk connector corresponding to the second power signal, and connect the second PCIE differential signal to a second type of PCIE pin of the NVME hard disk connector corresponding to the second PCIE differential signal.
7. The backing sheet of claim 6,
the second type of stray pin comprises: an E5 pin corresponding to an SSD reset signal, a P3 pin corresponding to an SSD hard disk control signal, a P4 pin corresponding to an SSD detection signal, and a P10 pin corresponding to an SSD hard disk type signal;
the second type of power pin comprises: an E4 pin, a P4 pin, a P11 pin, and an E25 pin corresponding to a third power supply; a P14 pin and a P15 pin corresponding to a fourth power supply; wherein the third power supply value is less than the fourth power supply value;
the second type of PCIE pin includes: the pin comprises an E10 pin, an E11 pin, an E13 pin, an E14 pin, an S17 pin, an S18 pin, an S20 pin, an S21 pin, an S23 pin, an S24 pin, an S26 pin, an S27 pin, an E17 pin, an E18 pin, an E20 pin and an E21 pin.
8. The backplane of claim 2, wherein the plurality of hard disk connectors comprise designated hard disk connectors of designated hard disks, the designated hard disks supporting serial hard disk SATA signals or serial attached small computer system interface hard disk SAS signals;
the high-speed signal connector comprises a third hard disk power supply signal and a second specified signal used for the specified hard disk, and the second specified signal is a differential signal of a SATA signal or a differential signal of an SAS signal;
the second backplane is specifically configured to connect the third power signal to a third type power pin of the designated hard disk connector corresponding to the third power signal, and connect the second designated signal to a second type designated pin of the designated hard disk connector corresponding to the second designated signal.
9. The backing sheet of claim 8,
the third type of power pin comprises: a P10 pin corresponding to the third power supply, a P7 pin, a P8 pin, and a P9 pin corresponding to the fifth power supply, a P13 pin, a P14 pin, and a P15 pin corresponding to the fourth power supply; the third power supply value is smaller than the fifth power supply value, and the fifth power supply value is smaller than the fourth power supply value;
the second type of designated pin comprises: an S2 pin, an S3 pin, an S5 pin, and an S6 pin.
10. A backplane according to any of claims 2-9, wherein the high speed signal connectors comprise any of the following connectors:
standard small SAS slim SAS connectors, micro SAS MiniSAS HD connectors, and mini Oculink connectors.
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