CN112527578A - SATA chip signal testing method, system and related assembly - Google Patents
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Abstract
The application discloses a method, a system and a device for testing SATA chip signals and a readable storage medium, which are applied to an operating system of a terminal to be tested with an embedded SATA chip, and the method comprises the following steps: acquiring a memory mapping space of the SATA chip; acquiring a memory mapping base address of the SATA chip; executing the following operations on each code pattern to be tested of the SATA chip: determining an offset address and an address value corresponding to the code pattern to be detected; and adding the memory mapping base address and the offset address to obtain a final address, and modifying the value of the final address in the memory mapping space into an address value so that the SATA chip sends out a signal waveform corresponding to the code pattern to be tested and sends the signal waveform to the oscilloscope for testing. The application can complete the code type conversion without AWG, saves the hardware cost of AWG, is applicable to various SATA chips, and effectively solves the problem that domestic SATA chips do not support AWG code type switching and can not carry out signal testing.
Description
Technical Field
The present invention relates to the field of signal testing, and in particular, to a method, a system, and a related component for testing SATA chip signals.
Background
Currently, a signal integrity test of an SATA (Serial Advanced Technology interface) chip is generally implemented by an AWG (arbitrary Waveform Generator), an SATA fixture and an oscilloscope, where the AWG sends an instruction Waveform to the SATA chip through an RX interface of the SATA fixture, and the SATA chip receives the instruction Waveform, converts a code pattern, sends a test signal, and sends the test signal to the oscilloscope through the TX interface. However, this kind of signal integrity test requires the SATA chip to support code pattern conversion, and is only suitable for the SATA interface and controller chip in foreign countries, and the SATA chip in home does not support this function, and although the SATA chip uses the same SATA protocol, it cannot automatically switch code patterns according to the command waveform of the AWG, which brings a great challenge to the integrity test of the SATA chip in home.
Therefore, how to provide a solution to the above technical problems is a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the present invention provides a method, a system and related components for testing signals of a SATA chip, so as to perform the signal testing of the SATA chip without receiving an instruction waveform of an AWG. The specific scheme is as follows:
a SATA chip signal test method is applied to an operating system of a terminal to be tested with an embedded SATA chip, and comprises the following steps:
acquiring a memory mapping space of the SATA chip;
acquiring a memory mapping base address of the SATA chip;
executing the following operations on each code pattern to be tested of the SATA chip:
determining an offset address and an address value corresponding to the code pattern to be detected;
and adding the memory mapping base address and the offset address to obtain a final address, and modifying the value of the final address in the memory mapping space into the address value so that the SATA chip sends a signal waveform corresponding to the code pattern to be tested and sends the signal waveform to an oscilloscope for testing.
Preferably, the process of determining the offset address and the address value corresponding to the code pattern to be tested includes:
and determining the offset address and the address value corresponding to the code pattern to be detected according to the mapping relation table of the SATA chip.
Preferably, the code patterns to be tested of the SATA chip comprise various code patterns to be tested with different code patterns and different rates.
Preferably, the code pattern includes HETP, MFTP, LFTP, and LBP; the rates include gen1, gen2, and gen 3.
Preferably, the process of determining the offset address and the address value corresponding to the code pattern to be tested includes:
determining a rate offset address and a rate address value corresponding to the code pattern to be detected;
determining a code pattern offset address and a code pattern address value corresponding to the code pattern to be detected;
the process of adding the memory mapping base address and the offset address to obtain a final address, and modifying the value of the final address in the memory mapping space into the address value includes:
adding the memory mapping base address and the rate offset address to obtain a final rate address, modifying the value of the final rate address in the memory mapping space to the rate address value, adding the memory mapping base address and the code pattern offset address to obtain a final code pattern address, and modifying the value of the final code pattern address in the memory mapping space to the code pattern address value.
Preferably, the SATA interface of the terminal to be tested is connected to a SATA test fixture, and a TX signal output port of the SATA test fixture is connected to an oscilloscope.
Preferably, after the adding the memory mapping base address and the offset address to obtain a final address and modifying the value of the final address in the memory mapping space to the address value, the method further includes:
and adjusting the emphasis and/or the signal slew rate in the memory mapping space to optimize the signal waveform.
Correspondingly, this application has still disclosed a SATA chip signal test system, includes:
the system comprises an acquisition module, a storage mapping module and a processing module, wherein the acquisition module is used for acquiring a storage mapping space of an SATA chip and also used for acquiring a storage mapping base address of the SATA chip;
the action module is used for executing the following operations on each code pattern to be tested of the SATA chip:
determining an offset address and an address value corresponding to the code pattern to be detected;
and adding the memory mapping base address and the offset address to obtain a final address, and modifying the value of the final address in the memory mapping space into the address value so that the SATA chip sends a signal waveform corresponding to the code pattern to be tested and sends the signal waveform to an oscilloscope for testing.
Correspondingly, this application still discloses a SATA chip signal testing arrangement, includes:
a memory for storing a computer program;
a processor for implementing the steps of the SATA chip signal testing method as described in any of the above when the computer program is executed.
Correspondingly, the application also discloses a readable storage medium, wherein a computer program is stored on the readable storage medium, and when the computer program is executed by a processor, the computer program realizes the steps of the SATA chip signal testing method.
The application discloses a SATA chip signal test method, which is applied to an operating system of a terminal to be tested with an embedded SATA chip, and comprises the following steps: acquiring a memory mapping space of the SATA chip; acquiring a memory mapping base address of the SATA chip; executing the following operations on each code pattern to be tested of the SATA chip: determining an offset address and an address value corresponding to the code pattern to be detected; and adding the memory mapping base address and the offset address to obtain a final address, and modifying the value of the final address in the memory mapping space into the address value so that the SATA chip sends a signal waveform corresponding to the code pattern to be tested and sends the signal waveform to an oscilloscope for testing. According to the method, the SATA chip signal test is executed by utilizing the operating system of the terminal to be tested, the code pattern is converted by changing the address value in the memory mapping space of the SATA chip, and then the signal waveform is acquired and sent to the oscilloscope for testing.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a flowchart illustrating a method for testing SATA chips according to an embodiment of the present invention;
FIG. 2 is an environment configuration diagram of a SATA chip signal testing method according to an embodiment of the present invention;
FIG. 3 is a diagram of a SATA chip signal testing system according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The existing signal integrity test requires that the SATA chip supports code pattern conversion, is only suitable for foreign SATA interfaces and controller chips, and the domestic SATA chip does not support the function, although the same SATA protocol is used, the code pattern cannot be automatically switched according to the instruction waveform of the AWG, which brings great challenge to the integrity test of the domestic SATA chip. According to the method, the SATA chip signal test is executed by utilizing the operating system of the terminal to be tested, the code pattern is converted by changing the address value in the memory mapping space of the SATA chip, and then the signal waveform is acquired and sent to the oscilloscope for testing.
The embodiment of the invention discloses a SATA chip signal testing method, which is applied to an operating system of a terminal to be tested with an embedded SATA chip, and is shown in figure 1, and comprises the following steps:
s1: acquiring a memory mapping space of the SATA chip;
s2: acquiring a memory mapping base address of the SATA chip;
s3: executing the following operations on each code pattern to be tested of the SATA chip:
s31: determining an offset address and an address value corresponding to the code pattern to be detected;
s32: and adding the memory mapping base address and the offset address to obtain a final address, and modifying the value of the final address in the memory mapping space into an address value so that the SATA chip sends out a signal waveform corresponding to the code pattern to be tested and sends the signal waveform to the oscilloscope for testing.
Specifically, the environment of the method for testing SATA chip signals in this embodiment is as shown in fig. 2, where an SATA interface of a terminal to be tested (DUT) is connected to a SATA Test fixture, a TX signal output port of the SATA Test fixture is connected to an oscilloscopes oscilloscope, and actually, the SATA interface of the terminal to be tested is connected to the SATA chip.
It can be understood that the memory mapping relationship of the SATA chip changes, and the working state of the SATA chip changes, so that the working state of the SATA chip can be adjusted by modifying the memory mapping, that is, the output code pattern of the signal, the execution main body of the modification action is the operating system OS of the terminal to be tested in which the SATA chip is embedded, the operating system has high activity and freedom, and can operate various objects in the terminal to be tested, after the memory mapping is modified, the SATA chip sends out the signal waveform of the code pattern to be tested, and sends the signal waveform to the oscilloscope through the SATA test fixture, and the oscilloscope completes the test.
It can be understood that the SATA chip has a plurality of patterns to be tested, the operations of steps S31-S32 are performed for each pattern, and finally the oscilloscope collects signal waveforms of all the patterns to be tested, so that the overall performance of the SATA chip and the signal integrity of the SATA interface can be determined.
According to the method, the SATA chip signal test is executed by utilizing the operating system of the terminal to be tested, the code pattern is converted by changing the address value in the memory mapping space of the SATA chip, and then the signal waveform is acquired and sent to the oscilloscope for testing.
The embodiment of the invention discloses a specific SATA chip signal testing method, and compared with the previous embodiment, the embodiment further explains and optimizes the technical scheme. Specifically, the method comprises the following steps:
the process of determining the offset address and the address value corresponding to the code pattern to be tested includes:
and determining the offset address and the address value corresponding to the code pattern to be detected according to the mapping relation table of the SATA chip.
The code patterns to be tested of the SATA chip comprise various code patterns to be tested with different code patterns and different rates. That is, a code pattern under test has two parameters that determine its signal characteristics: the code pattern and the rate, the two parameters are unrelated and in parallel relation, and different waveform signals can be shown by the code pattern to be detected when any parameter is different. Specifically, in the code Pattern to be tested of the SATA chip, the code Pattern generally includes HETP (High Frequency Test Pattern), MFTP (Mid Frequency Test Pattern), LFTP (Low Frequency Test Pattern), and LBP (line Bit Pattern), and the rate generally includes gen1, gen2, and gen 3.
Further, the process of determining the offset address and the address value corresponding to the code pattern to be tested includes:
determining a rate offset address and a rate address value corresponding to the code pattern to be detected;
determining a code pattern offset address and a code pattern address value corresponding to the code pattern to be detected;
the process of adding the memory mapping base address and the offset address to obtain a final address and modifying the value of the final address in the memory mapping space into an address value comprises the following steps: adding the memory mapping base address and the rate offset address to obtain a final rate address, modifying the value of the final rate address in the memory mapping space into a rate address value, adding the memory mapping base address and the code pattern offset address to obtain a final code pattern address, and modifying the value of the final code pattern address in the memory mapping space into a code pattern address value.
At this time, the mapping relationship table of the SATA chip is shown in the following table, where register is an offset address, value is an address value, command is an instruction used for modification, lines gen1/gen2/gen3 of each code pattern correspond to a rate address, a rate address value and an instruction of the rate, gen 1-3 lines represent a code pattern address, a code pattern address value and an instruction of the code pattern, and a base in the instruction is a memory mapping base address. Taking the code type to be tested of the code type HETP and the rate gen3 as an example, according to the method for modifying the memory mapping space value described above, the rate offset addresses and the rate address values corresponding to the HETP column and the gen3 row in the table are determined to be 0xf32 and 0xc6 respectively, then the code type offset addresses and the code type address values corresponding to the HETP column and the gen 1-3 rows in the table are determined to be 0xf45 and 0x0 respectively, and corresponding instructions are sequentially output, that is, the actions of adding the memory mapping base address and the rate offset addresses to obtain a final rate address, modifying the value of the final rate address in the memory mapping space to a rate address value, adding the memory mapping base address and the code type offset addresses to obtain a final code type address, and modifying the value of the final code type address in the memory mapping space to a code type address value are completed.
Table 1 relational mapping table of SATA chip
The testing process of the embodiment does not need the AWG, saves the cost of the AWG equipment, and the whole process is automatically carried out by the operating system, and the testing process is simple and quick.
The embodiment of the invention discloses a specific SATA chip signal testing method, and compared with the previous embodiment, the embodiment further explains and optimizes the technical scheme. Specifically, the method comprises the following steps:
adding the memory mapping base address and the offset address to obtain a final address, and after modifying the value of the final address in the memory mapping space into an address value, the method further comprises the following steps:
and adjusting the emphasis and/or the signal slew rate in the memory mapping space to optimize the signal waveform.
It can be understood that the adjustment of the emolisis and/or the signal skew rate is also implemented by adjusting the address values in the memory mapping space, and as shown in table 2 and table 3, the comparison of the signal waveforms before and after the adjustment and optimization is performed, the measured value before the optimization is 2.4336 and exceeds the normal range (-2, 1.5), and the measured value after the optimization is 0.7429, and in the normal range, the quality of the signal waveform is optimized.
TABLE 2 adjusting signal waveform parameter values before optimization
TABLE 3 adjusting optimized Signal waveform parameter values
Therefore, in the embodiment, by adjusting the memory mapping, multiple functions of signal testing, debug, signal optimization and the like of the SATA chip are realized, and the method has a very high practical value.
Correspondingly, an embodiment of the present application further discloses a SATA chip signal testing system, as shown in fig. 3, including:
the system comprises an acquisition module 1, a storage mapping module and a processing module, wherein the acquisition module 1 is used for acquiring a storage mapping space of the SATA chip and also used for acquiring a storage mapping base address of the SATA chip;
the action module 2 is used for executing the following operations on each code pattern to be tested of the SATA chip:
determining an offset address and an address value corresponding to the code pattern to be detected;
and adding the memory mapping base address and the offset address to obtain a final address, and modifying the value of the final address in the memory mapping space into an address value so that the SATA chip sends out a signal waveform corresponding to the code pattern to be tested and sends the signal waveform to the oscilloscope for testing.
According to the method, the SATA chip signal test is executed by utilizing the operating system of the terminal to be tested, the code pattern is converted by changing the address value in the memory mapping space of the SATA chip, and then the signal waveform is acquired and sent to the oscilloscope for testing.
In some specific embodiments, the action module 2 is specifically configured to:
and determining the offset address and the address value corresponding to the code pattern to be detected according to the mapping relation table of the SATA chip.
In some specific embodiments, the code patterns to be tested of the SATA chip include a plurality of code patterns to be tested with different code patterns and different rates.
In some specific embodiments, the pattern comprises HETP, MFTP, LFTP, and LBP; the rates include gen1, gen2, and gen 3.
In some specific embodiments, the action module 2 is specifically configured to:
determining a rate offset address and a rate address value corresponding to the code pattern to be detected;
determining a code pattern offset address and a code pattern address value corresponding to the code pattern to be detected;
adding the memory mapping base address and the rate offset address to obtain a final rate address, modifying the value of the final rate address in the memory mapping space to the rate address value, adding the memory mapping base address and the code pattern offset address to obtain a final code pattern address, and modifying the value of the final code pattern address in the memory mapping space to the code pattern address value.
In some specific embodiments, the SATA interface of the terminal to be tested is connected to a SATA test fixture, and a TX signal output port of the SATA test fixture is connected to an oscilloscope.
In some specific embodiments, the action module 2 is further configured to:
and adjusting the emphasis and/or the signal slew rate in the memory mapping space to optimize the signal waveform.
Correspondingly, the embodiment of the present application further discloses a SATA chip signal testing apparatus, including:
a memory for storing a computer program;
a processor for implementing the steps of the SATA chip signal testing method as described in any of the above when the computer program is executed.
Correspondingly, an embodiment of the present application further discloses a readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the steps of the SATA chip signal testing method as described in any one of the above.
The details of the SATA chip signal testing method can refer to the related description in the above embodiments, and are not repeated herein.
The SATA chip signal testing apparatus and the readable storage medium in this embodiment have the same advantages as the SATA chip signal testing method in the above embodiment, and are not described here again.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The SATA chip signal testing method, system and related components provided by the present invention are introduced in detail, and a specific example is applied in the present disclosure to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A SATA chip signal test method is characterized in that an operating system applied to a terminal to be tested with an embedded SATA chip comprises the following steps:
acquiring a memory mapping space of the SATA chip;
acquiring a memory mapping base address of the SATA chip;
executing the following operations on each code pattern to be tested of the SATA chip:
determining an offset address and an address value corresponding to the code pattern to be detected;
and adding the memory mapping base address and the offset address to obtain a final address, and modifying the value of the final address in the memory mapping space into the address value so that the SATA chip sends a signal waveform corresponding to the code pattern to be tested and sends the signal waveform to an oscilloscope for testing.
2. The method for SATA chip signal testing according to claim 1, wherein said determining offset addresses and address values corresponding to the patterns to be tested comprises:
and determining the offset address and the address value corresponding to the code pattern to be detected according to the mapping relation table of the SATA chip.
3. The SATA chip signal testing method according to claim 2,
the code patterns to be tested of the SATA chip comprise various code patterns to be tested with different code patterns and different rates.
4. The SATA chip signal testing method according to claim 3,
the code pattern comprises HETP, MFTP, LFTP and LBP;
the rates include gen1, gen2, and gen 3.
5. The SATA chip signal testing method according to claim 4,
the process of determining the offset address and the address value corresponding to the code pattern to be tested includes:
determining a rate offset address and a rate address value corresponding to the code pattern to be detected;
determining a code pattern offset address and a code pattern address value corresponding to the code pattern to be detected;
the process of adding the memory mapping base address and the offset address to obtain a final address, and modifying the value of the final address in the memory mapping space into the address value includes:
adding the memory mapping base address and the rate offset address to obtain a final rate address, modifying the value of the final rate address in the memory mapping space to the rate address value, adding the memory mapping base address and the code pattern offset address to obtain a final code pattern address, and modifying the value of the final code pattern address in the memory mapping space to the code pattern address value.
6. The SATA chip signal testing method according to any one of claims 1 to 5, wherein a SATA interface of the terminal to be tested is connected to a SATA test fixture, and a TX signal output port of the SATA test fixture is connected to an oscilloscope.
7. The SATA chip signal testing method according to claim 6,
after the adding the memory mapping base address and the offset address to obtain a final address and modifying the value of the final address in the memory mapping space to the address value, the method further includes:
and adjusting the emphasis and/or the signal slew rate in the memory mapping space to optimize the signal waveform.
8. A SATA chip signal test system, comprising:
the system comprises an acquisition module, a storage mapping module and a processing module, wherein the acquisition module is used for acquiring a storage mapping space of an SATA chip and also used for acquiring a storage mapping base address of the SATA chip;
the action module is used for executing the following operations on each code pattern to be tested of the SATA chip:
determining an offset address and an address value corresponding to the code pattern to be detected;
and adding the memory mapping base address and the offset address to obtain a final address, and modifying the value of the final address in the memory mapping space into the address value so that the SATA chip sends a signal waveform corresponding to the code pattern to be tested and sends the signal waveform to an oscilloscope for testing.
9. A SATA chip signal testing device, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the SATA chip signal testing method according to any one of claims 1 to 7 when said computer program is executed.
10. A readable storage medium, having stored thereon a computer program which, when executed by a processor, implements the steps of the SATA chip signal testing method according to any one of claims 1 to 7.
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| CN113268390A (en) * | 2021-06-10 | 2021-08-17 | 浪潮电子信息产业股份有限公司 | Testing jig, system and method for mSATA interface |
| WO2022116670A1 (en) * | 2020-12-04 | 2022-06-09 | 浪潮电子信息产业股份有限公司 | Sata chip signal test method and system, and related components |
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| CN107346276A (en) * | 2017-07-04 | 2017-11-14 | 济南浪潮高新科技投资发展有限公司 | One kind is based on domestic processor platform SATA chip signal testing tools |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2022116670A1 (en) * | 2020-12-04 | 2022-06-09 | 浪潮电子信息产业股份有限公司 | Sata chip signal test method and system, and related components |
| CN113268390A (en) * | 2021-06-10 | 2021-08-17 | 浪潮电子信息产业股份有限公司 | Testing jig, system and method for mSATA interface |
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