CN112527550B - Method for generating rereading table of storage device, testing device and storage medium - Google Patents
Method for generating rereading table of storage device, testing device and storage medium Download PDFInfo
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- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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Abstract
The application discloses a method for generating a memory device rereading table, a memory testing device and a memory medium. The method comprises the following steps: the method for generating the rereading table of the storage device comprises the following steps: acquiring a plurality of initial read reference voltages corresponding to one word line; each word line of the memory device is connected with a plurality of memory cells, each memory cell comprises at least one page, and each page comprises at least one initial read reference voltage; determining a read reference voltage corresponding to the initial read reference voltage; and recording the difference value between the read reference voltage and each initial read reference voltage to the rereading table. According to the scheme, the rereading table of the storage device can be conveniently and rapidly obtained, and accuracy of rereading values in the obtained rereading table can be improved.
Description
Technical Field
The present invention relates to the field of memory technologies, and in particular, to a method for generating a rereading table of a storage device, a memory test device, and a storage medium.
Background
FLASH memory (FLASH memory) has characteristics of fast read/write performance, low power consumption, and the like, compared with conventional hard disk devices. Flash memory is a commonly used data storage device. The flash memory can set the read voltage according to the read voltage parameter of the read command sent by the controller. The flash memory may also read the data voltage according to the address of the read command. The flash memory converts the data voltage into corresponding data according to the read voltage and sends the corresponding data to the controller. To reduce costs, flash technology has evolved to smaller and smaller geometries and higher densities (more bits per cell), making read errors a major problem for flash reliability. Because Data Retention (Data Retention), read disturb (read disturb) or program disturb (program disturb) causes the Data voltage output by the cell to shift to a lower (or higher) voltage, the shifted Data voltage may cause a Data read error. If the read voltage is not at an appropriate level, more erroneous bits may be caused in the corresponding data after reading/conversion.
Disclosure of Invention
The technical problem that this application mainly solves is to provide a storage device rereading table's generating method, a memory testing arrangement and computer readable storage medium, can acquire storage device rereading table conveniently and swiftly, and can improve the degree of accuracy of the rereading value in the rereading table who acquires.
In order to solve the technical problems, one technical scheme adopted by the application is as follows: the method for generating the rereading table of the storage device comprises the following steps: a plurality of initial read reference voltages corresponding to one word line are obtained. Each word line of the memory device is connected with a plurality of memory cells, each memory cell comprises at least one page, and each page comprises at least one initial read reference voltage. A plurality of offset reference voltages are determined based on each initial read reference voltage. And respectively applying each offset reference voltage to the word line to obtain the error code number corresponding to each offset reference voltage. And determining offset reference voltages corresponding to minimum values or minimum values in the error code digits as read reference voltages corresponding to the initial read reference voltages. And recording the difference value between the read reference voltage and each initial read reference voltage to the rereading table.
Further, applying each offset reference voltage to the word line, respectively, to obtain the number of error codes corresponding to each offset reference voltage includes: each offset reference voltage is respectively applied to the word line so as to read the data of the page corresponding to the initial read reference voltage in the memory cells, and finally, a plurality of data of the page corresponding to the initial read reference voltage are obtained. And comparing the plurality of data of the page corresponding to the initial read reference voltage with the original data of the page corresponding to the initial read reference voltage respectively to obtain the error code number corresponding to each offset reference voltage.
Further, applying each offset reference voltage to the word line to read the data of the page corresponding to the initial read reference voltage in the plurality of memory cells, and finally obtaining the plurality of data of the page corresponding to the initial read reference voltage includes: if the page corresponding to the initial read reference voltage comprises at least two initial read reference voltages, when the read reference voltage corresponding to the current initial read reference voltage is determined, the page is read based on the read reference voltages corresponding to other initial reference voltages.
Further, when determining the read reference voltage corresponding to the current initial read reference voltage, reading the page based on the read reference voltages corresponding to the other initial reference voltages includes: the data state of the page is determined based on the coordinate interval composed of the offset reference voltage and the read reference voltages corresponding to the other initial reference voltages.
Further, if the page corresponding to the initial read reference voltage includes at least two initial read reference voltages, when determining the read reference voltage corresponding to the current initial read reference voltage, reading the page based on the read reference voltages corresponding to the other initial reference voltages includes: if the other initial reference voltages do not have the corresponding read reference voltages, the other initial reference voltages are used as the read reference voltages corresponding to the other initial reference voltages.
Further, each page includes at least one initial read reference voltage, corresponding to an ideal read reference voltage for the data state of each page without voltage offset.
Further, determining a plurality of offset reference voltages from each initial read reference voltage includes: and performing multiple offsets on the initial read reference voltage in a preset offset interval to obtain multiple offset reference voltages.
Further, the storage device is NAND FLASH memory.
In order to solve the technical problems, another technical scheme adopted by the application is as follows: there is provided a memory test device connected to a storage device for testing the storage device, the memory test device comprising a memory for storing program data and a processor for executing the program data to implement the steps of the above method.
In order to solve the technical problems, another technical scheme adopted by the application is as follows: there is provided a computer readable storage medium storing a computer program which, when executed by a processor, performs the steps of the above method.
The beneficial effects of this application are: different from the situation of the prior art, the method for generating the re-reading table of the storage device provided by the application respectively determines the read reference voltages corresponding to each page of the plurality of storage units connected with each word line of the storage units, namely, when determining the read reference voltages of each page, the read reference voltages are independent and do not interfere with each other, so that the read reference voltages corresponding to the initial read reference voltages of each page can be conveniently and rapidly determined. In addition, the offset reference voltage corresponding to the minimum value or the minimum value in the plurality of error code digits is selected as the read reference voltage corresponding to the initial read reference voltage, so that the accuracy of the acquired read reference voltage can be improved, and the accuracy of the re-read value in the re-read table is further improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a statistical distribution of threshold voltages of memory cells in a memory device;
FIG. 2 is a schematic diagram of a memory device before and after a threshold voltage shift;
FIG. 3 is a flowchart illustrating an embodiment of a method for generating a memory device rereading table according to the present application;
FIG. 4 is a flowchart illustrating an embodiment of step S30 in FIG. 3;
FIG. 5 is a schematic diagram of an embodiment of a memory test device provided herein;
fig. 6 is a schematic structural diagram of an embodiment of a computer-readable storage medium provided in the present application.
Detailed Description
The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
The principle of the memory for storing information is to change the threshold voltage by changing the charge amount stored in the storage medium so as to achieve the purpose of storing information. For example, a memory cell in an erased (erase) data state may be considered to have no electrons in its storage medium, so its threshold voltage is small, typically less than 0V, whereas for a memory cell in a stored data state there is electrons in its storage medium, its threshold voltage is typically greater than 0V, so that the case where the threshold voltage is less than 0V is considered to have its stored information as 1, and the case where the threshold voltage is greater than 0V is considered to have its stored information as 0, thus achieving the purpose of storing information.
With the advancement of technology, it is currently possible to store multi-bit information in one memory cell, i.e., a multi-level memory cell. The implementation method comprises the following steps: multiple sets of threshold voltages are designed to divide the memory into multiple data states. NAND (NAND) type flash memories can be classified into single-level memory cell NAND type flash memories (i.e., flash memory modules that can store 1 bit of data in one memory cell), multi-level memory cell NAND type flash memories (i.e., flash memory modules that can store 2 bits of data in one memory cell) and multi-level memory cell type flash memories (i.e., flash memory modules that can store 3 bits of data in one memory cell) according to the number of bits that can be stored per memory cell of the memory device. It should be noted that, the method for generating the memory device rereading table provided in this embodiment is applicable to any memory device of the above memory cell type.
Referring to fig. 1, fig. 1 is a statistical distribution diagram of threshold voltages of all memory cells in a memory device. Referring to fig. 1, the abscissa indicates the threshold voltage, the ordinate indicates the number of memory cells at the threshold voltage, and the statistical distribution of the threshold voltage is similar to the normal distribution after the data is written into the memory. In FIG. 1, the memory includes eight data states L1-L8. As can be seen from fig. 1, the threshold voltages of each data state are different, so that when writing to the data states, a corresponding read reference voltage needs to be applied to read data from the target memory cell, thereby determining the data state of the memory cell. However, when the data retention of the memory is lowered, the threshold voltage of the memory is shifted, and typically, left.
Referring to fig. 2, fig. 2 is a schematic diagram of a memory device before and after a threshold voltage shift, as shown in fig. 2, wherein the threshold voltage is shown by a solid line before the threshold voltage shift, and the threshold voltage is shown by a dotted line after the threshold voltage shift, and the threshold voltage shifts to the left. If the threshold voltage of the memory has been shifted, the initial read reference voltage (i.e., the read reference voltage before the shift of the threshold voltage) is still applied to the target memory cell, the information of the memory is misread, resulting in a large number of error bits (fbc). Therefore, before performing read-write operation on the memory, the read reference voltage is usually debugged so as to meet the requirements, thereby avoiding generating a large number of error code digits.
The readback table of the memory device is recorded with the adjustment value of the initial read reference voltage in a plurality of memory cells connected with each word line of the memory device, the controller of the memory device (or the management circuit of the memory device) instructs the memory device to correspondingly adjust the initial read reference voltage according to the adjustment value of the initial read reference voltage in the readback table, and the data stored in the memory cells is read from the word lines by the adjusted initial read reference voltage.
The inventors of the present application have long studied and found that in the process of constructing a rereading table of a memory device, in general, a plurality of initial read reference voltages are adjusted in a mutually dependent manner when determining a rereading value of each of the initial read reference voltages, wherein the plurality of read reference voltages may correspond to different pages of a plurality of memory cells connected to the same word line. That is, the initial read reference voltage of one page of memory cells of a word line, when adjusted, will depend on the initial read reference voltage of the other page. In practice, the initial read reference voltages corresponding to the pages are independent of each other when reading data, i.e., when reading data of one page, the initial read reference voltage to the other page cannot be utilized. When the re-reading value corresponding to the initial reading reference voltage is determined in the traditional method, the data of the current page is read by utilizing the initial reading reference voltages of other pages, and the method is too complex, so that not only is the excessive calculated amount and the running time needed, but also the efficiency of the whole re-reading table generation process is low, and the obtained result is not accurate enough.
Based on this, the present application proposes a method for generating a rereading table of a memory device, which independently adjusts an initial read reference voltage of each page, wherein the initial read reference voltage corresponds to one page of a plurality of memory cells connected to the same word line, so as to obtain a rereading value of the initial read reference voltage of the page.
Specifically, referring to fig. 3, fig. 3 is a flowchart illustrating an embodiment of a method for generating a memory device rereading table provided in the present application.
In this embodiment, the storage device may be a NAND FLASH memory, for example, a portable disk, a solid state disk (Solid State Drives, SSD), or other storage devices, which are not limited herein.
As shown in fig. 3, the method comprises the steps of:
step S10, a plurality of initial read reference voltages corresponding to one word line are obtained. Each word line of the memory device is connected with a plurality of memory cells, each memory cell comprises at least one page, and each page comprises at least one initial read reference voltage.
In practice, the memory device includes a plurality of memory cells for storing data, a plurality of select gate drain (select gate drain, SGD) transistors and a plurality of select gate source (select gate source, SGS) transistors, and a plurality of bit lines, a plurality of word lines, and a common source line connecting the memory cells. The memory cells are arranged in an array at intersections of bit lines and word lines. When a write command or read data is received from a controller of the memory device, the control circuit controls the word line control circuit, the bit line control circuit, the row decoder, the data input/output buffer to write data into or read data from the memory cell, wherein the word line control circuit is used for controlling voltages applied to the word line, the bit line control circuit is used for controlling voltages applied to the bit line, the row decoder selects the corresponding bit line according to a decoded row address in the command, and the data input/output buffer is used for temporarily storing data.
If the storage device is a multi-level storage cell NAND type flash memory or a multi-level storage cell NAND type flash memory, each storage cell of the storage device includes at least 2 pages of binary data, generally, before the storage device leaves the factory, the manufacturer will set at least one initial read reference voltage for each page of the plurality of storage cells on each word line, and the initial read reference voltage of the page may be an ideal read reference voltage corresponding to the data state of the page of the storage device under the condition that the voltage has no offset.
In this step, the obtained initial read reference voltage may be an initial read reference voltage corresponding to each page of the plurality of memory cells connected to the word line.
Step S20, determining a plurality of offset reference voltages according to each initial read reference voltage.
In this embodiment, the initial read reference voltage may be shifted multiple times within a preset shift interval to obtain multiple shifted reference voltages.
The preset offset interval may be, for example, an interval including the initial read reference voltage. For example, the preset offset interval may be [ (V) Initial initiation -0.3),(V Initial initiation +0.2)]。
Optionally, the initial read reference voltage is changed at a regular pattern within a predetermined offset interval, for example, the initial read reference voltage is increased or decreased by a predetermined step, and it is understood that the predetermined step may be a fixed step or a variable step. When the preset step size is a fixed step size, the value of the preset step size includes but is not limited to 0.05V or 0.025V, etc., and the preset step size can also be directly set as the step size set by the memory reading device.
Step S30, each offset reference voltage is respectively applied to the word line, and the error code number corresponding to each offset reference voltage is obtained.
Specifically, referring to fig. 4, fig. 4 is a schematic flow chart of an embodiment of step S30 in fig. 3, and as shown in fig. 4, step S30 may include:
s31: each offset reference voltage is respectively applied to the word line so as to read the data of the page corresponding to the initial read reference voltage in the memory cells, and finally, a plurality of data of the page corresponding to the initial read reference voltage are obtained.
In this step, data of a corresponding page (page corresponding to the initial read reference voltage) of a plurality of memory cells connected to the word line is read using each offset reference voltage as a read reference voltage of the word line, respectively, to obtain data of a corresponding page of each memory cell.
S32: and comparing the read multiple data of the page corresponding to the initial read reference voltage with the original data of the page corresponding to the initial read reference voltage respectively to obtain the error code number corresponding to each offset reference voltage.
Specifically, the original data of the page corresponding to the initial read reference voltage refers to data stored in the page corresponding to the initial read reference voltage without bias. For example, when the page corresponding to the initial read reference voltage stores 1 data without bias, but when a certain offset reference voltage is applied to the word line, the data of the page of the memory cell is read as 0, the bit error number corresponding to the offset reference voltage is increased by one.
In one embodiment, the storage device has a function of calculating the number of error codes, and the algorithm of calculating the number of error codes carried by the storage device can be directly utilized to obtain the number of error codes corresponding to each offset reference voltage.
In another embodiment, for a page including at least two initial read reference voltages, the present embodiment further provides another method for calculating the number of error codes corresponding to each offset reference voltage.
In the present embodiment, the term "page including at least two initial read reference voltages" means that the data state of at least one page of memory cells to which a certain word line is connected is determined by at least two initial read reference voltages.
Specifically, if the page corresponding to the initial read reference voltage includes at least two initial read reference voltages, when determining the read reference voltage corresponding to the current initial read reference voltage, reading the page based on the read reference voltages corresponding to other initial reference voltages. Further, based on the coordinate interval formed by each offset reference voltage and the read reference voltages corresponding to other initial reference voltages, the data state of the page corresponding to the initial read reference voltage is determined.
That is, in the present embodiment, when a certain offset reference voltage is applied to a certain word line, data of a page corresponding to an initial read reference voltage among a plurality of memory cells connected to the word line is determined by a coordinate section composed of the offset reference voltage and the read reference voltages corresponding to other initial reference voltages.
Taking a complex-level memory cell NAND type flash memory as an example, it should be noted that the following method for calculating the number of error codes corresponding to each offset reference voltage provided in this embodiment is only exemplary and not limited thereto.
In the prior art, assuming that the lower page of the plurality of memory cells connected to a certain word line of the NAND-type flash memory with plural memory cells includes 2 initial read reference voltages (may also include 3 or more) and is set to a first initial read reference voltage and a second initial read reference voltage, when determining the first read reference voltage corresponding to the first initial read reference voltage connected to the word line, the lower page of the plurality of memory cells connected to the word line may be read based on the second read reference voltage corresponding to the second initial read reference voltage.
More specifically, when a certain offset reference voltage is applied to a certain word line, the data of the lower page of the plurality of memory cells connected to the word line is determined by a coordinate interval composed of the offset reference voltage and a second read reference voltage corresponding to the second initial read reference voltage.
It will be appreciated that if the second initial read reference voltage does not have a corresponding second read reference voltage, in other words, the second initial read reference voltage has not been adjusted, the second initial read reference voltage is used as the read reference voltage corresponding to the second initial read reference voltage.
In this case, when a certain offset reference voltage is applied to a certain word line, data of the lower page of the plurality of memory cells connected to the word line is determined by a coordinate section composed of the offset reference voltage and the second initial read reference voltage.
In determining the number of error codes of the offset reference voltage, the conventional method is to replace the first initial read reference voltage with the offset reference voltage, and divide the coordinate axis into three coordinate intervals by using the offset reference voltage and the second initial read reference voltage, so as to read the data of the lower page in each memory cell.
Unlike the conventional method, in this embodiment, the offset reference voltage is used to replace the first initial read reference voltage, and the coordinate axis is divided into three coordinate intervals by using the second read reference voltage corresponding to the offset reference voltage and the second initial read reference voltage, so as to read the data of the lower page in each memory cell. Obviously, the second read reference voltage is a read reference voltage which is more accurate than the second initial read reference voltage after being adjusted, so that the error code number corresponding to the offset reference voltage can be more accurately determined, and finally the first read reference voltage corresponding to the obtained first initial read reference voltage is more accurate.
In summary, the memory device has at least two pages of initial read reference voltages, and when the read reference voltage corresponding to the current initial read reference voltage is determined, the page can be acquired based on the read reference voltages corresponding to other initial read reference voltages.
Step S40, determining offset reference voltages corresponding to minimum values or minimum values in a plurality of error code digits as read reference voltages corresponding to a plurality of initial read reference voltages.
In determining the most accurate one of all offset reference voltages, the conventional manner is to use the one of all offset reference voltages with the smallest number of error codes as the corresponding read reference voltage of the initial read reference voltage.
Since the point of the minimum number of error bits is not necessarily the optimal reference voltage point, when the number of error bits is the minimum value, the reference voltage is often better. Based on this, in the present embodiment, when at least one minimum value exists in all the offset reference voltages, the minimum value may be used as the read reference voltage corresponding to the initial read reference voltage. In this way, a most accurate offset reference voltage can be determined in the event of fluctuations in the number of erroneous code bits.
And S50, recording the difference value between the read reference voltage and each initial read reference voltage to a rereading table.
By the method, the read reference voltage corresponding to the initial read reference voltage of each page in the plurality of memory cells connected with each word line of the memory device can be obtained, and then the rereading table of the memory device can be obtained.
In summary, the method for generating a rereading table of a storage device provided in the present application provides a method for generating a rereading table of a storage device, which includes: a plurality of initial read reference voltages corresponding to one word line are obtained. Each word line of the memory device is connected with a plurality of memory cells, each memory cell comprises at least one page, and each page comprises at least one initial read reference voltage. A plurality of offset reference voltages are determined based on each initial read reference voltage. And respectively applying each offset reference voltage to the word line to obtain the error code number corresponding to each offset reference voltage. And determining offset reference voltages corresponding to minimum values or minimum values in the error code digits as read reference voltages corresponding to the initial read reference voltages. And recording the difference value between the read reference voltage and each initial read reference voltage to the rereading table. That is, the method for generating the re-reading table provided in this embodiment determines the read reference voltages corresponding to each page of the plurality of memory cells connected to each word line of the memory cells, that is, the read reference voltages of each page are independent from each other and do not interfere with each other when determining the read reference voltages of each page, so that the read reference voltages corresponding to the initial read reference voltages of each page can be determined conveniently and rapidly. In addition, the offset reference voltage corresponding to the minimum value or the minimum value in the plurality of error code digits is selected as the read reference voltage corresponding to the initial read reference voltage. The accuracy of the acquired read reference voltage can be improved.
Referring to fig. 5, fig. 5 is a schematic structural diagram of an embodiment of a memory test device provided in the present application, where the memory test device 100 is connected to a storage device 200 and is used for testing the storage device 200, the memory test device 100 includes a memory 110 and a processor 120, the memory 110 is used for storing program data, and the processor 120 is used for executing the program data to implement the method for generating a re-reading table.
The memory test device 100 may be used, for example, to obtain a plurality of initial read reference voltages corresponding to one word line. Wherein each word line of the memory device 200 is connected to a plurality of memory cells, each memory cell including at least one page, each page including at least one initial read reference voltage. A plurality of offset reference voltages are determined based on each initial read reference voltage. And respectively applying each offset reference voltage to the word line to obtain the error code number corresponding to each offset reference voltage. And determining offset reference voltages corresponding to minimum values or minimum values in the error code digits as read reference voltages corresponding to the initial read reference voltages. And recording the difference value between the read reference voltage and each initial read reference voltage to the rereading table. Processor 120 may be a central processing unit CPU, or application specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement embodiments of the present application.
The memory 110 is used for executable instructions. Memory 110 may comprise high-speed RAM memory or may comprise non-volatile memory, such as at least one disk memory. Memory 110 may also be a memory array. The memory 110 may also be partitioned and the blocks may be combined into virtual volumes according to certain rules. The instructions stored by the memory 110 may be executable by the processor 120 to enable the processor 120 to perform the methods of any of the embodiments described above.
Referring to fig. 6, fig. 6 is a schematic structural diagram of an embodiment of a computer readable storage medium provided in the present application. The computer readable storage medium 300 has stored thereon a computer program 301, which when executed by a processor, implements the method steps provided herein. For example, the computer program 301, when executed by a processor, implements the steps of: a plurality of initial read reference voltages corresponding to one word line are obtained. Each word line of the memory device is connected with a plurality of memory cells, each memory cell comprises at least one page, and each page comprises at least one initial read reference voltage. A plurality of offset reference voltages are determined based on each initial read reference voltage. And respectively applying each offset reference voltage to the word line to obtain the error code number corresponding to each offset reference voltage. And determining offset reference voltages corresponding to minimum values or minimum values in the error code digits as read reference voltages corresponding to the initial read reference voltages. And recording the difference value between the read reference voltage and each initial read reference voltage to the rereading table. The computer-readable storage medium 300 can be any available medium or data storage device that can be accessed by a computer including, but not limited to, magnetic storage (e.g., floppy disk, hard disk, magnetic tape, magneto-optical disk (MO), etc.), optical storage (e.g., CD, DVD, BD, HVD, etc.), and semiconductor storage (e.g., ROM, EPROM, EEPROM, nonvolatile memory 110 (NANDFLASH), solid State Disk (SSD)), etc.
In summary, the method for generating a rereading table of a storage device provided in the present application provides a method for generating a rereading table of a storage device, which includes: a plurality of initial read reference voltages corresponding to one word line are obtained. Each word line of the memory device is connected with a plurality of memory cells, each memory cell comprises at least one page, and each page comprises at least one initial read reference voltage. And determining a read reference voltage corresponding to the initial read reference voltage. And recording the difference value between the read reference voltage and each initial read reference voltage to the rereading table. That is, the method for generating the re-reading table provided in this embodiment determines the read reference voltages corresponding to each page of the plurality of memory cells connected to each word line of the memory cells, that is, the read reference voltages of each page are independent from each other and do not interfere with each other when determining the read reference voltages of each page, so that the read reference voltages corresponding to the initial read reference voltages of each page can be determined conveniently and rapidly. In addition, the offset reference voltage corresponding to the minimum value or the minimum value in the plurality of error code digits is selected as the read reference voltage corresponding to the initial read reference voltage. The accuracy of the acquired read reference voltage can be improved.
The foregoing is merely specific embodiments of the present application, but the scope of protection of the present application is not limited to this, and any person skilled in the art will understand that modifications and substitutions made within the scope of the present application are included in the scope of protection of the present application, and the scope of protection of the present application should be determined by the claims.
Furthermore, in the description herein, reference to the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Claims (8)
1. A method for generating a memory device rereading table, the method comprising:
acquiring a plurality of initial read reference voltages corresponding to one word line; wherein each word line of the memory device is connected with a plurality of memory cells, each memory cell comprises at least one page, and each page comprises at least one initial read reference voltage;
determining a plurality of offset reference voltages according to each initial read reference voltage;
applying each offset reference voltage to the word line respectively to read data of a page corresponding to the initial read reference voltage in the plurality of memory cells, and finally obtaining a plurality of data of the page corresponding to the initial read reference voltage; if the page corresponding to the initial read reference voltage comprises at least two initial read reference voltages, reading the page based on the read reference voltages corresponding to other initial reference voltages when determining the read reference voltage corresponding to the current initial read reference voltage;
comparing the read data of the page corresponding to the initial read reference voltage with the read reference voltages corresponding to other initial reference voltages respectively to obtain the error number corresponding to each offset reference voltage;
determining offset reference voltages corresponding to minimum values or minimum values in a plurality of error code digits as read reference voltages corresponding to a plurality of initial read reference voltages;
and recording the difference value between the read reference voltage and each initial read reference voltage to the rereading table.
2. The method of claim 1, wherein the reading the page based on the read reference voltages corresponding to the other initial reference voltages when determining the read reference voltage corresponding to the current initial read reference voltage comprises:
and determining the data state of the page based on a coordinate interval formed by the offset reference voltage and the read reference voltages corresponding to the other initial reference voltages.
3. The method of claim 1, wherein if the page corresponding to the initial read reference voltage includes at least two initial read reference voltages, when determining the read reference voltage corresponding to the current initial read reference voltage, reading the page based on the read reference voltages corresponding to the other initial reference voltages comprises:
and if the other initial reference voltages do not have the corresponding read reference voltages, taking the other initial reference voltages as the read reference voltages corresponding to the other initial reference voltages.
4. The method of claim 2, wherein the step of determining the position of the substrate comprises,
and at least one initial read reference voltage included in each page is an ideal read reference voltage corresponding to the data state of each page under the condition that the voltage is not offset.
5. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the determining a plurality of offset reference voltages according to each of the initial read reference voltages includes:
and performing multiple offsets on the initial read reference voltage in a preset offset interval to obtain multiple offset reference voltages.
6. The method according to any one of claims 1 to 5, wherein,
the storage device is NAND FLASH memory.
7. A memory test device, characterized in that the memory test device is connected to a storage device for testing the storage device, the memory test device comprising a memory for storing program data and a processor for executing the program data for implementing the method according to any of claims 1-6.
8. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program which, when executed by a processor, implements the steps of the method according to any of claims 1-6.
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| CN110473588A (en) * | 2019-08-15 | 2019-11-19 | 山东华芯半导体有限公司 | A kind of method that on-line calibration NAND Flash reads reference voltage in SSD |
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| CN110473588A (en) * | 2019-08-15 | 2019-11-19 | 山东华芯半导体有限公司 | A kind of method that on-line calibration NAND Flash reads reference voltage in SSD |
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