CN110473588A - A kind of method that on-line calibration NAND Flash reads reference voltage in SSD - Google Patents
A kind of method that on-line calibration NAND Flash reads reference voltage in SSD Download PDFInfo
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- CN110473588A CN110473588A CN201910751725.7A CN201910751725A CN110473588A CN 110473588 A CN110473588 A CN 110473588A CN 201910751725 A CN201910751725 A CN 201910751725A CN 110473588 A CN110473588 A CN 110473588A
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- offset
- reference voltage
- nand flash
- read
- ssd
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
Abstract
The present invention discloses a kind of method that on-line calibration NAND Flash reads reference voltage in SSD, this method fully considers NAND Flash characteristic, the method read using offset, by scanning NAND Flash reference voltage online, under the premise of not influencing data content, the stability of data is improved.This method considers influence of the on-line calibration to SSD performance, and the number that setting offset is read reaches setting value there are still when check errors, by the block data-moving to new block in reading times.
Description
Technical field
The present invention relates to the calibration method that a kind of NAND Flash reads reference voltage, the online school specifically in a kind of SSD
The method that quasi- NAND Flash reads reference voltage, belongs to memory technology field.
Background technique
SSD is usually using NAND Flash as storage medium at present, however the physical structure of NAND Flash itself is special
Point determines it with natural unstability.There is probability that error in data can occur in NAND Flash reading process, and
With the development of NAND Flash technique and type, ascendant trend is presented in the probability of mistake, so nowadays NAND Flash needs
ECC algorithm error correcting capability it is more and more stronger.But ECC algorithm has been that ECC algorithm is several in the algorithm and SSD of a kind of maturation
All hardware realizations are smaller by the space for improving ECC algorithm reduction NAND Flash error probability.
Reading reference voltage is also a factor for influencing NAND Flash error probability, and reading reference voltage is in NAND
One be applied on the Control Gate of NAND Flash Cell in Flash reading process judges whether current Cell leads
Logical voltage.If reading, reference voltage is improper, also will affect the probability that mistake occurs for data.NAND Flash characteristic determines one
A reading reference voltage is not applicable in always in the different phase of NAND Flash life cycle.
Summary of the invention
The technical problem to be solved in the present invention is to provide the sides that on-line calibration NAND Flash in a kind of SSD reads reference voltage
Method reads the characteristic of adjustable reference voltage using offset, is read by using a kind of repeatedly adjustment reference voltage offset
Method obtains optimal reference voltage when current page is read, and for the read operation of the subsequent page, reduces data and mistake occurs
Accidentally probability.
In order to solve the technical problem, the technical solution adopted by the present invention is that: on-line calibration NAND in a kind of SSD
The method of Flash reading reference voltage, comprising the following steps: S01), all wordline of a certain block of NAND Flash are divided into M
Then group chooses N number of wordline from each word line group and carries out calibration voltage sampling, M, N are the positive integer greater than 1；S02), select respectively
The corresponding Lower Page of selected word line, Middle Page, Upper Page are taken, the corresponding ginseng of current page is obtained from DDR
Examine voltage Vref, then with VrefAddress D(Vref) it is that basic point successively carries out offset reading, offset spacers are set as Doffset；
S03), the data read to each offset all carry out ECC check, record the check errors rate E (n) that offset is read every time；S04),
All E (n) for comparing record find out minimum value and the corresponding offset of minimum value, by the corresponding D(V of minimum E (n)ref)+
Doffset(n)It is saved in corresponding position in DDR, Doffset(n)For the product of offset spacers and offset number.
SSD performance can be seriously affected in view of largely reading using offset, before carrying out step S02, offset is read
Number be set as i times, if the data ECC check of i reading all passes through, choose the i middle the smallest value of check errors rate
Corresponding position in DDR is recorded as new reference voltage；If occurring ECC check failure in i times, the voltage for recording failure is inclined
It moves, is then re-read i times to the opposite direction of the offset, if i ECC check is all successful, choose i middle check errors rate most
Small value is recorded in DDR, if occurring ECC check mistake in reverse read, by the block data-moving to new
block。
Further, i=5.
Further, M=4, N=4.
Further, Doffset=2。
Further, before carrying out step S01, the block for carrying out calibration voltage has write full data.
Beneficial effects of the present invention: this method fully considers NAND Flash characteristic, and the method read using offset is passed through
Online scanning NAND Flash reference voltage improves the stability of data under the premise of not influencing data content.This method
Influence in view of on-line calibration to SSD performance, the number that setting offset is read, reaching setting value in reading times, there are still schools
Error checking is mistaken, by the block data-moving to new block.
Detailed description of the invention
Fig. 1 is variation precedence diagram when reading correct；
Variation precedence diagram when Fig. 2 is read error；
Fig. 3 is the flow chart of embodiment 1.
Specific embodiment
The present invention is further illustrated in the following with reference to the drawings and specific embodiments.
Embodiment 1
NAND Flash Read operation can be divided into normal reading (normal read) and (shift read) is read in offset
Two ways, normal read only need to send Read order；Shift read needs pass through before sending Read order
The reference voltage parameter of this reading of Set Feature order setting.What reference voltage parameter represented is exactly that the current page that reads makes
Read Vref, different parameters correspond to different Vref.This method utilizes the characteristic of the adjustable reference voltage of shift read,
Optimal reference voltage when current page is read is obtained by using the method for repeatedly adjustment reference voltage shift read a kind of,
For the read operation of the subsequent page, reduces data and error probability occurs.
The present embodiment is illustrated for comprising the 2-3-2 of 256 Wordline coding 3D TLC.
Since the performance of NAND Flash characteristic is as unit of block, so all block use same calibration NAND
The method of Flash reading reference voltage.This method the following steps are included:
S01), all WL are divided into 4 groups of processing, grouping numerical value can expand or reduce according to the actual situation.From optimal
Parameter angle considers, records each WL(wordline) reference voltage parameter be most accurately that but this can bring huge DDR to account for
With it is result after equilibrium that all WL, which point are divided into 4 groups,.
S02), first WL group WL is chosengroup0, in order to guarantee the accuracy of sampling and reduce calibration process time-consuming, often
A WL group chooses 4 WL and carries out calibration voltage sampling, this 4 WL's is chosen for first WL of the groupfirst, the last one WLlast
And intermediate random two WL；
S03), read respectively and choose the corresponding Lower Page of WL, Middle Page, Upper Page, 3D used herein
Corresponding 2 V of the Lower Page of NAND Flashref, corresponding 3 V of Middle Pageref, corresponding 3 V of Upper Pageref,
Therefore VrefMAX=2 or 3, every kind of Page is to obtain the corresponding reference of current Page first using shift read mode when reading
Voltage Vref, then with current reference voltage address D (Vref) it is that basic point carries out offset reading, reference voltage parameter shift amount
Doffset(n)Be interval with 2, be followed successively by 0 ,+2, -2 ,+4, -4 ,+6, -6 ,+8, -8 ,+10, -10 ..., followed according to above-mentioned sequence
Ring completes the reading process of all WL groups；
S04), the data read to each offset all carry out ECC check, record the check errors rate E (n) that offset is read every time；
S05), all E (n) for comparing record find out minimum value and the corresponding offset of minimum value, by the corresponding D of minimum E (n)
(Vref)+Doffset(n)It is saved in corresponding position in DDR, Doffset(n)For the product of offset spacers and offset number.
In view of that largely can seriously affect SSD performance using shift read in calibration process, we use a kind of scheme:
Setting read number of maximum shift is 5 times when starting calibration, i.e., preceding No. 5 variations (0 ,+2, -2 ,+4, -4), if 5 times
The data ECC check of reading all passes through, then chooses the smallest value of error bits in 5 times and be recorded as new reference voltage
DDR corresponding position.If occurring ECC check failure in 5 times, the variation of failure is recorded, then to the opposite direction of the offset
It re-reads 5 times, if 5 ECC checks are all successful, choose the smallest value of error bits in this E (n) and be recorded in DDR.Such as
Occurs ECC check mistake in fruit reverse read, then by the block data-moving to new block.Reading order with reference to lower Fig. 1,
Fig. 2.
The detailed process that this method is realized refers to Fig. 3.
Described above is only basic principle and preferred embodiment of the invention, and those skilled in the art do according to the present invention
Improvement and replacement out, belong to the scope of protection of the present invention.
Claims (6)
1. a kind of method that on-line calibration NAND Flash reads reference voltage in SSD, it is characterised in that: the following steps are included:
S01), all wordline of a certain block of NAND Flash are divided into M group, then from each word line group choose respectively N number of wordline into
The sampling of row calibration voltage, M, N are the positive integer greater than 1；S02), choose respectively corresponding Lower Page of selected word line,
Middle Page, Upper Page obtain the corresponding reference voltage V of current page from DDRref, then with VrefAddress
D(Vref) it is that basic point successively carries out offset reading, offset spacers are set as Doffset；S03), the data each offset read all into
Row ECC check records the check errors rate E (n) that offset is read every time；S04), all E (n) for comparing record, find out minimum value
Offset corresponding with minimum value, by the corresponding D(V of minimum E (n)ref)+Doffset(n)It is saved in corresponding position in DDR,
Doffset(n)For the product of offset spacers and offset number.
2. the method that on-line calibration NAND Flash reads reference voltage in SSD according to claim 1, it is characterised in that:
Before carrying out step S02, set the number that offset is read to i times, if the data ECC check of i reading all passes through,
The i middle the smallest value of check errors rate is chosen as new reference voltage, corresponding position in DDR is recorded；If occurred in i times
ECC check failure, records the variation of failure, then re-reads i times to the opposite direction of the offset, if i ECC check
It is all successful, it chooses the smallest value of check errors rate in i times and is recorded in DDR, if occurring ECC check mistake in reverse read,
Then by the block data-moving to new block.
3. the method that on-line calibration NAND Flash reads reference voltage in SSD according to claim 2, it is characterised in that: i
=5。
4. the method that on-line calibration NAND Flash reads reference voltage in SSD according to claim 1, it is characterised in that: M
=4, N=4.
5. the method that on-line calibration NAND Flash reads reference voltage in SSD according to claim 1, it is characterised in that:
Doffset=2。
6. the method that on-line calibration NAND Flash reads reference voltage in SSD according to claim 1, it is characterised in that:
Before carrying out step S01, the block for carrying out calibration voltage has write full data.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106611607A (en) * | 2015-10-22 | 2017-05-03 | 爱思开海力士有限公司 | Reference voltage generation circuit, receiver, semiconductor apparatus and system using same |
| CN112151101A (en) * | 2020-09-18 | 2020-12-29 | 山东华芯半导体有限公司 | Method for scanning TLC NANDFlash optimal reading parameter |
| CN112527550A (en) * | 2020-11-26 | 2021-03-19 | 中山市江波龙电子有限公司 | Method for generating rereaded table of storage device, test device and storage medium |
| CN112863591A (en) * | 2021-03-22 | 2021-05-28 | 山东华芯半导体有限公司 | Test and processing method for Open Block |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1921015A (en) * | 2005-08-17 | 2007-02-28 | 赛芬半导体有限公司 | Method for reading non-volatile memory cells |
| US20090073771A1 (en) * | 2007-09-17 | 2009-03-19 | Yan Li | Non-Volatile Memory and Method for Biasing Adjacent Word Line for Verify During Programming |
| CN103380416A (en) * | 2011-02-18 | 2013-10-30 | 马维尔国际贸易有限公司 | Reliability metrics management for soft decoding |
| US8605505B2 (en) * | 2011-03-28 | 2013-12-10 | SK Hynix Inc. | Semiconductor integrated circuit and data read method |
| CN105989891A (en) * | 2015-03-20 | 2016-10-05 | Hgst荷兰有限公司 | Read level grouping for increased flash performance |
| CN205827924U (en) * | 2016-07-19 | 2016-12-21 | 北京兆易创新科技股份有限公司 | A kind of digital independent device of nonvolatile memory |
| CN106981308A (en) * | 2017-03-20 | 2017-07-25 | 记忆科技(深圳)有限公司 | A kind of application process of accurate acquisition LLR information |
-
2019
- 2019-08-15 CN CN201910751725.7A patent/CN110473588A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1921015A (en) * | 2005-08-17 | 2007-02-28 | 赛芬半导体有限公司 | Method for reading non-volatile memory cells |
| US20090073771A1 (en) * | 2007-09-17 | 2009-03-19 | Yan Li | Non-Volatile Memory and Method for Biasing Adjacent Word Line for Verify During Programming |
| CN103380416A (en) * | 2011-02-18 | 2013-10-30 | 马维尔国际贸易有限公司 | Reliability metrics management for soft decoding |
| US8605505B2 (en) * | 2011-03-28 | 2013-12-10 | SK Hynix Inc. | Semiconductor integrated circuit and data read method |
| CN105989891A (en) * | 2015-03-20 | 2016-10-05 | Hgst荷兰有限公司 | Read level grouping for increased flash performance |
| CN205827924U (en) * | 2016-07-19 | 2016-12-21 | 北京兆易创新科技股份有限公司 | A kind of digital independent device of nonvolatile memory |
| CN106981308A (en) * | 2017-03-20 | 2017-07-25 | 记忆科技(深圳)有限公司 | A kind of application process of accurate acquisition LLR information |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106611607A (en) * | 2015-10-22 | 2017-05-03 | 爱思开海力士有限公司 | Reference voltage generation circuit, receiver, semiconductor apparatus and system using same |
| CN112151101A (en) * | 2020-09-18 | 2020-12-29 | 山东华芯半导体有限公司 | Method for scanning TLC NANDFlash optimal reading parameter |
| CN112151101B (en) * | 2020-09-18 | 2023-03-14 | 山东华芯半导体有限公司 | Method for scanning TLC NANDFlash optimal reading parameters |
| CN112527550A (en) * | 2020-11-26 | 2021-03-19 | 中山市江波龙电子有限公司 | Method for generating rereaded table of storage device, test device and storage medium |
| CN112527550B (en) * | 2020-11-26 | 2023-06-30 | 中山市江波龙电子有限公司 | Method for generating rereading table of storage device, testing device and storage medium |
| CN112863591A (en) * | 2021-03-22 | 2021-05-28 | 山东华芯半导体有限公司 | Test and processing method for Open Block |
| CN112863591B (en) * | 2021-03-22 | 2024-03-22 | 山东华芯半导体有限公司 | Test and processing method for Open Block |
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