CN112511134A - Clock signal circuit for correcting high duty ratio - Google Patents

Clock signal circuit for correcting high duty ratio Download PDF

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Publication number
CN112511134A
CN112511134A CN202011433747.8A CN202011433747A CN112511134A CN 112511134 A CN112511134 A CN 112511134A CN 202011433747 A CN202011433747 A CN 202011433747A CN 112511134 A CN112511134 A CN 112511134A
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field effect
tube
control field
nmos
transistor
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CN112511134B (en
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罗婷
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Chengdu Analog Circuit Technology Inc
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Chengdu Analog Circuit Technology Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern

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  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

The invention discloses a clock signal circuit for correcting a high duty ratio, and relates to the technical field of integrated circuits. The circuit comprises a first phase inverter, a second phase inverter, a first current mirror module, a second current mirror module, a first control field effect transistor, a second control field effect transistor and a third control field effect transistor; the first phase inverter is connected to the signal input end and the second phase inverter respectively, and the second phase inverter is connected to the signal output end; the first control field effect transistor is connected with the first phase inverter, the second control field effect transistor, the third control field effect transistor, the first current mirror module and the second current mirror module; the second control field effect transistor and the third control field effect transistor are connected to the signal output end; the first current mirror module is connected to the second control field effect transistor, and the second current mirror module is connected to the third control field effect transistor. According to the technical scheme, the duty ratio of the output waveform of the signal output end is accurately controlled by controlling the magnitude of the currents of the mirror images of the first control field effect transistor and the second current mirror module.

Description

Clock signal circuit for correcting high duty ratio
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a clock signal circuit for correcting high duty ratio.
Background
In modern circuitry, the clock signal is the most commonly used signal that can be generated by either a crystal oscillator or an RC oscillator. Different circuit modules have different requirements for clock signals. For example, the analog-to-digital converter requires very small jitter of the edge of the input clock signal, the real-time clock circuit (RTC) requires very stable frequency of the input clock signal, and the Mixer (Mixer) in some rf circuits requires a non-50% duty cycle of the clock signal generated by the local oscillator, so as to achieve the purpose of increasing the conversion gain, and the frequency doubling circuit requires a 50% duty cycle of the clock signal. In the prior art, the quality of a clock signal generated by a crystal oscillator or an RC oscillator is sometimes poor, and a poor clock duty ratio exists.
Disclosure of Invention
The invention mainly aims to provide a clock signal circuit for correcting high duty ratio, aiming at accurately controlling the duty ratio of an output clock signal waveform.
In order to achieve the above object, the present invention provides a clock signal circuit for correcting a high duty ratio, the circuit including a first inverter, a second inverter, a first current mirror module, a second current mirror module, a first control fet, a second control fet, and a third control fet;
the first phase inverter is respectively connected with a signal input end and the second phase inverter, and the second phase inverter is connected with a signal output end; the first control field effect transistor is connected to the first inverter, the second control field effect transistor, the third control field effect transistor, the first current mirror module and the second current mirror module; the second control field effect transistor and the third control field effect transistor are connected to the signal output end; the first current mirror module is connected to the second control field effect transistor, and the second current mirror module is connected to the third control field effect transistor and is also connected with a first current source and a second current source;
the first phase inverter receives a clock signal and sends the clock signal after inversion to the second phase inverter, the second control field effect transistor and the third control field effect transistor respectively receive a signal output by the second phase inverter and are switched on/off according to the signal, the first current mirror module mirrors the current of a current source to the second control field effect transistor, the second current mirror module mirrors the current of the current source to the third control field effect transistor, and the duty ratio of the signal output end output signal is controlled by controlling the mirror currents of the first current mirror module and the second current mirror module;
the first control field effect transistor is connected to the second control field effect transistor and the third control field effect transistor, and the grid voltage of the first control field effect transistor is increased or decreased through the on/off of the first control field effect transistor and the second control field effect transistor to form circuit feedback.
Preferably, the first control field effect transistor is an NMOS field effect transistor; the second control field effect transistor is a PMOS field effect transistor; the third control field effect transistor is an NMOS field effect transistor.
Preferably, the drain of the first control field effect transistor is connected to the first inverter, the gate of the first control field effect transistor is connected to the drains of the second control field effect transistor and the third control field effect transistor, and the source of the first control field effect transistor is grounded; the source electrode of the second control field effect transistor is connected to the first current mirror module, the grid electrode of the second control field effect transistor is connected to the signal output end and the second phase inverter, and the drain electrode of the second control field effect transistor is connected to the first current mirror module and the second current mirror module; the grid electrode of the third control field effect transistor is connected with the signal output end and the second inverter, the source electrode of the third control field effect transistor is connected with the second current mirror module, and the drain electrode of the third control field effect transistor is connected with the first current mirror module and the second current mirror module.
Preferably, the circuit further includes a first capacitor, one end of the first capacitor is connected to a power supply, and the other end of the first capacitor is connected to the gate of the first control fet, the drain of the second control fet, and the drain of the third control fet.
Preferably, the first inverter comprises a first PMOS transistor and a first NMOS transistor, and gates of the first PMOS transistor and the first NMOS transistor are connected to each other and to the signal input terminal; the source electrode of the first PMOS tube is connected with a power supply, and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and the second phase inverter; and the source electrode of the first NMOS tube is connected to the drain electrode of the first control field effect tube.
Preferably, the second inverter comprises a second PMOS transistor and a second NMOS transistor; the grid electrodes of the second PMOS tube and the second NMOS tube are mutually connected and are connected with the drain electrodes of the first PMOS tube and the first NMOS tube; the drains of the second PMOS tube and the second NMOS tube are mutually connected and are connected with the signal output end, the grid of the second control field effect tube and the grid of the third control field effect tube; the source electrode of the second PMOS tube is connected to a power supply, and the source electrode of the second NMOS tube is grounded.
Preferably, the first current mirror includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, and a seventh PMOS transistor, gates of the third PMOS transistor, the fourth PMOS transistor, and the seventh PMOS transistor are connected to each other, a drain of the third PMOS transistor is connected to a source of the second control field effect transistor, and a drain of the fourth PMOS transistor is connected to the second current mirror module, a drain of the second control field effect transistor, and a drain of the third control field effect transistor; the source electrode of the seventh PMOS tube is connected to the power supply, and the drain electrode of the seventh PMOS tube is connected to the second current mirror module;
the grid electrodes of the fifth PMOS tube and the sixth PMOS tube are mutually connected and are connected with the drain electrodes of the second current mirror module, the second control field effect tube and the third control field effect tube; the source electrodes of the fifth PMOS tube and the sixth PMOS tube are connected to a power supply; the drain electrode of the fifth PMOS tube is connected to the source electrode of the third PMOS tube, and the drain electrode of the sixth PMOS tube is connected to the source electrode of the fourth PMOS tube.
Preferably, the second current mirror includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor;
the ninth NMOS tube is connected with a first current source, the current of the first current source is mirrored to the seventh NMOS tube, and the current is mirrored to the branch where the third NMOS tube is located through the seventh NMOS tube;
the tenth NMOS tube is connected to the second current source, mirrors the current of the second current source to the branch where the fourth NMOS tube is located, and mirrors the current to the branch where the third PMOS tube is located through the fourth PMOS tube.
Preferably, the gate of the third NMOS transistor is connected to the gates of the fourth, fifth and tenth NMOS transistors; the drain electrode of the third NMOS tube is connected with the source electrode of the third control field effect tube, and the source electrode of the third NMOS tube is connected with the drain electrode of the sixth NMOS tube;
the drain electrode of the fourth NMOS tube is connected to the first capacitor, the drain electrode of the fourth PMOS tube, the grid electrode of the first control field effect tube, the drain electrode of the second control field effect tube and the drain electrode of the third control field effect tube; the source electrode of the fourth NMOS tube is connected to the drain electrode of the seventh NMOS tube;
the drain electrode of the fifth NMOS tube is connected with the drain electrode of the seventh PMOS tube, and the source electrode of the fifth NMOS tube is connected with the drain electrode of the eighth NMOS tube;
the grid electrode of the sixth NMOS tube is connected to the grid electrodes of the seventh NMOS tube, the eighth NMOS tube and the ninth NMOS tube;
the drain electrode of the ninth NMOS tube is connected to the first current source, and the drain electrode of the tenth NMOS tube is connected to the second current source; the source electrodes of the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor and the tenth NMOS transistor are grounded.
According to the technical scheme, reference current is injected from a current source of a current source, then the first current mirror module and the second current mirror module mirror images a branch where a second control field effect transistor and a third control field effect transistor are located, and the duty ratio of the output waveform of the signal output end is accurately controlled by controlling the magnitude of currents mirrored by the first control field effect transistor and the second current mirror module.
Drawings
FIG. 1 is a circuit diagram of a circuit for correcting a clock signal with a high duty cycle according to the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The invention is further described below with reference to the accompanying drawings.
The embodiment of the invention provides a clock signal circuit for correcting a high duty ratio, which is used for adjusting an input clock signal with the high duty ratio so as to output a clock signal with the duty ratio required by a subsequent circuit.
As shown in fig. 1, the clock signal circuit for correcting a high duty ratio according to an embodiment of the present invention includes a first inverter, a second inverter, a first current mirror module, a second current mirror module, a first control fet M1, a second control fet M2, and a third control fet M3; the first phase inverter is respectively connected with a signal input end IN and the second phase inverter, and the second phase inverter is connected with a signal output end OUT; the first control FET M1 is connected to the first inverter, the second control FET M2, the third control FET M3, the first current mirror module and the second current mirror module; the second control fet M2 and the third control fet M3 are connected to the signal output terminal OUT; the first current mirror module is connected to the second control field effect transistor M2, the second current mirror module is connected to the third control field effect transistor M3, and is further connected to a first current source I1 and a second current source I2; the first inverter receives a clock signal and sends the inverted clock signal to the second inverter, the second control field effect transistor M2 and the third control field effect transistor M3 respectively receive a signal output by the second inverter and are switched on/off according to the signal, the first current mirror module mirrors the current of a current source to the second control field effect transistor M2, the second current mirror module mirrors the current of the current source to the third control field effect transistor M3, and the duty ratio of the signal output end OUT output signal is controlled by controlling the mirror currents of the first current mirror module and the second current mirror module; the first mosfet M1 is connected to the second mosfet M2 and the third mosfet M3, and the gate voltage of the first mosfet M1 is increased or decreased by turning on/off the second mosfet M2 and the third mosfet M3 to form a circuit feedback.
Specifically, as shown IN fig. 1, the signal input terminal IN inputs a clock signal with a high duty ratio, and the signal output terminal OUT outputs an adjusted clock signal. The high duty ratio clock signal enters the input end of the first inverter, and due to the high duty ratio, the time period of the input clock signal being high level is long, and the time period of the input clock signal being low level is short, so that after passing through the first inverter, the point a is discharged, the voltage of the point a is reduced, and after passing through the second inverter, the voltage of the signal output end OUT is at high level for a long time, so that the third control field effect transistor M3 is turned on. When the current of the first current mirror module branch is smaller than that of the second current mirror module branch, the voltage of the point Vcntl is decreased, so that the Gate voltage of the first control fet M1 is decreased, and the current flowing through the first control fet M1 is decreased, so that the decrease time of the point a is slower, the time that the point a is at the high level is longer, and further the low level time of the signal output end OUT is prolonged, at this time, the second control fet M2 is turned on, the voltage of the point Vcntl is increased, the Gate voltage of the first control fet M1 is increased, the current flowing through the first control fet M1 is increased, and the voltage of the point a is increased to form negative feedback.
The reference current is injected from the first current source I1 and the second current source I2, and then is mirrored to the branch where the second control fet M2 and the third control fet M3 are located by the first current mirror module and the second current mirror module. The purpose of controlling the duty ratio of the output waveform of the signal output end OUT is achieved by controlling the current magnitude of the mirror images of the first control field effect transistor M1 and the second current mirror module.
Preferably, as shown in fig. 1, the first control fet M1 is an NMOS fet; the second control field effect transistor M2 is a PMOS field effect transistor; the third control field effect transistor M3 is an NMOS field effect transistor. The drain electrode of the first control field effect transistor M1 is connected to the first inverter, the gate electrode of the first control field effect transistor M1 is connected to the drain electrode and the source electrode of the second control field effect transistor M2 and the third control field effect transistor M3 are grounded; the source electrode of the second control field effect transistor M2 is connected to the first current mirror module, the gate electrode is connected to the signal output end OUT and the second inverter, and the drain electrode is connected to the first current mirror module and the second current mirror module; the gate of the third control fet M3 is connected to the signal output terminal OUT and the second inverter, the source is connected to the second current mirror block, and the drain is connected to the first current mirror block and the second current mirror block. The rising and falling time of the clock signal waveform can be controlled by the first control field effect transistor M1.
Preferably, as shown in fig. 1, the circuit further includes a first capacitor C1, one end of the first capacitor C1 is connected to a power supply, and the other end is connected to the gate of the first mosfet M1, the drain of the second mosfet M2, and the drain of the third mosfet M3. The first capacitor C1 is used to stabilize the dot voltage at the dot B.
Preferably, as shown IN fig. 1, the first inverter includes a first PMOS transistor Mp1 and a first NMOS transistor Mn1, and gates of the first PMOS transistor Mp1 and the first NMOS transistor Mn1 are connected to each other and to the signal input terminal IN; the source electrode of the first PMOS tube Mp1 is connected with a power supply, the drain electrode of the first PMOS tube Mp1 is connected with the drain electrode of the first NMOS tube Mn1 and a second inverter; the source of the first NMOS transistor Mn1 is connected to the drain of the first control fet M1.
Preferably, as shown in fig. 1, the second inverter includes a second PMOS transistor Mp2 and a second NMOS transistor Mn 2; the gates of the second PMOS transistor Mp2 and the second NMOS transistor Mn2 are connected with each other and the drains of the first PMOS transistor Mp1 and the first NMOS transistor Mn 1; the drains of the second PMOS transistor Mp2 and the second NMOS transistor Mn2 are connected to each other and to the signal output terminal OUT, the gate of the second control fet M2, and the gate of the third control fet M3; the source electrode of the second PMOS tube Mp2 is connected to a power supply, and the source electrode of the second NMOS tube Mn2 is grounded.
Preferably, as shown in fig. 1, the first current mirror includes a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6 and a seventh PMOS transistor MP7, gates of the third PMOS transistor MP3, the fourth PMOS transistor MP4 and the seventh PMOS transistor MP7 are connected to each other, a drain of the third PMOS transistor MP3 is connected to a source of the second control field-effect transistor M2, and a drain of the fourth PMOS transistor MP4 is connected to the second current mirror module, a drain of the second control field-effect transistor M2 and a drain of the third control field-effect transistor M3; the source electrode of the seventh PMOS tube Mp7 is connected to the power supply, and the drain electrode is connected to the second current mirror module; the gates of the fifth PMOS transistor Mp5 and the sixth PMOS transistor Mp6 are connected to each other and to the drains of the second current mirror module, the second control fet M2 and the third control fet M3; the sources of the fifth PMOS tube Mp5 and the sixth PMOS tube Mp6 are connected to a power supply; the drain of the fifth PMOS transistor Mp5 is connected to the source of the third PMOS transistor MP3, and the drain of the sixth PMOS transistor Mp6 is connected to the source of the fourth PMOS transistor Mp 4. The double-layer current mirror makes the circuit more stable.
Preferably, as shown in fig. 1, the second current mirror includes a third NMOS transistor Mn3, a fourth NMOS transistor Mn4, a fifth NMOS transistor Mn5, a sixth NMOS transistor Mn6, a seventh NMOS transistor Mn7, an eighth NMOS transistor Mn8, a ninth NMOS transistor Mn9, and a tenth NMOS transistor Mn 10; the ninth NMOS transistor Mn9 is connected to the first current source I1, and mirrors the current of the first current source I1 to the seventh NMOS transistor Mn7, and mirrors the current to the branch of the third NMOS transistor Mn3 through the seventh NMOS transistor Mn 7; the tenth NMOS transistor Mn10 is connected to the second current source I2, and mirrors the current of the second current source I2 to the branch of the fourth NMOS transistor Mn4, and mirrors the current to the branch of the third PMOS transistor Mp3 through the fourth PMOS transistor Mp 4. The double-layer current mirror makes the circuit more stable.
Preferably, as shown in fig. 1, the gate of the third NMOS transistor Mn3 is connected to the gates of the fourth, fifth and tenth NMOS transistors Mn4, Mn5 and Mn 10; the drain of the third NMOS transistor Mn3 is connected to the source of the third control fet M3, and the source is connected to the drain of the sixth NMOS transistor Mn 6; the drain of the fourth NMOS transistor Mn4 is connected to the first capacitor C1, the drain of the fourth PMOS transistor Mp4, the gate of the first control fet M1, the drain of the second control fet M2 and the drain of the third control fet M3; the source electrode of the fourth NMOS transistor Mn4 is connected to the drain electrode of the seventh NMOS transistor Mn 7; the drain electrode of the fifth NMOS transistor Mn5 is connected to the drain electrode of the seventh PMOS transistor Mp7, and the source electrode of the fifth NMOS transistor Mn5 is connected to the drain electrode of the eighth NMOS transistor Mn 8; the gate of the sixth NMOS transistor Mn6 is connected to the gates of the seventh NMOS transistor Mn7, the eighth NMOS transistor Mn8 and the ninth NMOS transistor Mn 9; the drain of the ninth NMOS transistor Mn9 is connected to the first current source I1, and the drain of the tenth NMOS transistor Mn10 is connected to the second current source I2; the sources of the sixth NMOS transistor Mn6, the seventh NMOS transistor Mn7, the eighth NMOS transistor Mn8, the ninth NMOS transistor Mn9, and the tenth NMOS transistor Mn10 are grounded.
The circuit principle of the embodiment of the invention is as follows:
the clock signal with high duty ratio enters the input end of a first phase inverter composed of a first PMOS tube Mp1 and a first NMOS tube Mn1, the input clock signal is high level for a long time period and low level for a short time period, so that after passing through the first phase inverter, the discharge time of a point A is long through the first NMOS tube Mn1, the voltage of the point A is gradually reduced, and then the voltage of a signal output end OUT is in a high state for a long time through a second phase inverter composed of a second PMOS tube Mp2 and a second NMOS tube Mn 2. At this time, the third control fet M3 is turned on. When the branch current of the first current mirror module is smaller than that of the second current mirror module, the voltage of the point Vcntl is decreased, so that the Gate voltage of the first control fet M1 is decreased, and the current flowing through the first control fet M1 is decreased, so that the decrease time of the point a is slower, the time that the point a is at the high level is longer, and further the low level time of the signal output end OUT is prolonged, at this time, the second control fet M2 is turned on, the voltage of the point Vcntl is increased, the Gate voltage of the first control fet M1 is increased, the current flowing through the first control fet M1 is increased, and the voltage of the point a is increased to form negative feedback.
A third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5 and a sixth PMOS tube MP6 form a PMOS current mirror structure, a third NMOS tube Mn3, a fourth NMOS tube Mn4, a sixth NMOS tube Mn6 and a seventh NMOS tube Mn7 form an NMOS current mirror structure, reference current is injected from a first current source I1 and a second current source I2, and then the reference current is mirrored to a branch where the third PMOS tube MP3 and the third NMOS tube Mn3 are located. The branch of the seventh PMOS transistor Mp7, the fifth NMOS transistor Mn5 and the eighth NMOS transistor Mn8 provides the bias voltage required by the current mirror. Meanwhile, the gate of the first mosfet M1 is connected to the output of the inverter formed by the second mosfet M2 and the third mosfet M3. By controlling the current of the first control field effect transistor M1 and the mirror image of the current mirror module, the rising and falling time of the control voltage in each period of the clock signal can be controlled, and the purpose of accurately controlling the duty ratio of the output waveform of the signal output end OUT can be achieved.
It should be understood that the above is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent structures or equivalent flow transformations made by the present specification and drawings, or applied directly or indirectly to other related technical fields, are included in the scope of the present invention.

Claims (9)

1. A clock signal circuit for correcting high duty ratio is characterized in that the circuit comprises a first phase inverter, a second phase inverter, a first current mirror module, a second current mirror module, a first control field effect transistor, a second control field effect transistor and a third control field effect transistor;
the first phase inverter is respectively connected with a signal input end and the second phase inverter, and the second phase inverter is connected with a signal output end; the first control field effect transistor is connected to the first inverter, the second control field effect transistor, the third control field effect transistor, the first current mirror module and the second current mirror module; the second control field effect transistor and the third control field effect transistor are connected to the signal output end; the first current mirror module is connected to the second control field effect transistor, and the second current mirror module is connected to the third control field effect transistor and is also connected with a first current source and a second current source;
the first phase inverter receives a clock signal and sends the clock signal after inversion to the second phase inverter, the second control field effect transistor and the third control field effect transistor respectively receive a signal output by the second phase inverter and are switched on/off according to the signal, the first current mirror module mirrors the current of a current source to the second control field effect transistor, the second current mirror module mirrors the current of the current source to the third control field effect transistor, and the duty ratio of the signal output end output signal is controlled by controlling the mirror currents of the first current mirror module and the second current mirror module;
the first control field effect transistor is connected to the second control field effect transistor and the third control field effect transistor, and the grid voltage of the first control field effect transistor is increased or decreased through the on/off of the first control field effect transistor and the second control field effect transistor to form circuit feedback.
2. The corrected high duty cycle clock signal circuit of claim 1, wherein said first control fet is an NMOS fet;
the second control field effect transistor is a PMOS field effect transistor; the third control field effect transistor is an NMOS field effect transistor.
3. The circuit according to claim 2, wherein the drain of the first control fet is connected to the first inverter, the gate of the first control fet is connected to the drains of the second control fet and the third control fet, and the source of the first control fet is grounded;
the source electrode of the second control field effect transistor is connected to the first current mirror module, the grid electrode of the second control field effect transistor is connected to the signal output end and the second phase inverter, and the drain electrode of the second control field effect transistor is connected to the first current mirror module and the second current mirror module;
the grid electrode of the third control field effect transistor is connected with the signal output end and the second inverter, the source electrode of the third control field effect transistor is connected with the second current mirror module, and the drain electrode of the third control field effect transistor is connected with the first current mirror module and the second current mirror module.
4. The circuit according to claim 2, further comprising a first capacitor having one end connected to a power supply and the other end connected to the gate of the first fet, the drain of the second fet, and the drain of the third fet.
5. The circuit according to claim 4, wherein the first inverter comprises a first PMOS transistor and a first NMOS transistor, and gates of the first PMOS transistor and the first NMOS transistor are connected to each other and to the signal input terminal; the source electrode of the first PMOS tube is connected with a power supply, and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and the second phase inverter; and the source electrode of the first NMOS tube is connected to the drain electrode of the first control field effect tube.
6. The corrected high duty cycle clock signal circuit of claim 5, wherein said second inverter comprises a second PMOS transistor and a second NMOS transistor; the grid electrodes of the second PMOS tube and the second NMOS tube are mutually connected and are connected with the drain electrodes of the first PMOS tube and the first NMOS tube; the drains of the second PMOS tube and the second NMOS tube are mutually connected and are connected with the signal output end, the grid of the second control field effect tube and the grid of the third control field effect tube;
the source electrode of the second PMOS tube is connected to a power supply, and the source electrode of the second NMOS tube is grounded.
7. The circuit of claim 2, wherein the first current mirror comprises a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, and a seventh PMOS transistor,
the grid electrodes of the third PMOS tube, the fourth PMOS tube and the seventh PMOS tube are mutually connected, the drain electrode of the third PMOS tube is connected with the source electrode of the second control field effect tube, and the drain electrode of the fourth PMOS tube is connected with the drain electrodes of the second current mirror module, the second control field effect tube and the third control field effect tube; the source electrode of the seventh PMOS tube is connected to the power supply, and the drain electrode of the seventh PMOS tube is connected to the second current mirror module;
the grid electrodes of the fifth PMOS tube and the sixth PMOS tube are mutually connected and are connected with the drain electrodes of the second current mirror module, the second control field effect tube and the third control field effect tube; the source electrodes of the fifth PMOS tube and the sixth PMOS tube are connected to a power supply; the drain electrode of the fifth PMOS tube is connected to the source electrode of the third PMOS tube, and the drain electrode of the sixth PMOS tube is connected to the source electrode of the fourth PMOS tube.
8. The circuit of claim 7, wherein the second current mirror comprises a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor;
the ninth NMOS tube is connected with a first current source, the current of the first current source is mirrored to the seventh NMOS tube, and the current is mirrored to the branch where the third NMOS tube is located through the seventh NMOS tube;
the tenth NMOS tube is connected to the second current source, mirrors the current of the second current source to the branch where the fourth NMOS tube is located, and mirrors the current to the branch where the third PMOS tube is located through the fourth PMOS tube.
9. The corrected high duty cycle clock signal circuit of claim 8, wherein the gate of the third NMOS transistor is connected to the gates of the fourth, fifth and tenth NMOS transistors; the drain electrode of the third NMOS tube is connected with the source electrode of the third control field effect tube, and the source electrode of the third NMOS tube is connected with the drain electrode of the sixth NMOS tube;
the drain electrode of the fourth NMOS tube is connected to the first capacitor, the drain electrode of the fourth PMOS tube, the grid electrode of the first control field effect tube, the drain electrode of the second control field effect tube and the drain electrode of the third control field effect tube; the source electrode of the fourth NMOS tube is connected to the drain electrode of the seventh NMOS tube;
the drain electrode of the fifth NMOS tube is connected with the drain electrode of the seventh PMOS tube, and the source electrode of the fifth NMOS tube is connected with the drain electrode of the eighth NMOS tube;
the grid electrode of the sixth NMOS tube is connected to the grid electrodes of the seventh NMOS tube, the eighth NMOS tube and the ninth NMOS tube;
the drain electrode of the ninth NMOS tube is connected to the first current source, and the drain electrode of the tenth NMOS tube is connected to the second current source; the source electrodes of the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor and the tenth NMOS transistor are grounded.
CN202011433747.8A 2020-12-10 2020-12-10 Clock signal circuit for correcting high duty ratio Active CN112511134B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5164621A (en) * 1990-11-06 1992-11-17 Mitsubishi Denki Kabushiki Kaisha Delay device including generator compensating for power supply fluctuations
US6262616B1 (en) * 1999-10-08 2001-07-17 Cirrus Logic, Inc. Open loop supply independent digital/logic delay circuit
CN102594299A (en) * 2012-02-03 2012-07-18 深圳创维－Rgb电子有限公司 Square-wave generator circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5164621A (en) * 1990-11-06 1992-11-17 Mitsubishi Denki Kabushiki Kaisha Delay device including generator compensating for power supply fluctuations
US6262616B1 (en) * 1999-10-08 2001-07-17 Cirrus Logic, Inc. Open loop supply independent digital/logic delay circuit
CN102594299A (en) * 2012-02-03 2012-07-18 深圳创维－Rgb电子有限公司 Square-wave generator circuit

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