CN112511120B

CN112511120B - Hall sensor reading circuit and electronic equipment

Info

Publication number: CN112511120B
Application number: CN202011288726.1A
Authority: CN
Inventors: 陈岚
Original assignee: Shenzhen Qiuyu Electronic Co
Current assignee: Shenzhen Qiuyu Electronic Co
Priority date: 2020-11-17
Filing date: 2020-11-17
Publication date: 2024-03-01
Anticipated expiration: 2040-11-17
Also published as: CN112511120A

Abstract

The invention provides a Hall sensor reading circuit and electronic equipment, wherein the circuit mainly comprises a two-phase rotating current control circuit, a chopper modulation demodulation circuit, a linear transconductance operational amplifier OTA, a gain-adjustable GM-C integrator, a low-pass filter LPF, a magnetic field direction control circuit and an offset voltage-adjustable subtracting method module, can effectively amplify the output signal of a Hall sensor with high precision, and eliminates offset voltage and interference noise in the output signal of the Hall sensor.

Description

Hall sensor reading circuit and electronic equipment

Technical Field

The invention relates to the technical field of electronic circuits, in particular to a low-noise low-offset linear Hall sensor reading circuit and electronic equipment.

Background

With the development of the fifth generation mobile communication, the development of the aircraft and the automobile industry and the development of new materials, the integrated circuit hall sensor has wide application in non-contact detection change and automatic control systems of physical quantities such as magnetic fields, pressures, positions, displacements, speeds, accelerations, angles, angular velocities, currents and the like. However, in the automotive application field of high precision, high reliability, strict index, such as: the system has the advantages that the system is high in index requirement on the performance of the linear Hall sensor, such as low in imbalance, low in noise, high in reliability, high in sensitivity and the like.

The Hall sensor manufactured based on BiCMOS (Bipolar and CMOS) and BCD (Bipolar, CMOS and DMOS) processes has good compatibility, and the low temperature drift and the high noise resistance of the Hall sensor are realized by adopting a shallow trench isolation process technology (STI process). However, the voltage signal generated by the hall sensor is very weak, and is generally between hundreds of microvolts and several millivolts, and a series of factors such as ambient working temperature, electron hole mobility, design geometric factors, manufacturing process defects, packaging mechanical stress, injection concentration, device mismatch, mask dislocation, crystal face dislocation and the like are added, so that the hall voltage signal is mixed with offset voltage and noise, and in addition, non-ideal factors such as offset voltage, thermal noise, flicker noise and the like introduced by a hall sensor reading circuit are added, so that the weak hall voltage signal cannot be read correctly. Therefore, the readout circuit is required to have not only a high-precision signal amplifying capability but also an ability to eliminate offset voltage and interference noise.

Disclosure of Invention

In view of the above, the embodiment of the invention provides a hall sensor readout circuit and an electronic device, so as to realize high-precision amplification of a hall sensor output signal and eliminate offset voltage and interference noise in the hall sensor output signal.

In order to achieve the above object, the embodiment of the present invention provides the following technical solutions:

a hall sensor readout circuit comprising:

the input end of the two-phase rotating current control circuit is connected with the output end of the target Hall sensor;

the input end of the chopper modulation circuit is connected with the output end of the target Hall sensor;

the input end of the low-pass filter is connected with the output end of the chopper modulation circuit;

the input end of the magnetic field direction control circuit is connected with the output end of the low-pass filter;

the input end of the offset voltage-adjustable subtracting device is connected with the output end of the magnetic field direction control circuit;

the chopper modulation circuit comprises a modulation circuit and a demodulation circuit, wherein the input end of the modulation circuit is used as the input end of the chopper modulation circuit, and the output end of the demodulation circuit is used as the output end of the chopper modulation circuit;

the hall sensor readout circuit further includes:

the linear transconductance operational amplifier, the gain-adjustable GM-C integrator and the first source follower are sequentially connected in series between the output end of the modulation circuit and the input end of the demodulation circuit.

Optionally, in the above hall sensor readout circuit, the two-phase rotating current control circuit is configured to:

based on a variation period of a preset clock signal, a hall bias current of orthogonal rotation from 0 degrees to 90 degrees is generated and supplied to the hall element.

Optionally, in the above hall sensor readout circuit, the two-phase rotation current control circuit includes:

the first input end of the first constant current source is connected with an external power supply;

the input end of the first clock signal switch and the input end of the second clock signal switch are connected with the output end of the first constant current source, the output end of the first clock signal switch is connected with a first input interface of the Hall sensor, and the output end of the second clock signal switch is connected with a second input interface of the Hall sensor; the switching state of the first clock signal switch is controlled by a first clock signal, and the switching state of the second clock signal switch is controlled by a second clock signal;

the input end of the third clock signal switch is connected with the output end of the first clock signal switch, and the input end of the fourth clock signal switch is connected with the output end of the second clock signal switch; the switching state of the third clock signal switch is controlled by the first clock signal, and the switching state of the fourth clock signal switch is controlled by the second clock signal;

The first input end of the operational amplifier is connected with the output ends of the third clock signal switch and the fourth clock signal switch, the second input end of the operational amplifier inputs a reference voltage, and the output end of the operational amplifier is connected with the second input end of the first constant current source;

the output end of the fifth clock signal switch is connected with the first output interface of the Hall sensor, the output end of the sixth clock signal switch is connected with the second output interface of the Hall sensor, the switching state of the fifth clock signal switch is controlled by the first clock signal, and the switching state of the sixth clock signal switch is controlled by the second clock signal.

Optionally, in the hall sensor readout circuit, the modulation circuit includes:

the input end of the first modulation clock switch is connected with the second input end of the Hall sensor, the input end of the second modulation clock switch is connected with the first input end of the Hall sensor, the input end of the third modulation clock switch is connected with the first output end of the Hall sensor, the input end of the fourth modulation clock switch is connected with the second output end of the Hall sensor, the input ends of the first modulation clock switch, the second modulation clock switch, the third modulation clock switch and the fourth modulation clock switch are used as the input ends of the modulation circuit, the output ends of the first modulation clock switch and the second modulation clock switch are used as the first output ends of the modulation circuit, and the output ends of the third modulation clock switch and the fourth modulation clock switch are used as the second output ends of the modulation circuit;

The first input end of the self-zeroing clock switch is connected with the output ends of the first modulation clock switch and the second modulation clock switch, and the second input end of the self-zeroing clock switch is connected with the output ends of the third modulation clock switch and the fourth modulation clock switch;

the input end of the first capacitor is connected with the output end of the self-zeroing clock switch, and the output end of the first capacitor is grounded.

Optionally, in the hall sensor readout circuit, the demodulation circuit includes:

the first and second RC filter circuits are connected with the first and second demodulation clock switches respectively;

the input ends of the first dummy tube unit and the second dummy tube unit are used as the input ends of the demodulation circuit, the output end of the first dummy tube unit is connected with the input end of the first demodulation clock switch, and the output end of the second dummy tube unit is connected with the input end of the second demodulation clock switch;

the output ends of the third dummy tube unit and the fourth dummy tube unit are used as the output ends of the demodulation circuit, the input end of the third dummy tube unit is connected with the output end of the first demodulation clock switch, and the input end of the fourth dummy tube unit is connected with the output end of the second demodulation clock switch;

The first RC filter circuit is used for filtering signals output by the output end of the third dummy tube unit, and the second RC filter circuit is used for filtering signals output by the output end of the fourth dummy tube unit.

Optionally, in the readout circuit of a hall sensor, the linear transconductance operational amplifier includes:

the control end of the first MOS tube is connected with the first output end of the modulation circuit, and the control end of the second MOS tube is connected with the second output end of the modulation circuit;

the second constant current source is connected with the input end of the first MOS tube, and the third constant current source is connected with the input end of the second MOS tube;

the first end of the source degeneration resistor is connected with the input end of the first MOS tube, and the second end of the source degeneration resistor is connected with the input end of the second MOS tube;

the first input end of the second source follower is connected with the output end of the first MOS tube, the second end input of the second source follower is connected with the output end of the second MOS tube, the first output end of the second source follower is used as the first output end of the linear transconductance operational amplifier, and the second output end of the second source follower is used as the second output end of the linear transconductance operational amplifier;

The first input end of the negative transconductance is connected with the first output end of the second source follower, the second input end of the negative transconductance is connected with the second output end of the second source follower, the first output end of the negative transconductance is connected with the input end of the first MOS tube, and the second output end of the negative transconductance is connected with the input end of the second MOS tube;

the first input end of the fourth constant current source is connected with the output end of the first MOS tube, the first input end of the fifth constant current source is connected with the output end of the second MOS tube, and the output ends of the fourth constant current source and the fifth constant current source are grounded;

the first input end of the first error amplifier is used for acquiring a common mode feedback signal, the second input end of the first error amplifier is used for acquiring a first reference signal, and the output end of the first error amplifier is connected with the second input ends of the fourth constant current source and the fifth constant current source;

the second capacitor is arranged between the first input end of the fourth constant current source and the output end of the first error amplifier, and the third capacitor is arranged between the first input end of the fifth constant current source and the output end of the first error amplifier.

Optionally, in the above hall sensor readout circuit, the gain-adjustable GM-C integrator includes:

the control end of the third MOS tube is connected with the first output end of the modulation circuit, and the control end of the fourth MOS tube is connected with the second output end of the modulation circuit;

the control end of the fifth MOS tube and the control end of the sixth MOS tube are used for inputting preset signals, the output end of the fifth MOS tube is connected with the input end of the third MOS tube, and the output end of the sixth MOS tube is connected with the input end of the fourth MOS tube;

the first output end of the seventh constant current source is connected with the input end of the gain-adjustable GM-C integrator, and the output end of the seventh constant current source is used as the second output end of the gain-adjustable GM-C integrator;

the first resistor and the second resistor are connected in series between the output ends of the sixth constant current source and the seventh constant current source;

The first input end of the second error amplifier is connected with the common end of the first resistor and the second resistor and used for acquiring the common mode feedback signal, the second input end of the second error amplifier is used for acquiring a second reference signal, and the second output end of the second error amplifier is connected with the second input ends of the sixth constant current source and the seventh constant current source;

an eighth direct current source, wherein the input end of the eighth direct current source is connected with the output ends of the third MOS tube and the fourth MOS tube, and the output end of the eighth direct current source is grounded;

and the output end of the first gain device is connected with the input end of the eighth direct current source.

Optionally, in the above hall sensor readout circuit, the magnetic field direction control circuit includes:

the input end of the third source follower is used as the input end of the magnetic field direction control circuit;

the first end of the first direction control switch is connected with the first output end of the third source follower, the first end of the second direction control switch is connected with the second output end of the third source follower, the first end of the third direction control switch is connected with the second end of the second direction control switch, the second end of the third direction control switch is connected with the first end of the first direction control switch, the first end of the fourth direction control switch is connected with the first end of the second direction control switch, and the second end of the fourth direction control switch is connected with the second end of the first direction control switch;

The first input end of the fourth source follower is connected with the second end of the first direction control switch, the second input end of the fourth source follower is connected with the second end of the second direction control switch, and the output end of the third source follower is used as the output end of the magnetic field direction control circuit.

Optionally, in the above hall sensor readout circuit, the offset voltage adjustable subtracting method includes:

the input end of the first operational amplifier is used as the input end of the offset voltage adjustable subtracting device, and the output end of the operational amplifier is used as the output end of the offset voltage adjustable subtracting device;

a second operational amplifier, a first input end of which is used for inputting a third reference signal,

the output end of the offset voltage fine adjuster is connected with the second input end of the second operational amplifier;

the first end of the voltage dividing circuit is connected with the inverting input end of the first operational amplifier, the second end of the voltage dividing circuit is connected with the output end of the second operational amplifier, and the third end of the voltage dividing circuit is connected with the output end of the offset voltage fine regulator.

An electronic device employing a hall sensor readout circuit as claimed in any one of the preceding claims.

Based on the above technical scheme, the circuit provided by the embodiment of the invention mainly comprises a two-phase rotating current control circuit, a chopper modulation demodulation circuit, a linear transconductance operational amplifier OTA, a gain adjustable GM-C integrator, a low pass filter LPF, a magnetic field direction control circuit, an offset voltage adjustable subtracting method and other modules. By adopting the two-phase rotating current technology and the chopping dynamic offset elimination technology, offset voltage signals and flicker noise can be effectively eliminated. Meanwhile, OTA (transconductance amplifier) with high linearity, low offset and low noise is introduced as a first stage of amplification of the detection circuit, so that the input linear range of the detection circuit is effectively improved; a GM-C integrator (transconductance-capacitance integrator) with high gain, wide bandwidth and low offset is introduced as a second stage of amplification of the detection circuit, so that useful signals are effectively amplified, and useless higher harmonic signals are filtered out. In addition, a double-channel time-sharing sampling technology is adopted to sample positive Hall voltage signals and negative Hall voltage signals in a time-sharing mode, and a subtracter is utilized to obtain linearly amplified Hall voltage signals, so that high-precision amplification of output signals of the Hall sensor is realized, and offset voltage and interference noise can be eliminated.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a readout circuit of a hall sensor according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a two-phase rotating current control circuit in a Hall sensor readout circuit according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a modulation circuit in a readout circuit of a hall sensor according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a chopper modulation circuit in a hall sensor readout circuit disclosed in an embodiment of the present application;

fig. 5 is a schematic structural diagram of a linear transconductance operational amplifier OTA in a hall sensor readout circuit disclosed in an embodiment of the present application;

FIG. 6 is a schematic diagram of a gain-adjustable GM-C integrator in a readout circuit of a Hall sensor according to an embodiment of the present disclosure;

Fig. 7 is a schematic structural diagram of a first GAIN amplifier GAIN-TRIM according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a magnetic field direction control circuit in a Hall sensor readout circuit according to an embodiment of the present disclosure;

FIG. 9 is a schematic diagram of a third source follower disclosed in an embodiment of the present application;

fig. 10 is a schematic structural diagram of a fourth source follower disclosed in an embodiment of the present application;

fig. 11 is a schematic structural diagram of an offset voltage adjustable subtracting device in a readout circuit of a hall sensor according to an embodiment of the present disclosure;

fig. 12 is a schematic structural diagram of OFFSET voltage trimming device offset_trim according to an embodiment of the present disclosure;

FIG. 13 is a schematic diagram of a Hall sensor readout circuit according to another embodiment of the present disclosure;

FIG. 14 is a control timing diagram of a clock control signal in a Hall sensor read-out circuit;

fig. 15 is a waveform diagram of key signal transients in a hall sensor readout circuit.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Compared with the traditional amplifier, the low-noise low-offset chopper operational amplifier is a better choice. The chopper dynamic offset eliminating technology is one continuous time method and aims at eliminating offset voltage of Hall element caused by heat stress and mechanical pressure of temperature change.

Referring to fig. 1, a hall sensor readout circuit disclosed in an embodiment of the present application may include:

the circuit comprises a two-phase rotating current control circuit 100, a chopper modulation circuit, a low-pass filter LPF, a magnetic field direction control circuit 300, an offset voltage adjustable subtraction device 400, a linear transconductance operational amplifier OTA, a gain adjustable GM-C integrator 500 and a first source follower 600, wherein the first source follower 600 is a double-end-to-single-end source follower, and A=0.5;

the input end of the two-phase rotating current control circuit 100 is connected with the output end of the target Hall sensor;

the input end of the low-pass filter LPF is connected with the output end of the chopper modulation circuit;

the input end of the magnetic field direction control circuit 300 is connected with the output end of the low-pass filter LPF;

the input end of the offset voltage adjustable subtracting device 400 is connected with the output end of the magnetic field direction control circuit 300;

the chopper modulation circuit comprises a modulation circuit 201 and a demodulation circuit 202, wherein the input end of the modulation circuit is used as the input end of the chopper modulation circuit, and the output end of the demodulation circuit is used as the output end of the chopper modulation circuit;

the linear transconductance operational amplifier OTA, the gain-adjustable GM-C integrator 500 and the first source follower 600 are sequentially connected in series between the output end of the modulation circuit and the input end of the demodulation circuit.

As can be seen from the above embodiments, the readout circuit of the linear hall sensor disclosed in the embodiments of the present application mainly comprises two-phase rotating current control circuit 100, chopper modulation and demodulation circuit, linear transconductance operational amplifier OTA, gain adjustable GM-C integrator 500, low pass filter LPF, magnetic field direction control circuit 300, offset voltage adjustable subtracting method 400, and other modules. By adopting the two-phase rotating current technology and the chopping dynamic offset elimination technology, offset voltage signals and flicker noise can be effectively eliminated. Meanwhile, a linear transconductance operational amplifier OTA with high linearity, low offset and low noise is introduced as a first-stage amplification of the circuit, so that the input linear range of the circuit is effectively improved; the gain-adjustable GM-C integrator 500 with high gain, wide bandwidth and low offset is introduced as a second stage of amplification of the circuit, effectively amplifying the useful signal and filtering out unwanted higher harmonic signals. In addition, the two-phase rotating current control circuit 100 adopts a two-channel time-sharing sampling technology to sample the positive hall voltage signal and the negative hall voltage signal in a time-sharing manner, and the offset voltage-adjustable subtracting device 400 is utilized to obtain the linearly amplified hall voltage signal, so that the high-precision amplification of the output signal of the hall sensor is realized, and the offset voltage and the interference noise can be eliminated.

In the technical solution disclosed in the embodiments of the present application, the two-phase rotating current control circuit 100 is configured to: based on a variation period of a preset clock signal, a hall bias current of orthogonal rotation from 0 degrees to 90 degrees is generated and supplied to the hall element. In addition, the present application further discloses a schematic structural diagram of each circuit module in the readout circuit of the hall sensor, for example, referring to fig. 2, the two-phase rotating current control circuit 100 disclosed in the embodiments of the present application may include:

a first constant current source I1, wherein a first input end of the first constant current source I1 is connected with an external power supply VDD;

the input end of the first clock signal switch S1 and the input end of the second clock signal switch S2 are connected with the output end of the first constant current source I1, the output end of the first clock signal switch S1 is connected with a first input interface of the Hall sensor, and the output end of the second clock signal switch S2 is connected with a second input interface of the Hall sensor; the switching state of the first clock signal switch S1 is controlled by a first clock signal CLK+, and the switching state of the second clock signal switch S2 is controlled by a second clock signal CLK-;

A third clock signal switch S3 and a fourth clock signal switch S4, wherein an input end of the third clock signal switch S3 is connected to an output end of the first clock signal switch S1, and an input end of the fourth clock signal switch S4 is connected to an output end of the second clock signal switch S2; the switch state of the third clock signal switch S3 is controlled by the first clock signal CLK+, and the switch state of the fourth clock signal switch S4 is controlled by the second clock signal CLK-;

the first input end of the operational amplifier U1 is connected with the output ends of the third clock signal switch S3 and the fourth clock signal switch S4, the second input end of the operational amplifier U1 is input with a reference voltage VREF1, the output end of the operational amplifier U1 is connected with the second input end of the first constant current source I1, the reference voltage is off-chip bias reference voltage, when the operational amplifier U1 is used, the static output voltage of the linear Hall sensor and the off-chip bias reference voltage can be set to be in a 50% proportion relation, and the Hall bias current can be adjusted in proportion through the off-chip bias reference voltage;

the output end of the fifth clock signal switch S5 is connected with the first output interface of the Hall sensor, the output end of the sixth clock signal switch S6 is connected with the second output interface of the Hall sensor, the switching state of the fifth clock signal switch S5 is controlled by the first clock signal CLK+ and the switching state of the sixth clock signal switch S6 is controlled by the second clock signal CLK-.

The magnitude of the hall bias current provided by the two-phase rotating current control circuit 100 to the hall sensor can be adjusted proportionally by the off-chip bias reference voltage, and the direction of the hall bias current can be controlled to realize orthogonal rotation of 0 degrees and 90 degrees by a first clock signal clk+ and a second clock signal CLK-which are complementary with a preset frequency (for example, 200 KHZ).

In the above circuit, when the first clock signal clk+ is active, the switches S1, S3, S5 are closed, the hall bias current passes through the hall device in the direction D, B of the hall sensor, and the A, C terminal of the hall sensor is a positive hall voltage signal:

+Vhall＝VA-VC＝+ΔV+Vhall_os

(3-1)

in the above circuit, when the second clock signal CLK-is active, the switches S2, S4, S6 are closed, the hall bias current flows through the hall device in the direction A, C, and the D, B terminal is a negative hall voltage signal:

-Vhall＝VD-VB＝-ΔV+Vhall_os (3-2)

and then subtracting the equation 3-1 from the equation 3-2 through a subtracter, so as to obtain a final Hall voltage signal: vhall=Δv (3-3)

Wherein, deltaV is the generated Hall voltage signal, and Vhall_os is the offset voltage of the Hall device. When the clock signal is periodically changed, the direction of the Hall bias current is orthogonally rotated from 0 degrees to 90 degrees, a positive Hall voltage signal, a negative Hall voltage signal and an offset voltage Vhall_os with the polarity unchanged all the time are generated, and then offset voltage of the Hall device is eliminated through a subtracter.

Referring to fig. 3, the modulation circuit 201 may include:

the input end of the first modulation clock switch CH1 is connected with the second input end of the Hall sensor, the input end of the second modulation clock switch CH2 is connected with the first input end of the Hall sensor, the input end of the third modulation clock switch CH3 is connected with the first output end of the Hall sensor, the input end of the fourth modulation clock switch CH4 is connected with the second output end of the Hall sensor, the input ends of the first modulation clock switch CH1, the second modulation clock switch CH2, the third modulation clock switch CH3 and the fourth modulation clock switch CH4 serve as the input ends of the modulation circuit, the output ends of the first modulation clock switch CH1 and the second modulation clock switch CH2 serve as the first output ends of the modulation circuit, and the output ends of the third modulation clock switch CH3 and the fourth modulation clock switch CH4 serve as the output ends of the modulation circuit;

the first input end of the self-zeroing clock switch CLK_ZERO is connected with the output ends of the first modulation clock switch CH1 and the second modulation clock switch CH2, and the second input end of the self-zeroing clock switch CLK_ZERO is connected with the output ends of the third modulation clock switch CH3 and the fourth modulation clock switch CH 4;

The input end of the first capacitor C1 is connected with the output end of the self-zeroing clock switch CLK_ZERO, and the output end of the first capacitor C1 is grounded.

Referring to fig. 3, the demodulation circuit includes:

the first DUMMY pipe unit DUMMY1, the second DUMMY pipe unit DUMMY2, the third DUMMY pipe unit DUMMY3, the fourth DUMMY pipe unit DUMMY4, the first demodulation clock switch CH5, the second demodulation clock switch CH6, the first RC filter circuit and the second RC filter circuit;

the input ends of the first DUMMY tube unit DUMMY1 and the second DUMMY tube unit DUMMY2 are used as the input ends of the demodulation circuit, the output end of the first DUMMY tube unit DUMMY1 is connected with the input end of the first demodulation clock switch CH5, and the output end of the second DUMMY tube unit DUMMY2 is connected with the input end of the second demodulation clock switch CH 6;

the output ends of the third DUMMY single DUMMY3 element and the fourth DUMMY unit DUMMY4 serve as the output ends of the demodulation circuit, the input end of the third DUMMY single DUMMY3 element is connected with the output end of the first demodulation clock switch CH5, and the input end of the fourth DUMMY unit DUMMY4 is connected with the output end of the second demodulation clock switch CH 6;

the first RC filter circuit is configured to filter a signal output by the output end of the third DUMMY unit DUMMY3 element, and the second RC filter circuit is configured to filter a signal output by the output end of the fourth DUMMY unit DUMMY4, see fig. 4, and the RC filter circuit is configured of a capacitor and a resistor connected in parallel.

Specifically, the structure diagram of the demodulation circuit is shown in fig. 4, the conducting states of the NMOS pipes in the first DUMMY pipe unit DUMMY1, the second DUMMY pipe unit DUMMY2, the third DUMMY pipe unit DUMMY3, the fourth DUMMY pipe unit DUMMY4, the first demodulation clock switch CH5, and the second demodulation clock switch CH6 are formed by one NMOS pipe and one PMOS pipe, where the conducting states of the NMOS pipes in the first DUMMY pipe unit DUMMY1, the second DUMMY pipe unit DUMMY2, the third DUMMY pipe unit DUMMY3, and the fourth DUMMY pipe unit DUMMY4 are identical to the conducting states of the PMOS pipes in the first demodulation clock switch CH5 and the second demodulation clock switch CH6, and the conducting states of the PMOS pipes in the first DUMMY pipe unit DUMMY1, the second DUMMY pipe unit DUMMY2, the third DUMMY pipe unit DUMMY3, and the fourth DUMMY pipe unit DUMMY 6 are identical to the conducting states of the NMOS pipes in the first demodulation clock switch CH5 and the second demodulation clock switch CH6, where the first DUMMY pipe unit DUMMY3, the second DUMMY pipe unit DUMMY4 are controlled by the first DUMMY pipe unit DUMMY circuit 4, the second DUMMY pipe unit DUMMY4, and the fourth DUMMY pipe unit DUMMY pipe 4.

Referring to fig. 3 and 4, in order to reduce the charge injection effect of the MOS switch, the chopper modem circuit of the present invention introduces four techniques on the basis of a conventional chopper:

(1) The DUMMY transistor unit is introduced, the DUMMY transistor unit is composed of an NMOS transistor and a PMOS transistor in a source-drain short circuit mode and is controlled by a complementary clock of a switching transistor, after a demodulation clock switch is disconnected, the DUMMY transistor unit of a corresponding branch circuit is conducted, channel charges are injected into the DUMMY transistor units on two sides, isolation between the switching transistor and an input capacitor of a rear-stage operational amplifier is realized, and therefore charge injection to the input capacitor of the rear-stage operational amplifier is reduced, charge injection mismatch is reduced, and a clock feedthrough effect is inhibited.

(2) The combination of NMOS and PMOS devices allows opposite amounts of charge to be injected into each other by the two channels. As long as the injected charges of NMOS and PMOS are guaranteed to be equal, namely:

WnLn (Vck-Vin-Vthn) =WpLp (Vck-Vin-Vthp) can exactly cancel the opposite charge.

(3) Differential operation is utilized to reduce charge injection. Using a differential sampling circuit, two differential signals of equal amplitude and opposite directions are generated, and when vjn1=vjn2, the amount of charge is eliminated, and in addition, the structure can eliminate fixed offset and reduce nonlinear components.

(4) Input offset storage techniques. When the modulation clock (marked as CH 1) for controlling the first modulation clock switch and the third modulation clock switch, the clock signal (marked as CH 2) for controlling the second modulation clock switch and the fourth modulation clock switch and the clock signal (marked as CH 5) for controlling the first demodulation clock switch and the clock signal (marked as CH 6) for controlling the second demodulation clock switch are all disconnected, the self-regulating clock CLK_ZERO is enabled, the switch CLK_ZERO is closed and stores the input offset voltage of the operational amplifier and the residual offset voltage caused by a switching tube, and when the chopper works, the chopper is modulated to a high-frequency end and filtered by using a low-pass filter LPF of a later stage, so that the aim of eliminating charge injection mismatch is achieved.

Referring to fig. 5, the linear transconductance operational amplifier OTA includes:

the control end of the first MOS tube M1 is connected with the first output end of the modulation circuit, and the control end of the second MOS tube M2 is connected with the second output end of the modulation circuit;

the second constant current source I2 and the third constant current source I3, the second constant current source I2 is connected with the input end of the first MOS tube M1, and the third constant current source I3 is connected with the input end of the second MOS tube M2;

the first end of the source degeneration resistor R0 is connected with the input end of the first MOS tube M1, and the second end of the source degeneration resistor R0 is connected with the input end of the second MOS tube M2;

the first input end of the second source follower A1 is connected with the output end of the first MOS tube M1, the second input end of the second source follower A1 is connected with the output end of the second MOS tube M2, the first output end of the second source follower A1 is used as the first output end of the linear transconductance operational amplifier OTA, and the second output end of the second source follower A1 is used as the second output end of the linear transconductance operational amplifier OTA;

a first input end of the negative transconductance-GM is connected with a first output end of the second source follower A1, a second input end of the negative transconductance-GM is connected with a second output end of the second source follower A1, a first output end of the negative transconductance-GM is connected with an input end of the first MOS tube M1, and a second output end of the negative transconductance-GM is connected with an input end of the second MOS tube M2;

A first input end of the fourth constant current source I4 is connected with an output end of the first MOS tube M1, a first input end of the fifth constant current source I5 is connected with an output end of the second MOS tube M2, and output ends of the fourth constant current source I4 and the fifth constant current source I5 are grounded;

a first error amplifier U2, wherein a first input end of the first error amplifier U2 is used for obtaining a common mode feedback signal, a second input end of the first error amplifier U2 is used for obtaining a first reference signal VREF2, and an output end of the first error amplifier is connected with the second input ends of the fourth constant current source I4 and the fifth constant current source;

the second capacitor C2 and the third capacitor C3, the second capacitor C2 is arranged between the first input end of the fourth constant current source I4 and the output end of the first error amplifier, and the third capacitor C3 is arranged between the first input end of the fifth constant current source I5 and the output end of the first error amplifier.

Referring to fig. 5, the circuit structure of the linear transconductance operational amplifier OTA mainly comprises a PNP input differential pair tube (composed of a first MOS tube and a second MOS tube), a source follower A1, a negative transconductance-GM circuit, and an error amplifier U2, wherein a common-mode feedback signal CMFB is provided by a tail current source common-mode signal of a gain-adjustable GM-C integrator. Because the hall sensor signal is basically in a low frequency band, the signal amplitude is tiny, and is generally between hundreds of microvolts and a few millivolts, offset voltage and flicker noise of a back-end circuit become the most important factors influencing the amplification of the hall voltage signal. Meanwhile, as the process node of the integrated circuit is lower, the noise and offset performance of the linear transconductance operational amplifier OTA at the first stage of the circuit is more key to determining the success or failure of the whole detection amplifying circuit in the face of the reduction of the power supply voltage, the aggravation of flicker noise and the increase of offset voltage. Therefore, the invention introduces three technologies based on the traditional operational transconductance amplifier OTA to reduce offset voltage and flicker noise.

(1) The first MOS tube and the second MOS tube can be PNP tubes, namely PNP MOS tubes are adopted as differential input pair tubes. Because the Hall voltage signal is lower, PNP transistor is selected as input pair tube, and in addition, PNP transistor has better matching property than NPN transistor, lower introduced offset and smaller flicker noise.

(2) The addition of the emitter degeneration resistor R0, while the two tail current sources (the second constant current source I2 and the third constant current source I3) introduce some differential error, subject the output to higher noise (and offset voltage), increases exponentially for the trade-off linearity, which is acceptable.

(3) A negative transconductance-GM circuit is added. In order to reduce the influence of noise and offset voltage, the invention provides an improved emitter degeneration linearization technology, as shown in fig. 5. After the differential input signal is amplified by the first error amplifier U2 and the second source follower A1, the differential output signal is fed back to two branches of the source degeneration resistor R0 by a negative transconductance-GM circuit, and the negative feedback is used for automatically adjusting offset voltage caused by system offset and random offset, and larger noise and offset voltage caused by emitter degeneration linearization.

Referring to fig. 6, the gain-adjustable GM-C integrator 500 includes:

the control end of the third MOS tube M3 is connected with the first output end of the modulation circuit, and the control end of the fourth MOS tube M4 is connected with the second output end of the modulation circuit;

a fifth MOS transistor M5 and a sixth MOS transistor M6, where a control end of the fifth MOS transistor M5 and a control end of the sixth MOS transistor M6 are used for inputting a preset reference voltage signal, an output end of the fifth MOS transistor M5 is connected to an input end of the third MOS transistor M3, and an output end of the sixth MOS transistor M6 is connected to an input end of the fourth MOS transistor M4;

a first output end of the sixth constant current source I6 is connected with an input end of the fifth MOS tube M5, a first output end of the seventh constant current source I7 is connected with an input end of the sixth MOS tube M6, an output end of the sixth constant current source I6 is used as a first output end of the gain-adjustable GM-C integrator 500, and an output end of the seventh constant current source I7 is used as a second output end of the gain-adjustable GM-C integrator 500;

the first resistor R1 and the second resistor R2 are connected in series between the output ends of the sixth constant current source I6 and the seventh constant current source I7;

A first input end of the second error amplifier U3 is connected to a common end of the first resistor R1 and the second resistor R2, and is used for obtaining the common mode feedback signal, a second input end of the second error amplifier U3 is used for obtaining a second reference signal VREF3, and an output end of the second error amplifier U3 is connected to second input ends of the sixth constant current source I6 and the seventh constant current source I7;

an eighth direct current source I8, wherein an input end of the eighth direct current source I8 is connected with output ends of the third MOS tube M3 and the fourth MOS tube M4, and an output end of the eighth direct current source I8 is grounded;

the output terminal of the first GAIN-TRIM is connected to the input terminal of the eighth dc source I8.

Referring to fig. 6, the GAIN-adjustable GM-C integrator 500 mainly comprises an NPN differential input pair (composed of a third MOS transistor M3 and a fourth MOS transistor M4), a common-mode negative feedback detection circuit (composed of a resistor R1 and a resistor R2), a second error amplifier U3, and a first GAIN-TRIM. The integrator consisting of the linear transconductor (OTA) and the capacitor is called GM-C integrator. The single-ended OTA and the fully differential OTA have various advantages, the single-ended OTA does not need to consider a common-mode negative feedback circuit, but is easily affected by noise, and the output range is small. The full differential OTA has obvious advantages compared with the single-ended OTA, and has obvious inhibition capability on offset and noise. The invention adopts a fully differential OTA single capacitance balance structure. The gain-tunable GM-C integrator 500 not only has considerable gain and bandwidth, but also is capable of handling higher signal frequencies, enabling undistorted amplification of hall voltage signals modulated to chopper frequency. In addition, the transconductor outputs current without providing a low-impedance output stage like an operational amplifier, and the internal circuit also does not need an inter-stage miller compensation capacitance, and the output pole Vout of the circuit is the dominant pole, so that the transconductor has good high-frequency characteristics. Since the gain-adjustable GM-C integrator 500 is operated in an open loop, the linear transconductance signal input range of the transconductor is closely related to linearity, and the present invention adopts NPN pair transistors operating in a subthreshold region as input stages to linearize the transconductor. The invention also adjusts the gain value by adjusting the current magnitude of the tail current source. Referring to fig. 7, the first GAIN-TRIM may be fine-tuned by using a mirror current source structure, and by presetting a programmable adjustment bit, the GAIN value is changed from 200 to 300.

Referring to fig. 8, the magnetic field direction control circuit 300 includes:

a third source follower A2, an input terminal of the third source follower A2 being an input terminal of the magnetic field direction control circuit 300;

a first direction control switch b_dir1, a second direction control switch b_dir2, a third direction control switch b_dir3 and a fourth direction control switch b_dir4, wherein a first end of the first direction control switch b_dir1 is connected to a first output end of the third source follower A2, a first end of the second direction control switch b_dir2 is connected to a second output end of the third source follower A2, a first end of the third direction control switch b_dir3 is connected to a second end of the second direction control switch b_dir2, a second end of the third direction control switch b_dir3 is connected to a first end of the first direction control switch b_dir1, a first end of the fourth direction control switch b_dir4 is connected to a first end of the second direction control switch b_dir2, a second end of the fourth direction control switch b_dir4 is connected to a second end of the first direction control switch b_dir2 = 1;

and a first input end of the fourth source follower A3 is connected with the second end of the first direction control switch b_dir1, a second input end of the fourth source follower A3 is connected with the second end of the second direction control switch b_dir2, an output end of the third source follower A2 is used as an output end of the magnetic field direction control circuit 300, and a=1 of the fourth source follower A3.

The structures of the third source follower A2 and the fourth source follower A3 may be set according to the user's requirement, for example, the third source follower A2 may be shown in fig. 9, the fourth source follower A3 may be shown in fig. 10, and fig. 9 and 10 are two different types of source followers respectively.

The polarity of the hall voltage signal is related to the direction of the applied magnetic field and the direction of the hall bias current generated, as well as the characteristics of the semiconductor material. The polarities of the hall voltage signals generated by the N-type and P-type semiconductor materials are opposite when the direction of the externally applied magnetic field and the direction of the current are the same. Because the hall sensor is applied to various kinds of modules, and in order to not change the structure of the original module, only the hall sensor is replaced, so that the problem of polarity compatibility exists, the polarity adjustment can be performed according to the application situation only by configuring the magnetic field direction control signal b_dir by introducing the magnetic field direction control circuit 300. Referring to the magnetic field direction control circuit 300 shown in fig. 8, the circuit introduces two source followers for isolation in order not to affect the operation of the pre-post circuit. Wherein the post-stage source follower incorporates a negative feedback loop to reduce system mismatch caused by the directional control switching tube and random mismatch caused by device mismatch. When the B_DIR signal for controlling the first direction control switch and the second direction control switch is effective, the polarity of the Hall voltage signal is unchanged, and the Hall voltage signal is used as the input of the next stage; the signals used for controlling the third direction control switch and the fourth direction control switch are complementary with the B_DIR signals, and when the B_DIR signals used for controlling the first direction control switch and the second direction control switch are invalid, the polarities of the Hall voltage signals are exchanged to serve as the input of the next stage, so that the purpose of controlling the magnetic field direction is achieved.

Referring to fig. 11, the offset voltage adjustable step-down transformer 400 includes:

the input end of the first operational amplifier U4 is used as the input end of the offset voltage adjustable subtracting device 400, and the output end of the operational amplifier is used as the output end of the offset voltage adjustable subtracting device 400;

a second operational amplifier U5, wherein a first input end of the second operational amplifier U5 is used for inputting a third reference signal VREF4,

the output end of the OFFSET voltage fine adjuster offset_trim is connected with the second input end of the second operational amplifier U5, and the schematic structural diagram of the OFFSET voltage fine adjuster offset_trim can be shown in fig. 12;

the first end of the voltage dividing circuit is connected with the inverting input end of the first operational amplifier U4, the second end of the voltage dividing circuit is connected with the output end of the second operational amplifier U5, the third end of the voltage dividing circuit is connected with the output end of the OFFSET voltage fine regulator OFFSET_TRIM, see FIG. 11, the voltage dividing circuit is composed of two series voltage dividing resistors, and three ports of the voltage dividing circuit are respectively used as the first end, the second end and the third end of the voltage dividing circuit.

The circuit structure of the offset voltage-adjustable subtracting device 400 is shown in fig. 11, and the circuit is matched with the two-phase rotating current control circuit 100 to eliminate the offset voltage of the hall device and obtain the amplified hall voltage signal. Vout= +a1 a2 a3 Δv or vout= -a1 a2 a3 Δv, the polarity of which is determined by the magnetic field direction control signal b_dir. The OFFSET voltage fine adjuster OFFSET_TRIM is added to a classical subtracter, and the proportional relation between the static output voltage of the linear Hall sensor and the off-chip OFFSET reference voltage is set to be 50%. Because the offset of the hall device, the offset of the amplifying circuit, the residual offset voltage introduced by the switching tube and the like cannot be completely eliminated by the chopper and the differential structure, and certain errors exist, the linear hall sensor reading circuit sets the static output voltage vout=40% VREF in a default state, and then adjusts the static output voltage to vout=50% VREF through the offset voltage fine adjustment module. The OFFSET voltage fine tuning module OFFSET_TRIM adopts a mirror current source structure to conduct fine tuning, and the change of the static output voltage VOUT from 40% VREF to 60% VREF is met through presetting a programmable regulation bit.

In another comprehensive embodiment of the present application, in summary, the above specific circuits are disclosed, referring to fig. 13, a control timing sequence of the readout circuit in the circuit is shown in fig. 14, a transient waveform of a key signal of the readout circuit in the circuit is shown in fig. 15, where V1 is a voltage difference between two input terminals of OAT, V2 is a voltage difference between two input terminals of GM-C, V3 is a voltage difference between two output terminals of GM-C, V4 is a voltage value of an output signal of the output terminal of the first source follower, v5+ is a voltage value of an output signal of the first output terminal of A3, v5+ is a voltage value of an output signal of the second output terminal of A3, VOUT is an output signal of the readout circuit of the hall sensor, and a direction of VOUT is changed according to a state setting of a signal b_dir of the magnetic field direction control circuit 300. The Hall device obtains two-phase bias current through two-phase rotating current control clocks CLK+ and CLK-to generate corresponding positive Hall voltage signals +DeltaV and negative Hall voltage signals-DeltaV, offset voltage Vhall_os and flicker noise voltage Vhall_n generated by the Hall device are generated at the same time, and then, a chopper circuit is adopted to sample the positive Hall voltage signals and the negative Hall voltage signals which are output by the two-phase rotating current control circuit 100 and have offset and noise by adopting a chopper dynamic offset elimination technology and a time-sharing sampling technology, and the working process is as follows: firstly, when the signal is not sampled, CLK_ZERO is enabled, chopper modulation clocks CH1 and CH2 and demodulation clocks CH5 and CH6 are turned off, at the moment, positive and negative input ends of a detection amplifying circuit formed by OTA and GM_C are short-circuited, an input common mode level bias is provided through a first capacitor C1, an input offset voltage Va1a2_os and an input reference noise voltage Va1a2_n of the detection amplifying circuit are stored in capacitors respectively connected with two output ends of the GM_C integrator, and high-order harmonic noise components are filtered due to the filtering function of the GM_C integrator. When a positive hall voltage signal with offset and noise is sampled, clk_zero is set to ZERO, a chopper modulation clock CH1 is enabled, the positive hall voltage signal +Δv, a hall device offset voltage vhall_os and a flicker noise voltage vhall_n are modulated to a high frequency end and amplified by a detection amplifying circuit, then, a chopper demodulation clock CH5 is enabled, an input offset voltage Va1a2_os and an input reference noise voltage Va1a2_n of the detection amplifying circuit are modulated to the high frequency end, the amplified positive hall voltage signal at the high frequency end, the hall device offset voltage and the flicker noise voltage are demodulated, and after passing through a low pass filter LPF, the input offset voltage and the input reference noise voltage of the detection amplifying circuit and the flicker noise voltage of the hall device are eliminated, and the amplified positive hall voltage signal and the amplified hall device offset voltage are obtained, wherein the values are 0.5 x a1 x Δv+vhall_os; when a negative Hall voltage signal with offset and noise is sampled, CLK_ZERO is set to ZERO, a chopper modulation clock CH2 is enabled, a negative Hall voltage signal-DeltaV, a Hall device offset voltage Vhall_os and a flicker noise voltage Vhall_n are modulated to a high-frequency end and amplified by a detection amplifying circuit, then a chopper demodulation clock CH6 is enabled, an input offset voltage Va1a2_os and an input reference noise voltage Va1a2_n of the detection amplifying circuit are modulated to the high-frequency end, the amplified negative Hall voltage signal of the high-frequency end, the Hall device offset voltage and the flicker noise voltage are demodulated, and the input offset voltage and the input reference noise voltage of the Hall device and the flicker noise voltage of the Hall device are eliminated after passing through a low-pass filter LPF, so that amplified negative Hall voltage signals and the Hall device offset voltage are obtained, and the values of which are 0.5A 1 (-DeltaV+Vhall_os); then, the positive and negative signals are subtracted by a subtracter, and the direct current offset voltage of the hall device is eliminated, so that an amplified hall voltage signal is obtained, the value of which is + -A1, A2, A3, deltaV, and the positive and negative directions are determined by the signal B_DIR state of the magnetic field direction control circuit 300.

Corresponding to the circuit, the application also discloses an electronic device, wherein the Hall sensor reading circuit can be applied to the electronic device, and the electronic device can be any electronic device known in the prior art.

In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A hall sensor readout circuit, comprising:

the hall sensor readout circuit further includes:

2. The hall sensor readout circuit of claim 1, wherein the two-phase rotating current control circuit is configured to:

3. The hall sensor readout circuit of claim 2, wherein the two-phase rotating current control circuit comprises:

4. The hall sensor readout circuit of claim 1, wherein the modulation circuit comprises:

5. The hall sensor readout circuit of claim 1, wherein the demodulation circuit comprises:

6. The hall sensor readout circuit of claim 4, wherein the linear transconductance operational amplifier comprises:

7. The hall sensor readout circuit of claim 6, wherein the gain-adjustable GM-C integrator comprises:

the control end of the fifth MOS tube and the control end of the sixth MOS tube are used for inputting a preset reference voltage signal, the output end of the fifth MOS tube is connected with the input end of the third MOS tube, and the output end of the sixth MOS tube is connected with the input end of the fourth MOS tube;

The first input end of the second error amplifier is connected with the common end of the first resistor and the second resistor and used for acquiring the common mode feedback signal, the second input end of the second error amplifier is used for acquiring a second reference signal, and the output end of the second error amplifier is connected with the second input ends of the sixth constant current source and the seventh constant current source;

8. The hall sensor readout circuit of claim 1, wherein the magnetic field direction control circuit comprises:

9. The hall sensor readout circuit of claim 1, wherein the offset voltage adjustable step-down device comprises:

10. An electronic device, characterized in that the hall sensor read-out circuit according to any one of claims 1-9 is applied.