CN112511112A - Digital predistortion circuit and digital predistortion method - Google Patents
Digital predistortion circuit and digital predistortion method Download PDFInfo
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Abstract
The invention provides a digital predistortion circuit and a digital predistortion method. In the method, an input signal is sequentially subjected to pre-distortion processing, digital-to-analog conversion, and amplification processing to generate an output signal. The first bandwidth of the input signal after the pre-distortion processing is larger than the second bandwidth of the input signal after the digital-to-analog conversion. The output signal is filtered for signals outside the second bandwidth to produce a second output signal. And estimating a third output signal after the predistortion signal is amplified according to the predistortion signal of the input signal after the predistortion processing and the second output signal. The third bandwidth of the third output signal is greater than the second bandwidth. And determining parameters of predistortion processing according to the third output signal and the predistortion signal. Therefore, the distortion condition except the second bandwidth can be corrected, and the defect of insufficient bandwidth is further overcome.
Description
Technical Field
The present invention relates to signal processing technologies, and in particular, to a Digital Pre-Distortion (DPD) circuit and a Digital DPD method.
Background
The Power level of the signal affects the performance and throughput of the communication system, and thus a Power Amplifier (PA) plays an indispensable role in the communication system. The power amplifier has a non-linear characteristic, and when it operates in a high power range, it will cause distortion phenomena such as spectrum undesired increase (spectral re-growth), adjacent channel interference (adjacent channel interference) and out-of-band leakage (out-of-band distortion), and in-band distortion (in-band distortion). In order to solve the aforementioned distortion phenomenon, a digital predistortion technique is proposed. Digital predistortion techniques may perform signal training (training) on the output and input signals of the power amplifier and form a compensation signal accordingly, i.e., apply predistortion to the input signal via the compensation signal.
Fig. 1 is a schematic flow chart of digital predistortion, and fig. 2 is a circuit of the prior art applying digital predistortion. Referring to fig. 1 and fig. 2, after the spectrum 201 of the original transmission signal passes through the Power Amplifier (PA), there is a leakage (leakage). This phenomenon will cause the quality of the transmitted signal to be degraded and further affect the signals of adjacent bandwidths to cause inter-band interference (inter-band interference). In order to suppress the above phenomenon, the signal x (n) is fed back to the receiving end through the coupler after passing through the Digital-to-Analog Converter (DAC) and the Power Amplifier (PA) (i.e., the output signal is obtained through the feedback path), the fed-back signal y (n) is fed back into the Digital predistortion trainer (DPD Training) after passing through the Analog-to-Digital Converter (ADC), and the coefficient obtained by the DPD trainer is transmitted to the DPD actuator for use. Wherein, the DPD trainer will find out the signal x (n), the signal z (n) after pre-distortion processing and the training signal
With the smallest error e (n) between the coefficients.
Notably, DPD techniques can modify signals within the DAC bandwidth, but cannot modify signals outside the DAC bandwidth. As shown in fig. 2, assuming that the bandwidth of the signal spectrum 201 is 100 megahertz (MHz), the Adjacent Channel Leakage Ratio (ACLR) in 5 times the bandwidth of the signal after passing through the power amplifier increases (the bandwidth of the spectrum 203 is 500 MHz). When the bandwidth of the DAC and ADC is sufficient (e.g., 500MHz bandwidth), the problem of adjacent channel leakage ratio can be corrected by the DPD performer (the bandwidth of the spectrum 202 after the predistortion processing is 500MHz), and the signal can be restored to the original transmission signal (the spectrum 201 in fig. 2 is approximately the same as the spectrum 203 (amplitude increase)). However, when the bandwidth of DAC and ADC is less than 5 times, the DPD executor can only correct part of the adjacent channel leakage ratio problem. It can be seen that the digital predistortion technique for bandwidth limitation still needs to be improved.
Disclosure of Invention
The invention aims at a digital predistortion circuit and a digital predistortion method, and can make up for the problem caused by insufficient bandwidth by training a predistortion model based on an estimated output signal with larger bandwidth under the condition of bandwidth limitation.
According to an embodiment of the invention, the digital predistortion method comprises the following steps: the input signal is sequentially subjected to pre-distortion processing, digital-to-analog conversion and amplification processing to generate an output signal. The first bandwidth of the input signal after the pre-distortion processing is larger than the second bandwidth of the input signal after the digital-to-analog conversion. The output signal is filtered for signals outside the second bandwidth to produce a second output signal. And estimating a third output signal after the predistortion signal is amplified according to the predistortion signal of the input signal after the predistortion processing and the second output signal. The third bandwidth of the third output signal is greater than the second bandwidth. And determining parameters of predistortion processing according to the third output signal and the predistortion signal.
According to an embodiment of the present invention, a digital predistortion circuit includes a predistorter, a digital-to-analog converter, an amplification circuit, a band-pass filter, and an output signal estimation circuit. The predistorter performs predistortion processing on an input signal to generate a predistorted signal. The pre-distorted signal has a first bandwidth. The digital-to-analog converter is coupled with the predistorter and converts the predistortion signal into an analog predistortion signal. The analog predistortion signal has a second bandwidth, and the first bandwidth is greater than the second bandwidth. The amplifying circuit is coupled to the digital-to-analog converter and amplifies the analog predistortion signal to generate an output signal. The band-pass filter is coupled to the amplifying circuit and filters the output signal with a signal outside a second bandwidth to generate a second output signal. The output signal estimation circuit is coupled with the band-pass filter and the predistorter and estimates a third output signal of the predistortion signal after being processed by the amplifying circuit according to the predistortion signal and the second output signal. The third bandwidth of the third output signal is greater than the second bandwidth, and the predistorter determines parameters of predistortion processing according to the third output signal and the predistortion signal.
Based on the above, in the digital predistortion circuit and the digital predistortion method of the embodiments of the present invention, for the digital-to-analog converter whose bandwidth is smaller than the bandwidth processed by the amplifying circuit, the output signal is filtered by signals other than the bandwidth of the digital-to-analog converter, and accordingly, the output signal with a larger bandwidth is estimated. This output signal will be available for predistortion training. Therefore, the parameters obtained by training can further correct distortion conditions except the bandwidth of the digital-to-analog converter, and the defect of insufficient bandwidth can be overcome.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.
FIG. 1 is a schematic flow diagram of digital predistortion;
FIG. 2 is a prior art circuit employing digital predistortion;
FIG. 3 is a block diagram of components of a digital predistortion circuit in accordance with an embodiment of the present invention;
FIG. 4 is a flow chart of a digital predistortion method in accordance with an embodiment of the present invention;
fig. 5 is a block diagram and a frequency spectrum diagram of a digital predistortion circuit according to an embodiment of the invention.
Description of the reference numerals
201 to 203, 501 to 504: a frequency spectrum;
x(n)、y(n)、z(n)、
a signal;
e (n), e 2: an error;
100: a digital predistortion circuit;
110: a predistorter;
111: a DPD actuator;
112: a DPD trainer;
113. 155: a summing circuit;
120: a digital-to-analog converter;
130: an amplifying circuit;
140: a band-pass filter;
150: an output signal estimation circuit;
151: an analog-to-digital converter;
152: an amplifier circuit model estimator;
153. 154: a low-pass filter;
IS: inputting a signal;
and (2) PDS: pre-distorting the signal;
APDS: simulating a predistortion signal;
and OS: outputting the signal;
OS 2: a second output signal;
OS 3: a third output signal;
s410 to S470: a step of;
DOS: a digital output signal;
and (4) SOS: simulating an output signal;
OS 4: a fourth output signal;
OS 5: a fifth output signal;
EPDS: estimating a predistortion signal;
DPDP: and (4) parameters.
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Fig. 3 is a block diagram of the components of the digital predistortion circuit 100 in accordance with an embodiment of the present invention. Referring to fig. 3, the digital predistortion circuit 100 includes, but is not limited to, a predistorter 110, a digital-to-analog converter 120, an amplifying circuit 130, a band-pass filter 140 and an output signal estimation circuit 150. The digital predistortion circuit 100 may be embedded in various types of base stations, user equipment (e.g., cell phones, tablet computers, etc.), communication transceivers (e.g., supporting Wi-Fi, or various generations of mobile communication technologies), or other communication transceiving devices.
The predistorter 110 receives the input signal IS in a digital form and IS configured to perform predistortion processing on the input signal IS to generate a predistortion signal PDS, the detailed functions of which will be described in detail in the following embodiments. The predistorter 110 may be implemented by Programmable units such as a Digital Signal Processor (DSP), a microprocessor, an Application-Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), and so on.
The digital-to-analog converter 120 is coupled to the predistorter 110 and is configured to perform digital-to-analog conversion on the predistortion signal PDS to generate an analog predistortion signal APDS (i.e., a predistortion signal PDS in an analog form). It IS noted that, in the embodiment of the invention, the first bandwidth of the input signal IS after the pre-distortion processing IS larger than the second bandwidth of the input signal IS after the digital-to-analog conversion (i.e., the digital-to-analog converter 120 has the second bandwidth). For example, the first bandwidth is 500MHz and the second bandwidth is 300 MHz.
The amplifying circuit 130 is coupled to the digital-to-analog converter 120 and configured to amplify the analog predistortion signal APDS to generate an output signal OS. The amplifying circuit 130 may be a power amplifier for adjusting a power gain of the analog predistortion signal APDS. It should be noted that, in some embodiments, a mixer may be further connected between the amplifying circuit 130 and the digital-to-analog converter 120 to form the output signal OS of the radio frequency.
The band-pass filter 140 is coupled to the amplifying circuit 130 and is configured to filter the output signal OS by a signal outside a specific bandwidth to generate a second output signal OS 2. This second output signal OS2 may be further transmitted out through an antenna and/or other transmitter. It should be noted that, in some embodiments, a coupler may be further connected between the band pass filter 140 and the amplifying circuit 130 to feed back the output signal OS to the receiving end (i.e., the digital predistortion circuit 100).
The output signal estimation circuit 150 is coupled to the band pass filter 140 and the predistorter 110, and is configured to receive the predistortion signal PDS and the second output signal OS2, and accordingly generate a third output signal OS3, the detailed functions of which will be described in detail in the following embodiments. The output signal estimation circuit 150 may be implemented by a programmable unit such as a digital signal processor, a microprocessor, an asic, a field programmable gate array, etc., or may be a circuit composed of several digital circuits.
To facilitate understanding of the operation flow of the embodiment of the present invention, the signal processing flow of the digital predistortion circuit 100 in the embodiment of the present invention will be described in detail below with reference to a plurality of embodiments. The method according to the embodiment of the present invention will be described with reference to various components and modules in the digital predistortion circuit 100. The various processes of the method may be modified according to implementation, and are not limited thereto.
Fig. 4 is a flowchart of a digital predistortion method according to an embodiment of the invention. Referring to fig. 4, the digital predistortion circuit 100 sequentially performs predistortion processing, digital-to-analog conversion, and amplification processing on the input signal IS to generate an output signal OS (step S410). Specifically, predistorter 110 may perform predistortion processing using a model such as a Wiener-Hammerstein model, a Memory Multinomial (MP) model, a Generalized Memory multinomial (GMP) model, or other Memory power amplifier model. For example, the mathematical expression of the memory polynomial model is as follows:
yMP(n)＝∑k＝1∑q＝0ckqx(n-q)|x(n-q)|k-1…(1)
yMP(n) IS the output signal of predistorter 110 (i.e., predistortion signal PDS), x (n) IS the input signal of predistorter 110 (i.e., input signal IS), ckqIs a coefficient and n is an integer. As another example, the mathematical expression of the generalized memory polynomial model is represented as follows:
yGMP(n)＝∑k＝1∑Q＝0akqx(n-q)|x(n-q)|k-1
+∑k＝2∑Q＝0∑l＝1bkqlx(n-q)|x(n-q-l)|k-1
+∑k＝2∑Q＝0∑l＝1ckqlx(n-q)|x(n-q+l)|k-1…(2)
yGMP(n) IS the output signal of predistorter 110 (i.e., predistortion signal PDS), x (n) IS the input signal of predistorter 110 (i.e., input signal IS), akq、bkql、ckqlIs a coefficient. The coefficients of the functions used in the pre-distortion processing are parameters (e.g., coefficients of a pre-distortion model or other gain function, etc.) trained by the pre-distorter 110 based on the third output signal OS3 and the pre-distortion signal PDS. For example, predistorter 110 minimizes the error between predistorted signal PDS and the signal of third output signal OS3 after an inverse model/function of amplification circuit 130 (i.e., a predistortion model) and derives an inverse model with the minimum error. The predistorter 110 may also compensate for distortion phenomena of the amplifying circuit 130 outside the bandwidth of the input signal IS based on these parameters.
It should be noted that predistorter 110 of the present embodiment includes both training (e.g., training coefficients of a predistortion model or a gain function) and modifying (e.g., passing input signal IS through a memory power amplifier model or multiplying by a gain function). In addition, the predistortion is performed by an adaptive algorithm, but in some embodiments, the predistorter 110 may also use a look-up table (e.g., linear mapping or gain mapping) to derive the predistorted signal PDS.
It is noted that the present embodiment is directed to the limitation that the second bandwidth of the digital-to-analog converter 120 is smaller than the first bandwidth of the predistortion signal PDS. That is, the second bandwidth of the analog predistortion signal APDS is smaller than the first bandwidth of the predistortion signal PDS. However, the output signal OS generated by the amplification processing of the analog predistortion signal APDS by the amplification circuit 130 may have distortion phenomena (e.g., leakage, spectral growth, etc.) occurring outside the second bandwidth. If predistorter 110 trains the parameters for the predistortion process based on output signal OS and predistortion signal PDS, these parameters may only compensate for the distortion in the second bandwidth. To solve the aforementioned problem, the embodiment of the present invention further processes the output signal OS.
The band pass filter 140 filters the output signal OS for signals outside the second bandwidth to generate a second output signal OS2 (step S430). For example, the second bandwidth is 200MHz, then the second output signal OS2 is a signal within 200MHz reserved for the output signal OS. Thereby, it is ensured that the distortion of the output signal OS by the amplifying circuit 130 outside the second bandwidth is removed.
Next, the output signal estimation circuit 150 estimates the third output signal OS3 according to the predistorted signal PDS of the input signal IS and the second output signal OS2 (step S450). Specifically, since the second bandwidth is not enough to the bandwidth amplified by the amplifying circuit 130, the predistortion processing based on the training of the output signal OS may not be able to complete the correction of the output signal OS for signals other than the second bandwidth. An embodiment of the present invention first generates a third output signal OS3 having a bandwidth greater than the second bandwidth. The output signal estimation circuit 150 may estimate the simulated amplifying circuit corresponding to the amplifying circuit 130. The simulation amplifying circuit can be in a functional form or a comparison table form. The signal of the predistortion signal PDS passing through the artificial amplification circuit will approach the third output signal OS3 within the second bandwidth. For example, the output signal estimation circuit 150 minimizes the error between the signal of the pre-distorted signal PDS after passing through the artificial amplification circuit and the second output signal OS2, and obtains a function of the artificial amplification circuit with the minimum error. The output signal estimation circuit 150 then amplifies the predistortion signal PDS by the artificial amplification circuit to generate a third output signal OS 3. The third output signal OS3 is generated assuming that the predistortion signal PDS has not been subjected to a bandwidth limited digital-to-analog conversion and the third bandwidth of the third output signal OS3 is larger than the second bandwidth. The third bandwidth may be equal to the first bandwidth or another bandwidth greater than the second bandwidth.
Next, the predistorter 110 determines parameters of the predistortion process according to the third output signal OS3 and the predistortion signal PDS (step S470). Specifically, the third output signal OS3 is not subject to the bandwidth limitations of digital-to-analog conversion compared to the output signal OS. Therefore, based on the parameters (e.g., the coefficients of the predistortion model or other gain function, etc.) obtained by the training of the third output signal OS3, the predistorter 110 should be modifiable for signals outside the second bandwidth. Taking the predistortion model of the memory power amplifier as an example, the mathematical expression of the bandwidth-limited memory polynomial model is as follows:
yMP,L(n)＝∑mhmyMP(n-m)
＝∑k＝1∑Q＝0∑mhmckqx(n-q-m)|x(n-q-m)|k-1
＝∑k＝1∑Q＝0ckq∑mhmx(n-q-m)|x(n-q-m)|k-1
＝∑k＝1∑Q＝0ckqxL(n-q-m)…(3)
yMP,L(n) is the output signal of predistorter 110 (i.e., predistortion signal PDS), hmIs the frequency response of the low-pass filtering process (whose bandwidth is not greater than the bandwidth of the band-pass filter 140 (i.e., the second bandwidth)). Within the pass band of the low pass filtering process, the predistorter 110 may solve (i.e., derive coefficients) for errors between the predistorted signal PDS and the signal of the third output signal OS3 after an inverse model/function (i.e., predistortion model) of the amplification circuit 130 using optimization methods such as Least Squares (LS), Mean Squares (MS), Root Mean Squares (RMS), etc., whose mathematical equations are expressed as follows:
yMP,L＝XMO,LcPA,BL…(4)
yMP,Lis the output signal of predistorter 110 (i.e., predistorted signal PDS), XMP,LIS the input signal (i.e., input signal IS), c of predistorter 110PA,BLIs the full bandwidth factor (which corresponds to a bandwidth greater than the second bandwidth).
As another example, the mathematical expression of the bandwidth-limited generalized memory polynomial model is represented as follows:
yGMP,L(n)＝∑mhmyGMP(n-m)
＝∑k＝1∑q＝0akq∑mhmx(n-q-m)|x(n-q-m)|k-1
+∑k＝1∑q＝0∑l＝1bkql∑mhmx(n-q-m)|x(n-q-l-m)|k-1
+∑k＝1∑q＝0∑l＝1ckql∑mhmx(n-q-m)|x(n-q+l-m)|k-1…(5)
yGMP,L(n) is the output signal of predistorter 110 (i.e., predistortion signal PDS). Likewise, predistorter 110 may also solve for equation (5) using optimization methods such as least squares, mean squares, root mean squares). Then, the predistorter 110 may perform predistortion processing based on the parametric input signal IS trained by the third output signal OS 3. Thereby, the distortion phenomenon of the output signal OS outside the second bandwidth can be corrected.
Referring to the more detailed hardware architecture, fig. 5 is a block diagram and a spectrum diagram of components of the digital predistortion circuit 100 according to an embodiment of the invention. Referring to fig. 5, predistorter 110 includes a DPD executor 111, a DPD trainer 112, and a summation (summation) circuit 113. The output signal estimation circuit 150 includes an analog-to-digital converter 151, an amplifier circuit model estimator 152, low pass filters 153 and 154, and a summation circuit 155.
The DPD executor 111 and the DPD trainer 112 are used for performing the correction and training functions of the predistorter 110. The low- pass filters 153, 154 are filters whose frequency response is known, and whose bandwidth is not greater than the bandwidth (i.e., the second bandwidth) of the band-pass filter 140. The amplifier circuit model estimator 152 may be implemented by a digital signal processor, a microprocessor, an application specific integrated circuit, a field programmable gate array, or other programmable units.
The input signal IS sequentially passed through the digital-to-analog converter 120, the amplifying circuit 130 and the band-pass filter 140 to generate a second output signal OS 2. The analog-to-digital converter 151 converts the second output signal OS2 into a digital output signal DOS in a digital form, and the low-pass filter 153 low-pass filters the digital output signal DOS to generate the fourth output signal OS 4. On the other hand, the amplifier circuit model estimator 152 generates an initial simulation amplifier circuit, and amplifies the predistortion signal PDS through the simulation amplifier circuit to generate the simulation output signal SOS. The low pass filter 154 low pass filters this emulated output signal SOS to produce a fifth output signal OS 5. The summation circuit 155 subtracts the fourth output signal OS4 and the fifth output signal OS5 to obtain an error e between the two output signals OS4, OS 5. This error e can be used to estimate the final simulated amplifier circuit. The amplifier circuit model estimator 152 may minimize the error e to arrive at a simulated amplifier circuit with the smallest error e. Next, the amplifier circuit model estimator 152 will amplify the predistortion signal PDS with the artificial amplifier circuit having the smallest error to form the third output signal OS 3.
The DPD trainer 112 is based on an initial predistortion model and subjects the third output signal OS3 to a predistortion model to generate an estimated predistortion signal EPDS. The sum circuit 113 subtracts the estimated predistortion signal EPDS and the predistortion signal PDS to obtain an error e2 between the two signals EPDS, PDS. This error e2 can be used to generate the final predistortion model. The DPD trainer 112 may minimize the error e2 to derive a predistortion model with the minimum error e 2. Then, the DPD trainer 112 generates parameters DPDP for the predistortion process according to the predistortion model with the minimum error, so as to be used by the DPD executor 111.
For the spectrum variation, the spectrum 501 of the input signal IS pre-distorted by the DPD executor 111 to have an increased bandwidth, but the dac 120 can only form the analog pre-distorted signal APDS having a second bandwidth (the spectrum 502 IS limited to the second bandwidth of the dashed box as shown in the figure). The bandwidth of the output signal OS amplified by the amplifying circuit 130 on the analog predistortion signal APDS may exceed the second bandwidth (the spectrum of which is shown in the figure, and the spectrum 503 still has a frequency response outside the second bandwidth (indicated by the dashed box)). And bandpass filter 140 removes signals outside the second bandwidth to output a second output signal OS2 (the spectrum of which is shown as having the frequency response outside the second bandwidth in spectrum 504 filtered out compared to spectrum 503).
It should be noted that the shapes of the spectrums 501-504 are only used for illustration and are not used to limit the types or parameters of the input signal IS, the dac 120, the amplifying circuit 130, and the band-pass filter 140.
In summary, the digital predistortion circuit and the digital predistortion method of the embodiment of the invention estimate the output signal with larger bandwidth under the limitation that the bandwidth of the digital-to-analog converter is insufficient for the bandwidth processed by the amplifying circuit, and train the parameters used for the predistortion processing through the output signal. In addition, signals out of the bandwidth of the digital-to-analog converter in the output signals processed by the amplifying circuit are filtered. Therefore, the distortion condition except the bandwidth of the digital-to-analog converter can be corrected, and the defect of insufficient bandwidth is further overcome.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A digital predistortion method, comprising:
sequentially carrying out pre-distortion processing, digital-to-analog conversion and amplification processing on an input signal to generate an output signal, wherein a first bandwidth of the input signal after the pre-distortion processing is larger than a second bandwidth of the input signal after the digital-to-analog conversion;
filtering signals outside the second bandwidth on the output signal to produce a second output signal;
estimating a third output signal of the pre-distorted signal after the amplification processing according to the pre-distorted signal of the input signal after the pre-distortion processing and the second output signal, wherein a third bandwidth of the third output signal is greater than the second bandwidth; and
and determining parameters of the predistortion processing according to the third output signal and the predistortion signal.
2. The digital predistortion method of claim 1, wherein the step of estimating the third output signal comprises:
converting the second output signal to a digital output signal; and
estimating the simulation amplifying circuit corresponding to the amplifying circuit according to the predistortion signal and the digital output signal, wherein
The third output signal is generated by amplifying the predistortion signal by the artificial amplification circuit.
3. The digital predistortion method as claimed in claim 2, wherein the step of estimating the simulated amplifying circuit corresponding to the amplifying circuit comprises:
low pass filtering the digital output signal to produce a fourth output signal;
performing the low-pass filtering on the third output signal to generate a fifth output signal, wherein a bandwidth corresponding to the low-pass filtering is not greater than the second bandwidth; and
and generating the simulation amplifying circuit according to the error between the fourth output signal and the fifth output signal.
4. The digital predistortion method of claim 3, wherein the step of generating the artificial amplification circuit comprises:
minimizing the error to obtain the simulation amplifying circuit with the minimum error.
5. The digital predistortion method of claim 1, wherein the third bandwidth is equal to the first bandwidth.
6. A digital predistortion circuit, comprising:
a predistorter for performing predistortion processing on an input signal to generate a predistorted signal, wherein the predistorted signal has a first bandwidth;
a digital-to-analog converter coupled to the predistorter and converting the predistorted signal into an analog predistorted signal, wherein the analog predistorted signal has a second bandwidth, and the first bandwidth is greater than the second bandwidth;
the amplifying circuit is coupled with the digital-to-analog converter and amplifies the analog predistortion signal to generate an output signal;
a band-pass filter coupled to the amplifying circuit and configured to filter the output signal outside the second bandwidth to generate a second output signal; and
and an output signal estimation circuit, coupled to the band-pass filter and the predistorter, for estimating a third output signal of the predistorted signal after being processed by the amplification circuit according to the predistorted signal and the second output signal, where a third bandwidth of the third output signal is greater than the second bandwidth, and the predistorter determines a parameter of the predistortion processing according to the third output signal and the predistorted signal.
7. The digital predistortion circuit of claim 6, wherein the output signal estimation circuit comprises:
an analog-to-digital converter coupled to the band pass filter and converting the second output signal to a digital output signal; and
an amplifier circuit model estimator coupled to the ADC and the predistorter for estimating an analog amplifier circuit corresponding to the amplifier circuit according to the predistortion signal and the digital output signal, wherein the amplifier circuit model estimator estimates the analog amplifier circuit corresponding to the amplifier circuit according to the predistortion signal and the digital output signal
The third output signal is generated by amplifying the predistortion signal by the artificial amplification circuit.
8. The digital predistortion circuit of claim 7, wherein the output signal estimation circuit further comprises:
a first low pass filter coupled to the analog-to-digital converter and filtering the digital output signal to generate a fourth output signal; and
a second low pass filter coupled to the amplifier circuit model estimator and filtering the third output signal to generate a fifth output signal, wherein bandwidths of the first low pass filter and the second low pass filter are not greater than the second bandwidth, and wherein
The amplifier circuit model estimator generates the simulation amplifier circuit according to an error between the fourth output signal and the fifth output signal.
9. The digital predistortion circuit of claim 8 wherein the amplifier circuit model estimator minimizes the error to arrive at the simulated amplifier circuit with the minimum error.
10. The digital predistortion circuit of claim 6, wherein the third bandwidth is equal to the first bandwidth.
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