CN112510030B - Chip, three-dimensional chip, electronic device, and method for manufacturing three-dimensional chip - Google Patents

Chip, three-dimensional chip, electronic device, and method for manufacturing three-dimensional chip Download PDF

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Publication number
CN112510030B
CN112510030B CN202011387222.5A CN202011387222A CN112510030B CN 112510030 B CN112510030 B CN 112510030B CN 202011387222 A CN202011387222 A CN 202011387222A CN 112510030 B CN112510030 B CN 112510030B
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chip
circuit
internal
interface
internal interface
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CN112510030A (en
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王嵩
谈杰
刘成
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Xian Unilc Semiconductors Co Ltd
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Xian Unilc Semiconductors Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The application discloses a chip, a three-dimensional chip, electronic equipment and a manufacturing method of the three-dimensional chip, wherein the chip is used as a sub-chip of the three-dimensional chip, and comprises the following components: the internal interface is used for connecting other sub-chips in the three-dimensional chip, wherein the internal circuit is connected to the internal interface through an electrostatic discharge circuit, and the electrostatic discharge circuit is used for discharging electrostatic charges poured from the internal interface. The application aims at the sub-chip forming the inside of the three-dimensional chip, and an electrostatic discharge circuit is connected between the internal circuit and the internal interface, so that when the sub-chip generates an ESD (Electro-STATIC DISCHARGE) event in the assembling process, the electrostatic charge poured from the internal interface can be discharged, thereby avoiding the damage of the sub-chip and solving the technical problem of poor reliability of the three-dimensional chip in the prior art.

Description

Chip, three-dimensional chip, electronic device, and method for manufacturing three-dimensional chip
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a chip, a three-dimensional chip, an electronic device, and a method for manufacturing the three-dimensional chip.
Background
As chip technology is becoming finer, the technology goes to 3 nanometers, moore's law encounters a development bottleneck, and physical dimensions are almost limited, but the market demand for chip performance is not reduced. In this case, it is becoming more and more difficult to continue to shrink critical dimensions in various different kinds of chip technologies to achieve performance improvement, area reduction and cost reduction, and integration of different chips or different areas of the same chip by means of wafer three-dimensional integration is one of the main directions of integrated circuit technology development, and reliability of three-dimensional chips has received unprecedented attention.
However, the three-dimensional chip in the prior art is poor in reliability.
Disclosure of Invention
The embodiment of the application solves the technical problem of poor reliability of the three-dimensional chip in the prior art by providing the chip, the three-dimensional chip, the electronic equipment and the manufacturing method of the three-dimensional chip.
In a first aspect, the present application provides, according to an embodiment of the present application, the following technical solutions:
A chip for use as a sub-chip of a three-dimensional chip, the chip comprising: the internal circuit is used for realizing the receiving and transmitting functions of the chip, and is used for connecting other sub-chips in the three-dimensional chip, wherein the internal circuit is connected to the internal interface through an electrostatic discharge circuit, and the electrostatic discharge circuit is used for discharging electrostatic charges poured from the internal interface.
In one embodiment, the number of the internal circuits is one or more, and a single internal circuit comprises any one of a transceiver circuit, a receiving circuit and a transmitting circuit, wherein the transceiver circuit is used for realizing the receiving function and the transmitting function of the chip; the receiving circuit is used for realizing the receiving function of the chip; the transmitting circuit is used for realizing the transmitting function of the chip.
In one embodiment, each of the internal circuits corresponds to one of the internal interfaces and one of the electrostatic discharge circuits.
In one embodiment, the internal interface connects the other sub-chips by way of hybrid bonding.
In one embodiment, the chip is a memory chip or a logic chip.
In a second aspect, the present application provides, according to an embodiment of the present application, the following technical solutions:
a three-dimensional chip comprising the chip of any one of the two first aspects, wherein two of the chips are interconnected by respective ones of the internal interfaces.
In one embodiment, each of the internal circuits corresponds to a respective one of the internal interfaces; the two chips are a first chip and a second chip respectively, wherein when the internal circuit of the first chip comprises a transceiver circuit, the internal circuit of the second chip comprises the transceiver circuit, an internal interface corresponding to the transceiver circuit of the first chip is correspondingly connected with an internal interface corresponding to the transceiver circuit of the second chip, and the transceiver circuit is used for realizing the receiving function and the transmitting function of the chip; when the internal circuit of the first chip comprises a receiving circuit, the internal circuit of the second chip comprises a transmitting circuit, the internal interface corresponding to the receiving circuit of the first chip is correspondingly connected with the internal interface corresponding to the transmitting circuit of the second chip, the receiving circuit is used for realizing the receiving function of the chip, and the transmitting circuit is used for realizing the transmitting function of the chip; when the internal circuit of the first chip comprises the transmitting circuit, the internal circuit of the second chip comprises the receiving circuit, and the internal interface corresponding to the transmitting circuit of the first chip is correspondingly connected with the internal interface corresponding to the receiving circuit of the second chip.
In one embodiment, the internal interface of the first chip is connected with the internal interface of the second chip by means of hybrid bonding.
In a third aspect, the present application provides, according to an embodiment of the present application, the following technical solutions:
An electronic device comprising a chip as claimed in any one of the first aspects.
In a fourth aspect, the present application provides, according to an embodiment of the present application, the following technical solutions:
A method of manufacturing a three-dimensional chip, comprising: providing two chips, wherein the chips comprise an internal interface and an internal circuit, the internal circuit is used for realizing the transceiving function of the chips, the internal interface of a first chip of the two chips is used for connecting the internal interface of a second chip of the two chips, the internal circuit is connected to the internal interface through an electrostatic discharge circuit, and the electrostatic discharge circuit is used for discharging electrostatic charges filled from the internal interface; and connecting the two chips through the respective internal interfaces.
In one embodiment, said connecting said two chips through respective said internal interfaces comprises: growing a first bond post on an internal interface of the first chip; growing a second bond post on an internal interface of the second chip; and performing hybrid bonding on the first chip and the second chip through the first bonding post and the second bonding post.
One or more technical solutions provided in the embodiments of the present application at least have the following technical effects or advantages:
The applicant found that in the process of connecting the internal interface of the sub-chip with the internal interfaces of other sub-chips to assemble the three-dimensional chip, the sub-chip and the external assembly device can be in direct contact, and in the process of contact, an ESD (Electro-STATIC DISCHARGE, electrostatic discharge) event can be easily generated on the internal interface of the sub-chip, and the ESD event can generate instantaneous large voltage and large current to destroy the internal functional circuit, thereby causing the functional failure of the sub-chip. Based on the finding, the application aims at the sub-chip forming the inside of the three-dimensional chip, and the electrostatic discharge circuit is connected between the internal circuit and the internal interface, so that when the sub-chip generates an ESD event in the assembling process, the electrostatic discharge circuit can discharge electrostatic charges poured from the internal interface, thereby avoiding the sub-chip from being damaged, solving the technical problems that the three-dimensional chip in the prior art is imperfect in electrostatic protection and the reliability of the three-dimensional chip is poor.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a chip according to a first embodiment of the present application;
FIG. 2 is a diagram showing the internal connection relationship of the chip provided in FIG. 1;
FIG. 3 is a schematic diagram of the internal structure of the chip provided in FIG. 2;
FIG. 4 is a schematic diagram of the internal structure of the chip provided in FIG. 2;
FIG. 5 is a schematic diagram of the internal structure of the chip provided in FIG. 2;
fig. 6 is a schematic structural diagram of a three-dimensional chip according to a second embodiment of the present application;
FIG. 7 is a diagram showing the internal connection relationship of the three-dimensional chip provided in FIG. 6;
fig. 8 is a schematic diagram of an electronic device according to a third embodiment;
fig. 9 is a flowchart of a method for manufacturing a three-dimensional chip according to a fourth embodiment of the present application;
fig. 10-12 are process flow diagrams of a three-dimensional chip according to a second embodiment of the present application.
Detailed Description
The embodiment of the application solves the technical problem of poor reliability of the three-dimensional chip in the prior art by providing the chip, the three-dimensional chip, the electronic equipment and the manufacturing method of the three-dimensional chip.
The technical scheme of the embodiment of the application aims to solve the technical problems, and the overall thought is as follows:
The applicant found that in the process of connecting the internal interface of the sub-chip with the internal interfaces of other sub-chips to assemble the three-dimensional chip, the sub-chip and the external assembly device can be in direct contact, and in the process of contact, an ESD (Electro-STATIC DISCHARGE) event can be easily generated on the internal interface of the sub-chip, and the ESD event can generate instant large voltage and large current to destroy the internal functional circuit, so that the function of the sub-chip is disabled. Based on the finding, the application aims at the sub-chip forming the inside of the three-dimensional chip, and the electrostatic discharge circuit is connected between the internal circuit and the internal interface, so that when the sub-chip generates an ESD event in the assembling process, the electrostatic discharge circuit can discharge the electrostatic charge poured from the internal interface, thereby avoiding the sub-chip from being damaged and solving the technical problem of poor reliability of the three-dimensional chip in the electrostatic protection aspect in the prior art.
In order to better understand the above technical solutions, the following detailed description will refer to the accompanying drawings and specific embodiments.
First, the term "and/or" appearing herein is merely an association relationship describing associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
Example 1
As shown in fig. 1, the present embodiment provides a chip that serves as a sub-chip of a three-dimensional chip. The three-dimensional chip further comprises other sub-chips, all the sub-chips of the three-dimensional chip are connected through an internal interface I to realize transmission of internal data of the three-dimensional chip, each sub-chip further provides an external interface corresponding to the internal interface I of the sub-chip, and the sub-chip is used as an interface for communication between the three-dimensional chip and an external device, is hereinafter collectively called an external interface, and is hereinafter described in detail as a chip of the sub-chip of the three-dimensional chip.
The chip comprises an internal interface I and an internal circuit 1, wherein,
The internal circuit 1 is used for realizing the transceiving function of the chip, and the internal interface I is an interface externally provided by the internal circuit 1 and is used for connecting other sub-chips in the three-dimensional chip so as to realize the communication between the internal circuit 1 and the other sub-chips of the chip.
In this embodiment, the internal circuit 1 is connected to the internal interface I through an electrostatic discharge circuit (i.e., an Electro-STATIC DISCHARGE ELECTRIC circuit, hereinafter referred to as ESD circuit 2), and the ESD circuit 2 is used to discharge electrostatic charges injected from the internal interface I.
It should be noted that, when the three-dimensional chip leaves the factory and interacts with the customer hand, there are often damage situations, when the three-dimensional chip has a damage event, a person skilled in the art will usually pay attention to whether there is a problem on the chip itself and whether an ESD event has occurred on the external interface, but the internal interface I of the sub-chip that does not pay attention to the interior of the three-dimensional chip will also be damaged due to the occurrence of the ESD event, so that the three-dimensional chip assembled later is damaged, and the following problems are caused, which cause that the person skilled in the art cannot pay attention to the problem:
The external interface of the first three-dimensional chip and the internal interface I provided by the sub-chip inside the three-dimensional chip are damaged after the ESD event occurs, and no difference exists.
Secondly, it appears to those skilled in the art that the external interface of the three-dimensional chip has a possibility of ESD event, and the internal interface I is not in contact with the outside because it is packaged inside, so that no ESD event occurs, and further, when an ESD event occurs, the bias will cause those skilled in the art to put the focus on other reasons, without consideration, and the internal interface I may also have an ESD event.
Based on this, the applicant's findings: in the process of connecting the internal interface I of the sub-chip with the internal interfaces I of other sub-chips to assemble the three-dimensional chip, the sub-chip and external assembly equipment are in direct contact, in the contact process, an ESD (Electro-STATIC DISCHARGE) event can be easily generated on the internal interface I of the sub-chip, and the ESD event can generate instant large voltage and large current to destroy an internal functional circuit, so that the function of the sub-chip is invalid. Based on the finding, the application aims at the sub-chip forming the inside of the three-dimensional chip, and the ESD circuit 2 is connected between the internal circuit 1 and the internal interface I, and the ESD circuit 2 can release the static charge poured from the internal interface I when the sub-chip generates an ESD event in the assembling process, so that the internal circuit connected with the internal interface in the sub-chip can be prevented from being damaged, and the technical problem that the three-dimensional chip in the prior art is imperfect in electrostatic protection and has poor reliability is solved.
Further, the sub-chips for assembling the three-dimensional chip may involve the following three interfaces in the cascade process using the external device: input-output interfaces for both input and output signals, such as: the I1 interface in fig. 2 is an output interface for outputting signals only, for example: the I2 interface in fig. 2, and an input interface for inputting signals only, for example: in the interface I3 in fig. 2, static electricity is easily introduced at these interfaces, which causes chip damage, so that the ESD circuit 2 can be provided for electrostatic protection between these internal interfaces I and the corresponding internal circuits 1.
Thus, alternatively, the number of the internal circuits 1 may be one or plural, and a single internal circuit 1 may include any one of the transceiver circuit 11, the transmitter circuit 12, and the receiver circuit 13. Each internal circuit 1 is respectively corresponding to an internal interface I and an ESD circuit 2, and for convenience of description, the internal interface I corresponding to the transceiver circuit 11 is hereinafter referred to as an input/output interface I1; the internal interface I corresponding to the receiving circuit 13 is hereinafter referred to as an input interface I3; the internal interface I corresponding to the transmission circuit 12 is hereinafter referred to as an output interface I2. The ESD circuit 2 corresponding to the transceiver circuit 11 is hereinafter referred to as a first protection circuit 21; the ESD circuits 2 corresponding to the transmission circuits 12 are hereinafter collectively referred to as second protection circuits 22; the ESD circuit 2 corresponding to the reception circuit 13 is hereinafter referred to as a third protection circuit 23.
Here, the transceiver circuit 11 refers to a circuit for realizing both the receiving function and the transmitting function of the chip, and as an example, the transceiver circuit 11 includes a receiver RX and a transmitter TX, and an input terminal of the receiver RX is connected to an output terminal of the transmitter TX to realize the receiving and transmitting functions of the chip. The receiving circuit 13 here refers to a circuit for realizing a receiving function of a chip, and as an example, the receiving circuit 13 may include a receiver RX. The transmission circuit 12 herein refers to a circuit for realizing a transmission function of a chip, and as an example, the transmission circuit 12 may include a transmitter TX.
When the internal circuit 1 includes the transceiver circuit 11, the transceiver circuit 11 is connected to the input-output interface I1 through the first protection circuit 21, and/or
When the internal circuit 1 includes the transmitting circuit 12, the transmitting circuit 12 is connected to the output interface I2 through the second protection circuit 22, and/or
When the internal circuit 1 includes the receiving circuit 13, the receiving circuit 13 is connected to the input interface I3 through the third protection circuit 23.
More specifically, the first protection circuit 21, the second protection circuit 22, and the third protection circuit 23 may be any of the following three examples of the ESD circuit 2, and for convenience of description, the connection points of the internal circuit 1 and the corresponding internal interface I are collectively referred to as protection points.
As shown in fig. 3, in a first example, the ESD circuit 2 includes: a first diode (e.g., diode D0, diode D2, diode D4 in fig. 3), a second diode (e.g., diode D1, diode D3, diode D5 in fig. 3), and a bi-directional ESD circuit (not shown in the figure, which is a very existing circuit, not described in detail herein), wherein the cathode of the first diode is connected to vdd, the second diode is connected to vss, the bi-directional ESD circuit is disposed between vdd and vss, and the anode of the first diode and the anode of the second diode are connected to a guard point.
Electrostatic discharge process: taking as an example when a chip is interconnected with other sub-chips, an ESD event is generated on the I1 interface. When a forward ESD voltage is generated between the I1 interface and the vdd, namely, the voltage of the I1 interface is higher than that of the vdd, the diode D0 is conducted, the current between the I1 interface and the vdd is discharged, and the voltage between the I1 interface and the vdd is reduced, so that the internal circuit 1 is protected. When negative ESD voltage is generated between the I1 interface and vdd, i.e. the I1 interface voltage is lower than vdd, because there is no voltage on vss (vss is suspended), diode D1 is turned on and the bidirectional ESD circuit between vss and vdd is turned on, current between the I1 interface and vdd is discharged, and the voltage between the I1 interface and vdd is reduced, thereby protecting internal circuit 1. When a forward ESD voltage is generated between the I1 interface and the vss, that is, the I1 interface voltage is higher than the vss, because no voltage is applied to the vdd (the vdd is suspended), the diode D0 is conducted, a bidirectional ESD circuit between the vdd and the vss is conducted, the current between the I1 interface and the vss is discharged, and the voltage between the I1 interface and the vss is reduced; when a negative ESD voltage is generated between the I1 interface and vss, i.e., the I1 interface voltage is lower than vss, the diode D1 is turned on to bleed the current between the I1 interface and vss, reducing the voltage between the I1 interface and vss. ESD events generated on other interfaces will also have corresponding bleed paths.
As shown in fig. 4, in a second example, the ESD circuit 2 includes: an NPN transistor (such as transistor T0, transistor T2, and transistor T4 in fig. 4), a PNP transistor (such as transistor T1, transistor T3, and transistor T5 in fig. 4), and a bi-directional ESD circuit (not shown in the drawings, which is a very existing circuit and will not be described here), wherein a base of the NPN transistor is connected to vss, a collector of the NPN transistor is connected to vdd, a base of the PNP transistor is connected to vdd, a collector of the NPN transistor is connected to vss, the bi-directional ESD circuit is disposed between vdd and vss, and an emitter of the NPN transistor and an emitter of the PNP transistor are both connected to a protection point.
Electrostatic discharge process: taking as an example when a chip is interconnected with other sub-chips, an ESD event is generated on the I1 interface. When a forward ESD voltage is generated between the I1 interface and the vdd, namely, the voltage of the I1 interface is higher than that of the vdd, the triode T0 is conducted, the current between the I1 interface and the vdd is discharged, and the voltage between the I1 interface and the vdd is reduced, so that the internal circuit 1 is protected. When negative ESD voltage is generated between the I1 interface and vdd, i.e. the I1 interface voltage is lower than vdd, because there is no voltage on vss (vss is suspended), the triode T1 is turned on and the bidirectional ESD circuit between vss and vdd is turned on, the current between the I1 interface and vdd is discharged, and the voltage between the I1 interface and vdd is reduced, thereby playing a role in protecting the internal circuit 1. When a forward ESD voltage is generated between the I1 interface and the vss, namely the I1 interface voltage is higher than the vss, because no voltage is arranged on the vdd (the vdd is suspended), the triode T0 is conducted, a bidirectional ESD circuit between the vdd and the vss is conducted, the current between the I1 interface and the vss is discharged, and the voltage between the I1 interface and the vss is reduced; when negative ESD voltage is generated between the I1 interface and the vss, namely the voltage of the I1 interface is lower than the vss, the triode T1 is conducted to discharge current between the I1 interface and the vss, and the voltage between the I1 interface and the vss is reduced. ESD events generated on other interfaces will also have corresponding bleed paths.
As shown in fig. 5, in a third example, the ESD circuit 2 includes: the first NMOS transistor (e.g., transistor M0, transistor M2, and transistor M4 in fig. 5), the second NMOS transistor (e.g., transistor M1, transistor M3, and transistor M5 in fig. 5), and the bidirectional ESD circuit (not shown, which is a very existing circuit and will not be described here again), wherein the gate and drain of the first NMOS transistor are connected to vdd, the gate and source of the second NMOS transistor are connected to vss, the source of the first NMOS transistor and the drain of the second NMOS transistor are connected to the guard point, and the bidirectional ESD circuit is disposed between vdd and vss.
Electrostatic discharge process: taking as an example when a chip is interconnected with other sub-chips, an ESD event is generated on the I1 interface. When a forward ESD voltage is generated between the I1 interface and vdd, i.e. the I1 interface voltage is higher than vdd, the transistor M0 is turned on to discharge the current between the I1 interface and vdd, so that the voltage between the I1 interface and vdd is reduced, and the internal circuit 1 is protected. When negative ESD voltage is generated between the I1 interface and vdd, i.e. the I1 interface voltage is lower than vdd, because there is no voltage on vss (vss is suspended), the transistor M1 is turned on and the bidirectional ESD circuit between vss and vdd is turned on, so that the current between the I1 interface and vdd is discharged, and the voltage between the I1 interface and vdd is reduced, thereby protecting the internal circuit 1. When a forward ESD voltage is generated between the I1 interface and the vss, that is, the I1 interface voltage is higher than the vss, because no voltage is present on the vdd (vdd is suspended), the transistor M0 is conducted, and the bidirectional ESD circuit between the vdd and the vss is conducted, the current between the I1 interface and the vss is discharged, and the voltage between the I1 interface and the vss is reduced; when negative ESD voltage is generated between the I1 interface and vss, i.e. the I1 interface voltage is lower than vss, the transistor M1 is turned on to bleed current between the I1 interface and vss, reduce the voltage between the I1 interface and vss, and ESD events generated on other interfaces will have corresponding bleed paths.
The first protection circuit 21, the second protection circuit 22, and the third protection circuit 23 may be any of the ESD circuits 2 in the above three examples, and may be the same or different, and the bidirectional ESD circuits provided between vdd and vss in the above three examples may be shared.
As an alternative embodiment, the internal interface I connects other sub-chips by Hybrid Bonding (HB) in comparison with the through silicon via (Through Silicon Via, abbreviated as TSV) technology in the prior art, which generally requires complete chip penetration and has only a few pillars connected between chips, which is very thick, the hybrid bonding technology in this embodiment does not require chip penetration and can create very many connecting pillars.
It should be noted that the internal interface I may also be connected to other sub-chips by other connection methods, and is not limited herein, as long as the metal layer of the chip can be directly connected to the metal layer of other sub-chips.
As an alternative embodiment, the chip is a memory chip or a logic chip.
The technical scheme provided by the embodiment of the application at least has the following technical effects or advantages:
The applicant found that in the process of connecting the internal interface I of the sub-chip with the internal interfaces I of other sub-chips to assemble the three-dimensional chip, the sub-chip and the external assembly device are in direct contact, and in the process of contact, an ESD (Electro-STATIC DISCHARGE) event is easily generated on the internal interface I of the sub-chip, and the ESD event can generate instantaneous large voltage and large current to destroy the internal functional circuit, thereby causing the functional failure of the sub-chip. Based on the finding, the application aims at the sub-chip forming the inside of the three-dimensional chip, and the ESD circuit 2 is connected between the internal circuit 1 and the internal interface I, and the ESD circuit 2 can release the electrostatic charge poured from the internal interface I when the sub-chip generates an ESD event in the assembling process, so that the sub-chip can be prevented from being damaged, and the technical problem of poor reliability of the three-dimensional chip in the electrostatic protection aspect in the prior art is solved.
Example two
As shown in fig. 6, this embodiment provides a three-dimensional chip including two chips as in any one of the first embodiment, and for convenience of explanation, the two chips are a first chip S01 and a second chip S02, respectively, and the internal interface I of the first chip S01 and the second chip S02 are connected to each other through the respective internal interfaces I, and it should be understood that, even though the two chips are distinguished in terms of name, the first chip S01 and the second chip S02 each have the structure and the function of the chip provided in the first embodiment.
In an actual implementation process, the first chip S01 and the second chip S02 may be a memory chip or a logic chip.
Applicants' discovery: in the process of connecting the internal interface I of the first chip S01 and the internal interface I of the second chip S02 to assemble the three-dimensional chip, the internal interface I of the first chip S01, the internal interface I of the second chip S02 and external assembly equipment are in direct contact, in the contact process, an ESD (Electro-STATIC DISCHARGE) event can be easily generated on the internal interface I, and the ESD event can generate instant large voltage and large current to damage an internal functional circuit, so that the function of a sub-chip is invalid. Based on the finding, the application aims at the first chip S01 and the second chip S02 which form the inside of the three-dimensional chip, and the ESD circuit 2 is connected between the internal circuit 1 and the internal interface I, and the ESD circuit 2 can release static charges poured in from the internal interface I when the sub-chip has an ESD event in the assembling process, so that the sub-chip can be prevented from being damaged, and the technical problem that the three-dimensional chip in the prior art is imperfect in electrostatic protection and has poor reliability is solved.
As an alternative embodiment, as shown in fig. 7, each internal circuit 1 of the first chip S01 corresponds to one internal interface I, each internal circuit 1 of the second chip S02 corresponds to one internal interface I, wherein,
When the internal circuit 1 of the first chip S01 includes the transceiver circuit 11, the internal circuit 1 of the second chip S02 includes the transceiver circuit 11, and the internal interface I corresponding to the transceiver circuit 11 of the first chip S01 is correspondingly connected to the internal interface I corresponding to the transceiver circuit 11 of the second chip S02;
when the internal circuit 1 of the first chip S01 includes the receiving circuit 13, the internal circuit 1 of the second chip S02 includes the transmitting circuit 12, and the internal interface I corresponding to the receiving circuit 13 of the first chip S01 is correspondingly connected to the internal interface I corresponding to the transmitting circuit 12 of the second chip S02;
When the internal circuit 1 of the first chip S01 includes the transmitting circuit 12, the internal circuit 1 of the second chip S02 includes the receiving circuit 13, and the internal interface I corresponding to the transmitting circuit 12 of the first chip S01 is correspondingly connected to the internal interface I corresponding to the receiving circuit 13 of the second chip S02.
As an alternative embodiment, as shown in fig. 7, the internal interface I of the first chip S01 is connected to the internal interface I of the second chip S02 by Hybrid Bonding (HB), which generally requires complete chip penetration and few pillars connected between chips, but is very thick, compared to the through silicon via (Through Silicon Via, abbreviated as TSV) technology in the prior art, which does not require chip penetration and can generate very many connecting pillars.
The internal interface I of the first chip S01 may be connected to the internal interface I of the second chip S02 by other connection methods, as long as the metal layer of the first chip S01 and the metal layer of the second chip S02 can be directly connected.
The technical scheme provided by the embodiment of the application at least has the following technical effects or advantages:
the applicant found that in the process of connecting the internal interface I of the sub-chip with the internal interfaces I of other sub-chips to assemble the three-dimensional chip, the sub-chip and the external assembly device are in direct contact, and in the process of contact, an ESD (Electro-STATIC DISCHARGE) event is easily generated on the internal interface I of the sub-chip, and the ESD event can generate instantaneous large voltage and large current to destroy the internal functional circuit, thereby causing the functional failure of the sub-chip. Based on the finding, the application aims at the sub-chip forming the inside of the three-dimensional chip, and the electrostatic discharge circuit is connected between the internal circuit 1 and the internal interface I, so that the electrostatic discharge circuit enables the sub-chip to generate an ESD event in the process of assembling the three-dimensional chip, and electrostatic charges poured from the internal interface I can be discharged, thereby avoiding the sub-chip from being damaged, and solving the technical problem of poor reliability of the three-dimensional chip in the aspect of electrostatic protection in the prior art.
Example III
As shown in fig. 8, the present embodiment provides an electronic device including a chip serving as a sub-chip of a three-dimensional chip, the chip including an internal interface I and an internal circuit 1, the internal circuit 1 being for implementing a transceiving function of the chip, the internal interface 3 being for connecting other sub-chips in the three-dimensional chip, wherein the internal circuit 1 is connected to the internal interface I through an ESD circuit 2, the ESD circuit 2 being for discharging electrostatic charges injected from the internal interface I.
In a specific implementation process, the electronic device may further include a chip according to any one of the embodiments.
Example IV
As shown in fig. 9, the present embodiment provides a method for manufacturing a three-dimensional chip, including:
Step 301: providing two chips, wherein the chips comprise an internal interface and an internal circuit, the internal circuit is used for realizing the transceiving function of the chips, the internal interface of a first chip in the two chips is used for connecting the internal interface of a second chip in the two chips, the internal circuit is connected to the internal interface through an electrostatic discharge circuit, and the electrostatic discharge circuit is used for discharging electrostatic charges poured from the internal interface;
step 302: the two chips are connected through respective internal interfaces.
As an alternative embodiment, as shown in fig. 10-12, step 302 includes:
growing a first bonding post a on the internal interface I of the first chip (i.e., metal layer TM1 in fig. 10);
Growing a second bonding post B on the internal interface I of the second chip (i.e., metal layer TM2 in fig. 11);
The first chip and the second chip are subjected to hybrid bonding through the first bonding post a and the second bonding post B, and the three-dimensional chip is formed as shown in fig. 12.
In this embodiment, an electrostatic discharge circuit is connected between the internal circuit and the internal interface of the sub-chip for assembling the three-dimensional chip, and the electrostatic discharge circuit enables an ESD event to occur during the process of assembling the three-dimensional chip, so that electrostatic charges poured from the internal interface can be discharged, thereby avoiding the sub-chip from being damaged, and solving the technical problem of poor reliability of the three-dimensional chip in the aspect of electrostatic protection in the prior art.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (9)

1. A chip for use as a sub-chip of a three-dimensional chip, the chip comprising:
An internal interface and an internal circuit, wherein the internal circuit is used for realizing the receiving and transmitting functions of the chip, the internal interface is used for connecting other sub-chips in the three-dimensional chip, and the internal interface is used for connecting the other sub-chips in the three-dimensional chip,
The internal circuit is connected to the internal interface through an electrostatic discharge circuit for discharging electrostatic charges injected from the internal interface, wherein,
The number of the internal circuits is one or more, each internal circuit is respectively corresponding to one internal interface and one electrostatic discharge circuit, and the internal interfaces are connected with the other sub-chips in a hybrid bonding mode.
2. The chip of claim 1, wherein the number of internal circuits is one or more, and a single internal circuit comprises any one of a transceiver circuit, a transmitter circuit, and a receiver circuit, wherein,
The receiving and transmitting circuit is used for realizing the receiving function and the transmitting function of the chip;
the receiving circuit is used for realizing the receiving function of the chip;
the transmitting circuit is used for realizing the transmitting function of the chip.
3. The chip of claim 1, wherein the chip is a memory chip or a logic chip.
4. A three-dimensional chip comprising two chips according to any one of claims 1-3, wherein two of said chips are interconnected by respective ones of said internal interfaces.
5. The three-dimensional chip of claim 4, wherein each of said internal circuits corresponds to a respective one of said internal interfaces;
The two chips are a first chip and a second chip respectively, wherein,
When the internal circuit of the first chip comprises a transceiver circuit, the internal circuit of the second chip comprises the transceiver circuit, and an internal interface corresponding to the transceiver circuit of the first chip is correspondingly connected with an internal interface corresponding to the transceiver circuit of the second chip, wherein the transceiver circuit is used for realizing the receiving function and the transmitting function of the chip;
When the internal circuit of the first chip comprises a receiving circuit, the internal circuit of the second chip comprises a transmitting circuit, the internal interface corresponding to the receiving circuit of the first chip is correspondingly connected with the internal interface corresponding to the transmitting circuit of the second chip, the receiving circuit is used for realizing the receiving function of the chip, and the transmitting circuit is used for realizing the transmitting function of the chip;
when the internal circuit of the first chip comprises the transmitting circuit, the internal circuit of the second chip comprises the receiving circuit, and the internal interface corresponding to the transmitting circuit of the first chip is correspondingly connected with the internal interface corresponding to the receiving circuit of the second chip.
6. The three-dimensional chip of claim 5, wherein the internal interface of the first chip is connected to the internal interface of the second chip by hybrid bonding.
7. An electronic device, comprising: the chip of any one of claims 1-6.
8. A method of manufacturing a three-dimensional chip, comprising:
Providing two chips, wherein the chips comprise an internal interface and an internal circuit, the internal circuit is used for realizing the transceiving function of the chips, the internal interface of a first chip of the two chips is used for connecting the internal interface of a second chip of the two chips, the internal circuit is connected to the internal interface through an electrostatic discharge circuit, and the electrostatic discharge circuit is used for discharging electrostatic charges filled from the internal interface;
And connecting the two chips through the respective internal interfaces.
9. The method of manufacturing a three-dimensional chip according to claim 8, wherein said connecting the two chips through the respective internal interfaces includes:
Growing a first bond post on an internal interface of the first chip;
Growing a second bond post on an internal interface of the second chip;
and performing hybrid bonding on the first chip and the second chip through the first bonding post and the second bonding post.
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