CN112507491A - Parameterized unit and implementation method thereof - Google Patents

Parameterized unit and implementation method thereof Download PDF

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CN112507491A
CN112507491A CN202011471523.6A CN202011471523A CN112507491A CN 112507491 A CN112507491 A CN 112507491A CN 202011471523 A CN202011471523 A CN 202011471523A CN 112507491 A CN112507491 A CN 112507491A
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structures
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layer setting
parameterization unit
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CN112507491B (en
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江照燿
刘学刚
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Quanxin Integrated Circuit Manufacturing Jinan Co Ltd
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Abstract

The invention provides a parameterized unit and an implementation method thereof, wherein the method comprises the following steps: providing a parameterization unit comprising a plurality of first structures and a plurality of second structures, the first structures and the second structures being repetitive structures, the first structures and the second structures differing in function; and changing the layer setting of the first structure and/or the second structure to make the function of the first structure identical to that of the second structure, and/or to make the function of the second structure identical to that of the first structure, so that the first structure and/or the second structure and other structures form a required device, thereby realizing the balance of the characteristics of the device and the area of the device, namely obtaining the optimal device characteristics with the least waste of the area.

Description

Parameterized unit and implementation method thereof
Technical Field
The present invention relates to the field of semiconductor integrated circuit manufacturing technology, and more particularly, to a parameterized cell and a method for implementing the same.
Background
With the development of the process, the introduction of the finfet and the multi-Patterning Technology (MPT) has become the mainstream process Technology under twenty nm. Although these mainstream technologies continue moore's law, they also increase the complexity of the process, and the foundry has to define the more strict Design Rule (RDR) in the Design Rule manual.
The traditional parameterization unit is designed according to a design rule manual, and the optimal device characteristics can be obtained with the least waste of area. However, the addition of restrictive design rules, reflected in layout design, may result in more and more repetitive structures within the parameterized cell. Although the characteristics of the device are better as the number of the repeated structures is larger, the defect of wasting more area is brought about. Based on this, how to balance the characteristics of the device and the area of the device is one of the problems that those skilled in the art are urgently required to solve.
Disclosure of Invention
In view of the above, the present invention provides a parameterization unit and a method for implementing the same, so as to adjust a repetitive structure in the parameterization unit and obtain an optimal device characteristic with minimal waste of area.
In order to achieve the purpose, the invention provides the following technical scheme:
a method for realizing a parameterized unit comprises the following steps:
providing a parameterization unit comprising a plurality of first structures and a plurality of second structures, the first structures and the second structures being repetitive structures, the first structures and the second structures differing in function;
changing the layer setting of the first structure and/or the second structure to make the function of the first structure identical to that of the second structure, and/or to make the function of the second structure identical to that of the first structure;
and forming the first structure and/or the second structure and other structures into a required device.
Optionally, the parameterization unit comprises a first device comprising a plurality of first structures and a plurality of second structures; changing the layer setting of the first structure and/or the second structure includes:
changing the layer settings of two adjacent first structures to ensure that the functions of the two adjacent first structures are the same as the functions of the second structure;
the means required to form the first and/or second structure with other structures includes:
and cutting off the connecting structure between the two adjacent first structures, so that one of the two adjacent first structures forms a required second device with the other structure, and the other of the two adjacent first structures forms a required third device with the other structure.
Optionally, the parameterization unit comprises a first device and a second device, each comprising a plurality of first structures and a plurality of second structures;
changing the layer setting of the first structure and/or the second structure includes:
changing the layer setting of a part of second structures in the first device to enable the functions of the part of second structures in the first device to be the same as the functions of the first structures in the second device;
changing the layer setting of a part of second structures in the second device to enable the functions of the part of second structures in the second device to be the same as the functions of the first structures in the first device;
the means required to form the first and/or second structure with other structures includes:
and combining part of the second structure in the first device with the first structure of the second device, combining part of the second structure in the second device with the first structure in the first device, and enabling the first device and the second device to form a required third device.
Optionally, the parameterization unit comprises a first device and a second device, each comprising a plurality of first structures and a plurality of second structures;
changing the layer setting of the first structure and/or the second structure includes:
changing the layer setting of a part of second structures in the first device to enable the functions of the part of second structures in the first device to be the same as the functions of the first structures in the second device;
changing the layer setting of a part of second structures in the second device to enable the functions of the part of second structures in the second device to be the same as the functions of the first structures in the first device;
the means required to form the first and/or second structure with other structures includes:
and forming a connecting structure between parts of the second structures in the first device, forming a connecting structure between parts of the second structures in the second device, and forming a connecting structure between parts of the second structures in the first device and parts of the second structures in the second device, so that the first device and the second device form a required third device.
Optionally, forming the connection structure comprises:
forming a connection structure by designing a parameterization unit;
alternatively, the connection structure is formed by a layout tool.
Optionally, the first structure comprises a gate of a fin field effect transistor, the second structure comprises a dummy gate of the fin field effect transistor, and the connection structure comprises a fin structure.
A parameterization unit implemented using the method as claimed in any one of the preceding claims.
Compared with the prior art, the technical scheme provided by the invention has the following advantages:
the parameterization unit and the implementation method thereof provided by the invention have the advantages that since the parameterization unit comprises a plurality of first structures and a plurality of second structures, the first structures and the second structures are repetitive structures, and the functions of the first structures and the second structures are different, the functions of the first structures and the second structures can be the same by changing the layer settings of the first structures and/or the second structures, and/or the functions of the second structures and the first structures are the same, and the first structures and/or the second structures and other structures form required devices, so that the balance between the device characteristics and the device areas is realized, namely the optimal device characteristics are obtained with the minimum waste of the areas.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram of a parameterized cell including a FinFET;
FIG. 2 is a flowchart of a method for implementing a parameterization unit according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a parameterization unit before layer settings are changed according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of the parameterization unit shown in FIG. 3 after the parameterization unit changes the layer settings;
FIG. 5 is a schematic structural diagram of a parameterization unit before layer settings are changed according to another embodiment of the present invention;
fig. 6 is a schematic structural diagram after changing layer settings of the parameter unit in fig. 5 according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram illustrating a structure after changing a layer setting of a parameter unit in fig. 5 according to another embodiment of the present invention;
fig. 8 is a schematic structural diagram after changing the layer setting of the parameter unit in fig. 5 according to another embodiment of the present invention.
Detailed Description
As in the background art, the greater the number of repeated structures, the better the device characteristics. As shown in fig. 1, in the finfet of the parameterized cell designed according to the design rule manual with restrictive design rules, a dummy gate 11 is provided around a gate 10, and the dummy gate 11 and the gate 10 have the same structure but different layer settings and different functions.
Although problems such as LDE (Layout Dependent Effect) caused by the process can be alleviated by the dummy gate, and the more the number of the dummy gates is, the better the characteristics of the device are, however, the more the sacrificial area is, the more the wasted area is.
Based on this, the present invention provides a parameterized block and an implementation method thereof, so as to overcome the above problems in the prior art, including:
providing a parameterization unit, wherein the parameterization unit comprises a plurality of first structures and a plurality of second structures, the first structures and the second structures are repeated structures, and the functions of the first structures and the second structures are different;
changing the layer setting of the first structure and/or the second structure to make the function of the first structure identical to that of the second structure, and/or to make the function of the second structure identical to that of the first structure;
the first structure and/or the second structure and other structures are formed into the desired device.
The parameterization unit and the implementation method thereof provided by the invention have the advantages that the function of the first structure is the same as that of the second structure by changing the layer setting of the first structure and/or the second structure, and/or the function of the second structure is the same as that of the first structure, and the first structure and/or the second structure and other structures form a required device, so that the balance between the characteristics of the device and the area of the device can be realized, namely, the optimal device characteristics can be obtained under the condition of least waste of the area.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, so that the above is the core idea of the present invention, and the above objects, features and advantages of the present invention can be more clearly understood. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a method for implementing a parameterized unit, as shown in fig. 2, including:
s101: providing a parameterization unit, wherein the parameterization unit comprises a plurality of first structures and a plurality of second structures, the first structures and the second structures are repeated structures, and the functions of the first structures and the second structures are different;
s102: changing the layer setting of the first structure and/or the second structure to make the function of the first structure identical to that of the second structure, and/or to make the function of the second structure identical to that of the first structure;
s103: the first structure and/or the second structure and other structures are formed into the desired device.
In the embodiment of the present invention, the parameterized unit is a finfet as an example, but the present invention is not limited thereto, and the method provided in the embodiment of the present invention may be adopted to adjust the repetitive structure in other parameterized units.
As shown in fig. 3, the parameterization unit includes a plurality of first structures 21 and a plurality of second structures 22, the first structures 21 are gates of finfets, the second structures 22 are dummy gates of finfets, the first structures 21 and the second structures 22 are repeated structures, and the first structures 21 and the second structures 22 have different layer settings, that is, the gate and the dummy gates have the same structure and are repeated structures, but have different layer settings and different functions.
The gate, the source and the drain in the fin field effect transistor respectively cover part of the fin structure, a gate dielectric layer (not shown) is arranged between the gate and the fin structure, the source is electrically connected with a source region on the fin structure, the drain is electrically connected with a drain region on the fin structure, and the source region and the drain region are formed by doping the fin structure. The dummy gate and the fin structure are not connected.
The layer settings of the first structure 21 and/or the second structure 22 are changed so that the first structure 21 has the same function as the second structure 22, and/or the second structure 22 has the same function as the first structure 21 so that the first structure 21 and/or the second structure 22 and other structures form the required devices.
That is, the layer setting of the first structure 21 is changed, so that the function of the first structure 21 is the same as that of the second structure 22, and the first structure 21 and other structures form required devices; or changing the layer setting of the second structure 22 to make the function of the second structure 22 the same as that of the first structure 21, so that the second structure 22 and other structures form a required device; alternatively, the layer settings of the first structure 21 and the second structure 22 are changed, so that the function of the first structure 21 is the same as that of the second structure 22, the function of the second structure 22 is the same as that of the first structure 21, and the first structure 21, the second structure 22 and other structures form a desired device.
In some embodiments of the invention, as shown in fig. 3, the parameterization unit comprises a first device 1, the first device 1 comprising a plurality of first structures 21 and a plurality of second structures 22. Changing the layer settings of the first structure 21 and/or the second structure 22 comprises: the layer settings of two adjacent first structures 21 in the plurality of first structures 21 are changed, so that the functions of the two adjacent first structures 21 are the same as the functions of the second structures 22.
The means required to form the first structure 21 and/or the second structure 22 with other structures include: the connecting structure 23 between two adjacent first structures 21 is cut off, so that one first structure 21 of the two adjacent first structures 21 and the other structures form a required second device, and the other first structure 21 of the two adjacent first structures 21 and the other structures form a required third device.
As shown in fig. 4, when the first structure 21 is a gate of a finfet and the second structure 22 is a dummy gate, the layer settings of two adjacent gates within the dashed line frame are changed so that the functions of the two adjacent gates are the same as those of the dummy gate, even if the two adjacent gates become dummy gates. And then cutting off the connecting structure 23 between two adjacent dummy gates in the dotted line frame, wherein the connecting structure 23 comprises a fin structure. Then, one of the two adjacent dummy gates and the other structure on the right side thereof form a required second device 2, and one of the two adjacent dummy gates and the other structure on the left side thereof form a required third device 3.
In further embodiments of the present invention, as shown in fig. 5, the parameterization unit includes a first device 4 and a second device 5, each of the first device 4 and the second device 5 includes a plurality of first structures 21 and a plurality of second structures 22, and changing the layer settings of the first structures 21 and/or the second structures 22 includes:
changing the layer setting of a part of the second structure 22 in the first device 4 to make the function of the part of the second structure 22 in the first device 4 the same as the function of the first structure 21 in the second device 5;
changing the layer setting of part of the second structure 22 in the second device 5 to make the function of part of the second structure 22 in the second device 5 the same as the function of the first structure 21 in the first device 4;
the means required to form the first structure 21 and/or the second structure 22 with other structures include:
part of the second structure 22 in the first device 4 is merged with the first structure 21 of the second device 5 and part of the second structure 22 in the second device 5 is merged with the first structure 21 in the first device 4, so that the first device 4 and the second device 5 form the desired third device 6.
As shown in fig. 5, the layer setting of a part of the dummy gate in the first device 4 is changed, so that the function of the part of the dummy gate in the first device 4 is the same as that of the gate in the second device 5, that is, the part of the dummy gate in the first device 4 is the gate;
changing the layer setting of part of the virtual grid in the second device 5 to make the function of part of the virtual grid in the second device 5 the same as that of the grid in the first device 4, namely, making part of the virtual grid in the second device 5 become the grid;
then, the first device 4 is moved to the right and the second device 5 is moved to the left, as shown in fig. 6, the second structure 22 within the dashed box of the first device 4 is merged with the first structure 21 in the second device 5, and the second structure 22 within the dashed box of the second device 5 is merged with the first structure 21 in the first device 4, so that the first device 4 and the second device 5 form the desired third device 6.
Of course, the present invention is not limited thereto, and in another embodiment, on the basis of the structure shown in fig. 5, as shown in fig. 7, the first device 4 and the second device 5 do not move, the connection structure 23 is formed between a part of the second structure 22 in the first device 4, the connection structure 23 is formed between a part of the second structure 22 in the second device 5, and the connection structure 23 is formed between a part of the second structure 22 in the first device 4 and a part of the second structure 22 in the second device 5, so that the first device 4 and the second device 5 form the required third device 7.
That is, a fin structure is formed between part of the dummy gates in the first device 4, a fin structure is formed between part of the dummy gates in the second device 5, and a fin structure is formed between part of the dummy gates in the first device 4 and part of the dummy gates in the second device 5, so that the first device 4 and the second device 5 form the required third device 7.
It should be noted that in other embodiments of the present invention, on the basis of the structure shown in fig. 5, as shown in fig. 8, the first device 4 may also be moved to the right, and the second device 5 may be moved to the left, so that the second structure 22 in the dashed frame of the first device 4 is merged with the second structure 22 in the second device 5, and a connection structure 23 is formed between the second structures 22 to form a desired device, which is not described herein again.
In some embodiments of the present invention, forming the connection structure 23 comprises: forming the connection structure 23 by designing a parameterization unit; alternatively, the connection structure 23 is formed by a layout tool. Of course, the invention is not limited to this, and in other embodiments, the connection structure 23 may be generated by a layout engineer.
The embodiment of the invention also provides a parameterization unit which is realized by adopting the method provided by any one of the embodiments.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (7)

1. A method for implementing a parameterized unit, comprising:
providing a parameterization unit comprising a plurality of first structures and a plurality of second structures, the first structures and the second structures being repetitive structures, the first structures and the second structures differing in function;
changing the layer setting of the first structure and/or the second structure to make the function of the first structure identical to that of the second structure, and/or to make the function of the second structure identical to that of the first structure;
and forming the first structure and/or the second structure and other structures into a required device.
2. The method of claim 1, wherein the parameterization unit comprises a first device comprising a plurality of first structures and a plurality of second structures; changing the layer setting of the first structure and/or the second structure includes:
changing the layer settings of two adjacent first structures to ensure that the functions of the two adjacent first structures are the same as the functions of the second structure;
the means required to form the first and/or second structure with other structures includes:
and cutting off the connecting structure between the two adjacent first structures, so that one of the two adjacent first structures forms a required second device with the other structure, and the other of the two adjacent first structures forms a required third device with the other structure.
3. The method of claim 1, wherein the parameterization unit comprises a first device and a second device, each comprising a plurality of first structures and a plurality of second structures;
changing the layer setting of the first structure and/or the second structure includes:
changing the layer setting of a part of second structures in the first device to enable the functions of the part of second structures in the first device to be the same as the functions of the first structures in the second device;
changing the layer setting of a part of second structures in the second device to enable the functions of the part of second structures in the second device to be the same as the functions of the first structures in the first device;
the means required to form the first and/or second structure with other structures includes:
and combining part of the second structure in the first device with the first structure of the second device, combining part of the second structure in the second device with the first structure in the first device, and enabling the first device and the second device to form a required third device.
4. The method of claim 1, wherein the parameterization unit comprises a first device and a second device, each comprising a plurality of first structures and a plurality of second structures;
changing the layer setting of the first structure and/or the second structure includes:
changing the layer setting of a part of second structures in the first device to enable the functions of the part of second structures in the first device to be the same as the functions of the first structures in the second device;
changing the layer setting of a part of second structures in the second device to enable the functions of the part of second structures in the second device to be the same as the functions of the first structures in the first device;
the means required to form the first and/or second structure with other structures includes:
and forming a connecting structure between parts of the second structures in the first device, forming a connecting structure between parts of the second structures in the second device, and forming a connecting structure between parts of the second structures in the first device and parts of the second structures in the second device, so that the first device and the second device form a required third device.
5. The method of claim 4, wherein forming a connection structure comprises:
forming a connection structure by designing a parameterization unit;
alternatively, the connection structure is formed by a layout tool.
6. The method of claim 2, 3 or 4, wherein the first structure comprises a gate of a fin field effect transistor, the second structure comprises a dummy gate of the fin field effect transistor, and the connection structure comprises a fin structure.
7. A parameterization unit implemented by the method of any one of claims 1 to 6.
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