CN112506569B - Byte code executing method, byte code executing device and terminal equipment - Google Patents
Byte code executing method, byte code executing device and terminal equipment Download PDFInfo
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- CN112506569B CN112506569B CN202011465836.0A CN202011465836A CN112506569B CN 112506569 B CN112506569 B CN 112506569B CN 202011465836 A CN202011465836 A CN 202011465836A CN 112506569 B CN112506569 B CN 112506569B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/30134—Register stacks; shift registers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/321—Program or instruction counter, e.g. incrementing
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application is applicable to the technical field of computers, and provides a byte code executing method, a byte code executing device and terminal equipment, wherein the method comprises the following steps: acquiring a first byte code to be executed; converting the first byte code into a second byte code in a custom format, wherein the second byte code comprises an index corresponding to each read-write data operation in the execution process of the first byte code; determining a section of target memory based on the index, wherein the target memory comprises at least one virtual register, and each virtual register is identified by a different index; the second bytecode is executed based on virtual registers identified by respective indexes in the second bytecode. By the method, the performance of the virtual machine in interpreting and executing the byte codes can be improved.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a method for executing a byte code, a device for executing a byte code, a terminal device, and a computer readable storage medium.
Background
Byte-code (Byte-code) is a binary file consisting of a sequence of op code/data pairs, which contains the executable program, and is an intermediate code. The bytecode may be interpreted by a virtual machine. Currently, in the process of interpreting and executing byte codes, the memory used by the virtual machine is designed based on a stack structure. However, the performance of data reading and writing using the memory of the stack structure is very low.
Disclosure of Invention
In view of the foregoing, the present application provides a bytecode execution method, a bytecode execution device, a terminal device, and a computer-readable storage medium, which can improve performance of a virtual machine in interpreting and executing bytecodes.
In a first aspect, the present application provides a method for executing a bytecode, including:
acquiring a first byte code to be executed;
converting the first byte code into a second byte code with a custom format, wherein the second byte code comprises an index corresponding to each read-write data operation in the execution process of the first byte code;
determining a section of target memory based on the index, wherein the target memory comprises at least one virtual register, and each virtual register is identified by a different index;
and executing the second byte code based on the virtual register identified by each index in the second byte code.
In a second aspect, the present application provides a bytecode execution device, including:
an acquisition unit configured to acquire a first bytecode to be executed;
the conversion unit is used for converting the first byte code into a second byte code with a custom format, wherein the second byte code comprises an index corresponding to each read-write data operation in the execution process of the first byte code;
A determining unit, configured to determine a section of target memory based on the index, where the target memory includes at least one virtual register, and each virtual register is identified by a different index;
and the execution unit is used for executing the second byte codes based on the virtual registers identified by the indexes in the second byte codes.
In a third aspect, the present application provides a terminal device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the method as provided in the first aspect when executing the computer program.
In a fourth aspect, the present application provides a computer readable storage medium storing a computer program which, when executed by a processor, implements a method as provided in the first aspect.
In a fifth aspect, the present application provides a computer program product for causing a terminal device to carry out the method provided in the first aspect above, when the computer program product is run on the terminal device.
In the above-mentioned scheme, first byte codes to be executed are obtained first, the first byte codes are converted into second byte codes with a self-defined format, the second byte codes comprise indexes corresponding to each read-write data operation in the execution process of the first byte codes, then a section of target memory is determined based on the indexes, the target memory comprises at least one virtual register, each virtual register is identified by different indexes, and finally the second byte codes are executed based on the virtual registers identified by each index in the second byte codes. According to the method and the device, the first byte code to be executed is converted into the second byte code in the self-defined format, and the index corresponding to each read-write data operation in the execution process of the first byte code is added into the second byte code, so that the virtual register which is required to be used currently can be rapidly determined according to each index when the second byte code is interpreted and executed by the virtual machine, and the performance of the virtual machine for interpreting and executing the byte code can be improved. It will be appreciated that the advantages of the second to fifth aspects may be found in the relevant description of the first aspect, and are not described here again.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following description will briefly introduce the drawings that are needed in the embodiments or the description of the prior art, it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a method for executing byte codes according to an embodiment of the present application;
FIG. 2 is a block diagram of a bytecode execution device according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a terminal device provided in an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
As used in this specification and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".
In addition, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
Fig. 1 shows a flowchart of a method for executing a bytecode, which is provided in an embodiment of the present application, and the method for executing a bytecode is applied to a terminal device, and is described in detail as follows:
In the embodiment of the application, if a section of program source code needs to be executed, a user can compile the section of program source code into a byte code to be executed through a compiler, and the byte code can be recorded as a first byte code. For example, for a piece of Java program source code that needs to be executed, the user may compile the piece of Java program source code into WebAssembly (WASM) bytecode, i.e., the first bytecode.
In this embodiment of the present application, the first bytecode includes a plurality of instructions having a sequential execution order, and the first bytecode is executed, that is, the plurality of instructions in the first bytecode are executed. When executing an instruction, the virtual machine may need to perform one or more data reading and writing operations, where the data reading and writing operations include a data reading operation and a data writing operation. In order to improve the execution efficiency of the byte codes, the embodiment of the application reforms the first byte code and converts the first byte code into the second byte code in the custom format. The second byte code includes an index corresponding to each read-write data operation in the execution process of the first byte code, where the index is used to identify a virtual register, that is, a memory area in a memory of the terminal device. And determining the virtual register which is currently required to be used for data reading and writing operation according to the corresponding index.
It should be noted that, since the user actually needs to execute the first byte code to implement the function of the first byte code, it should be ensured that executing the second byte code can implement the function of the first byte code. The function of the byte code is determined by the operation code in the instruction, so that the second byte code and the first byte code can contain the same operation code, and the execution of the second byte code can be ensured to realize the function of the first byte code. Further, since the second byte code and the first byte code contain the same operation code, the read-write data operation in the execution process of the second byte code is the same as the read-write data operation in the execution process of the first byte code. When any one of the read-write data operations in the second byte code process is executed, the virtual machine can quickly determine the virtual register which is needed to be used currently by the read-write data operation according to the index corresponding to the read-write data operation.
Optionally, the step 102 specifically includes:
a1, traversing each instruction in the first byte code according to the instruction execution sequence;
a2, aiming at the current instruction, determining an index corresponding to the read-write data operation included in the current instruction according to the meaning of the current instruction;
a3, generating a new instruction according to an index corresponding to the read-write data operation included in the current instruction and an operation code of the current instruction;
and A4, serializing new instructions corresponding to the instructions in the first byte code to obtain a second byte code.
In the embodiment of the present application, each instruction in the first byte code may be traversed according to the instruction execution sequence of the first byte code. For example, assuming that the first byte code is a WASM byte code, since the length of the operation code in the WASM byte code is one byte, the data in the first byte code can be sequentially read, and the data can be converted into one instruction by reading the data with one byte length at a time. And for the currently traversed instruction, recording the instruction as a current instruction, and determining an index corresponding to each read-write data operation included in the current instruction according to the meaning of the current instruction. The meaning of the current instruction can be obtained according to the operation code of the current instruction, and the operation code of the current instruction is used for representing the operation characteristics and functions of the current instruction, namely the meaning of the current instruction. After determining the index corresponding to each data read-write operation included in the current instruction, generating a new instruction according to the index and the operation code of the current instruction, wherein the generated new instruction comprises the operation code of the current instruction and the index corresponding to each data read-write operation included in the current instruction.
For example, the operation code of the current instruction and the index corresponding to each data read-write operation included in the current instruction may be spliced to obtain the new instruction. The composition structure of the new instruction is value ID (4 bytes) +opcode (1 byte) +operants, wherein the value ID is an index corresponding to data writing operation included in the current instruction, and the length is 4 bytes; the opcode is the operation code of the current instruction, and the length is 1 byte; operands is the index corresponding to the read data operation included in the current instruction. It should be noted that if the data to be read by the data-reading operation is an immediate operand, the operands may be the immediate operand to be read by the data-reading operation, instead of the index corresponding to the data-reading operation. Wherein the immediate operand is a constant in the instruction, without reading from the virtual register. In a new instruction, there may be no interfaces, one interface, or more than two interfaces, where the number of interfaces is the same as the number of data that needs to be read by the current instruction, and each interface is 4 bytes in length. For example, the current instruction includes a read data operation 1 and a read data operation 2, where the read data operation 1 needs to read one data 1 from the virtual register 1, and the read data operation 2 needs to read one data 2 (i.e., immediate operand) from the first byte code, and then two operands are included in the new instruction, respectively, the index for identifying the virtual register 1 and the data 2.
After each instruction in the first byte code is executed in the steps A2 and A3 to obtain a corresponding new instruction, the new instructions corresponding to each instruction in the first byte code can be serialized to obtain the second byte code. Serialization refers to the process of converting structured data into a specified format according to a certain coding specification.
Optionally, the step A2 specifically includes:
judging whether a data writing operation exists in the data reading and writing operations included in the current instruction or not and whether a data reading operation exists or not according to the meaning of the current instruction;
if the data writing operation exists in the data reading and writing operations included in the current instruction, carrying out self-increment on a preset count value, and taking the self-increment count value as an index corresponding to the data writing operation;
if the read-write data operation included in the current instruction includes the read-write data operation, the index corresponding to the target write data operation is used as the index corresponding to the read data operation.
In the embodiment of the application, whether the data writing operation exists in the data reading and writing operation included in the current instruction or not can be judged according to the meaning of the current instruction, and whether the data reading operation exists in the data reading and writing operation included in the current instruction or not is judged. If the data writing operation exists in the data writing operation included in the current instruction, the preset count value can be self-increased, and then the self-increased count value is used as an index corresponding to the data writing operation.
For example, the count value may be preset to 0, and the size of each self-increment of the count value is 1. If the current instruction is the first instruction in the first byte code according to the instruction execution sequence and there is a data writing operation in the data reading and writing operation included in the current instruction, the index corresponding to the data writing operation may be set to 1. If the current instruction is a second instruction in the first byte code according to the instruction execution sequence and a data writing operation exists in the data reading and writing operations included in the current instruction, an index corresponding to the data writing operation can be set to 2, and the like, and according to the execution sequence of the data writing operation, the index corresponding to each data writing operation is equal to the index corresponding to the previous data writing operation plus 1.
Based on the fact that there may be no write data operation in the read-write data operation included in the current instruction, the value id in the new instruction may be set to a preset invalid index, for example, the invalid index may be 0. Wherein the invalid index is not an identification of any one virtual register.
If the read-write data operation included in the current instruction includes the read-write data operation, and the data to be read by the read-write data operation is not an immediate operand, the index corresponding to the target write data operation may be used as the index corresponding to the read-write data operation. The target write data operation and the read data operation are used for operating the same data. For example, if the current instruction is the second instruction in the first byte code according to the instruction execution sequence, and there is a read data operation in the read-write data operation included in the current instruction, the data to be read in the read data operation is data a. And data a is written into the virtual register by a write data operation included in a first instruction in the first byte code in the order of execution of the instructions. Therefore, the write data operation included in the first instruction is a target write data operation, and the target write data operation and the read data operation included in the current instruction are both used for operating the data a.
If there is a read data operation in the read data operation included in the current instruction, and the data to be read by the read data operation is an immediate operand, the interfaces in the new instruction may be set to the immediate operand.
In the embodiment of the present application, since the index is used to identify the virtual registers, the total number of virtual registers that need to be used in the execution of the second bytecode may be determined based on each index included in the second bytecode. For example, an index stack may be preset, after the step A2, an index corresponding to a write data operation included in the current instruction may be pushed into the index stack, an index corresponding to a read data operation included in the current instruction may be popped from the index stack, then, each index and the number of indexes in the index stack at this time are counted, and each index and the number of indexes in the index stack are saved as an index record, where the number of indexes in the index stack is the number of virtual registers in use when the current instruction is executed. Based on the above, after each instruction in the first byte code is traversed, an index record corresponding to each instruction is stored in the terminal device, where the index record includes each index and the number of indexes in the index stack when the corresponding instruction is executed. It should be appreciated that when an index is popped from the index stack, the virtual register identified on behalf of the index becomes idle; when an index is pushed onto the index stack, the virtual register identified by that index is changed to a use state. Therefore, in view of virtual register multiplexing, the index corresponding to the read-write data operation included in the instruction in the first byte code can be updated based on the preset update rule and the index record. The preset updating rule may be: and judging whether a popped index exists before pushing an index corresponding to the data writing operation into an index stack according to the data writing operation included by the instruction in the first byte code, if so, taking any popped index as a new index corresponding to the data writing operation, and updating the value ID in the new instruction corresponding to the instruction into the new index. Accordingly, if the index corresponding to the write data operation is updated to the new index, the index corresponding to the read data operation with the write data operation as the target write data operation should also be updated to the new index, and the interfaces in the new instruction corresponding to the read data operation should be updated to the new index. And finally, determining the total number of virtual registers needed to be used in the execution process of the second byte code according to each updated index.
For example, assume that instruction 1, instruction 2, instruction 3, instruction 4, and instruction 5 are included in the first bytecode.
The instruction 1 includes a data writing operation 1, and the step A2 is executed to obtain an index 1 corresponding to the data writing operation 1, that is, the data should be written into the virtual register identified by the index 1 by the data writing operation 1, and then the index 1 is pushed into the index stack, where the index stack includes indexes 1 and the number of indexes is 1.
The instruction 2 includes a data writing operation 2, and the step A2 is executed to obtain an index 2 corresponding to the data writing operation 2, and then the index 2 is pushed into an index stack, where indexes included in the index stack are 1 and 2, and the number of indexes is 2.
The instruction 3 includes a data writing operation 3, and the step A2 is executed to obtain an index 3 corresponding to the data writing operation 3, and then the index 3 is pushed into an index stack, where indexes included in the index stack are 1, 2 and 3, and the number of indexes is 3.
The instruction 4 includes a data reading operation 1, a data reading operation 2 and a data writing operation 4, the step A2 is executed to obtain an index 1 corresponding to the data reading operation 1, an index 2 corresponding to the data reading operation 2 and an index 4 corresponding to the data writing operation 4, then the index 1 and the index 2 in the index stack are popped, the index 4 is pushed into the index stack, at this time, the indexes included in the index stack are 3 and 4, and the number of the indexes is 2.
The instruction 5 includes a data reading operation 4, and the step A2 is executed to obtain an index corresponding to the data reading operation 4 as 4, and then the index 4 is popped from the index stack, where the index stack includes indexes as 3 and the number of indexes as 1.
Because there is no index that has been popped before pushing the index 1 into the index stack, that is, there is no free virtual register, the index corresponding to the write data operation 1 does not need to be updated; similarly, the indices corresponding to write data operation 2 and write data operation 3 need not be updated. Before pushing the index 4 to the index stack, the index 1 and the index 2 are popped, that is, after the read data operation 1 and the read data operation 2 are executed, the data in the virtual register identified by the index 1 and the virtual register identified by the index 2 are read out, and at this time, the virtual register identified by the index 1 and the virtual register identified by the index 2 are in an idle state, so that the index corresponding to the write data operation 4 can be updated to 1 or 2, that is, the write data operation 4 can write the data into the virtual register identified by the index 1 or the virtual register identified by the index 2, and meanwhile, the value id in the new instruction corresponding to the instruction 4 is updated to the index 1 or the index 2. Since the read data operation 4 and the write data operation 4 operate the same data, that is, the read data operation 4 uses the write data operation 4 as the target write data operation, after the index corresponding to the write data operation 4 is updated to 1 or 2, the index corresponding to the read data operation 4 using the write data operation 4 as the target write data operation should also be updated to 1 or 2, and the interfaces corresponding to the new instruction of the instruction 5 should be updated to 1 or 2. Finally, according to each updated index, the total number of virtual registers needed to be used in the execution process of the second byte code can be determined to be 3, and the virtual registers are respectively identified by the index 1, the index 2 and the index 3.
After the total number of virtual registers needed to be used in the execution process of the second byte code is obtained, the memory size of the target memory can be determined according to the total number. For example, the product of the total number and the preset memory size of the virtual registers may be taken as the target memory size. For example, the size of the target memory is 4×3=12 if the predetermined memory size is 4, that is, the memory size of each virtual register is 4, and the total number of virtual registers needed to be used in the execution process of the second bytecode is 3. The target memory may be any section of continuous and idle memory in the memory of the terminal device, where the target memory is used to store operation data generated in the execution process of the second byte code. Based on the above example, the size of the target memory is 12, and the target memory includes 3 virtual registers, that is, the target memory is divided into 3 memory areas, each representing one virtual register.
In this embodiment of the present application, the second bytecode is executed, that is, each new instruction in the second bytecode is executed, and the composition structure of the new instruction in the second bytecode is value id+opcode+operations. Upon execution of each new instruction in the second bytecode, an operation indicated by an operation code of the new instruction may be performed according to a virtual register identified by an index included in the new instruction. Specifically, a data writing operation included in the new instruction can be executed, and data to be written is written into a virtual register identified by the value ID; the new instruction is executed to include a read data operation to read the required data from the virtual register identified by the operants. For example, a new instruction with a value ID of 3 and an interfaces of 2 indicates that a write operation needs to write data A and a read operation needs to read data B, then, when the new instruction is executed, data A is written into the virtual register identified by index 3 and data B is read from the virtual register identified by index 2. It should be noted that, the interfaces in the new instruction may be an immediate operand, and the virtual machine may determine, according to the operation code in the new instruction, whether the read data operation included in the new instruction needs to read data from the memory, if so, it indicates that the interfaces are not immediate operands, and if not, it indicates that the interfaces are immediate operands. In the case where the operands are immediate operands, the virtual machine may use the operands directly to perform the logical operations indicated by the opcode. By the method, when a new instruction in the second byte code is executed, the virtual register which is needed to be used currently can be quickly determined according to the value ID and the operants in the new instruction, so that the execution speed of the instruction is increased.
In the above-mentioned scheme, first byte codes to be executed are obtained first, the first byte codes are converted into second byte codes with a self-defined format, the second byte codes comprise indexes corresponding to each read-write data operation in the execution process of the first byte codes, then a section of target memory is determined based on the indexes, the target memory comprises at least one virtual register, each virtual register is identified by different indexes, and finally the second byte codes are executed based on the virtual registers identified by each index in the second byte codes. According to the method and the device, the first byte code to be executed is converted into the second byte code in the self-defined format, and the index corresponding to each read-write data operation in the execution process of the first byte code is added into the second byte code, so that the virtual register which is required to be used currently can be rapidly determined according to each index when the second byte code is interpreted and executed by the virtual machine, and the performance of the virtual machine for interpreting and executing the byte code can be improved.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic of each process, and should not limit the implementation process of the embodiment of the present application in any way.
Fig. 2 shows a block diagram of a bytecode execution device according to an embodiment of the present application, and for convenience of explanation, only a portion related to the embodiment of the present application is shown.
The bytecode execution device 200 includes:
an acquiring unit 201, configured to acquire a first bytecode to be executed;
a conversion unit 202, configured to convert the first byte code into a second byte code in a custom format, where the second byte code includes an index corresponding to each read-write data operation in the execution process of the first byte code;
a determining unit 203, configured to determine a section of target memory based on the index, where the target memory includes at least one virtual register, and each virtual register is identified by a different index;
the execution unit 204 is configured to execute the second bytecode based on the virtual register identified by each index in the second bytecode.
Optionally, the conversion unit 202 includes:
a traversing subunit, configured to traverse each instruction in the first byte code according to an instruction execution sequence;
the index determination subunit is used for determining an index corresponding to the read-write data operation included in the current instruction according to the meaning of the current instruction aiming at the current instruction, wherein the current instruction is a currently traversed instruction;
A generating subunit, configured to generate a new instruction according to an index corresponding to the read-write data operation included in the current instruction and an operation code of the current instruction;
and the serializing subunit is used for serializing new instructions corresponding to the instructions in the first byte code to obtain the second byte code.
Optionally, the executing unit 204 includes:
an instruction execution subunit, configured to execute a new instruction in the second bytecode;
and the operation execution subunit is used for executing the operation indicated by the operation code of the new instruction according to the virtual register identified by the index included in the new instruction.
Optionally, the index determination subunit includes:
the judging subunit is used for judging whether a data writing operation exists in the data reading and writing operations included in the current instruction or not and whether a data reading operation exists or not according to the meaning of the current instruction;
the first judging subunit is used for carrying out self-increment on a preset count value if a data writing operation exists in the data writing operation included in the current instruction, and taking the self-increment count value as an index corresponding to the data writing operation;
and the second judging subunit is used for taking an index corresponding to a target write data operation as the index corresponding to the read data operation if the read data operation exists in the read data operation included in the current instruction, wherein the target write data operation and the read data operation are operated for the same data.
Optionally, the generating subunit is specifically configured to splice an index corresponding to the read-write data operation included in the current instruction with an operation code of the current instruction, so as to obtain the new instruction.
Optionally, the determining unit 203 includes:
a total number determining subunit, configured to determine, based on the index, a total number of virtual registers that need to be used in the execution process of the second bytecode;
a memory size determining subunit, configured to determine a memory size of the target memory according to the total number;
and the memory determining subunit is used for determining an idle memory as the target memory according to the memory size.
Optionally, the memory size determining subunit is specifically configured to take a product of the total number and a preset memory size of the virtual register as the size of the target memory.
In the above-mentioned scheme, first byte codes to be executed are obtained first, the first byte codes are converted into second byte codes with a self-defined format, the second byte codes comprise indexes corresponding to each read-write data operation in the execution process of the first byte codes, then a section of target memory is determined based on the indexes, the target memory comprises at least one virtual register, each virtual register is identified by different indexes, and finally the second byte codes are executed based on the virtual registers identified by each index in the second byte codes. According to the method and the device, the first byte code to be executed is converted into the second byte code in the self-defined format, and the index corresponding to each read-write data operation in the execution process of the first byte code is added into the second byte code, so that the virtual register which is required to be used currently can be rapidly determined according to each index when the second byte code is interpreted and executed by the virtual machine, and the performance of the virtual machine for interpreting and executing the byte code can be improved.
Fig. 3 is a schematic structural diagram of a terminal device according to an embodiment of the present application. As shown in fig. 3, the terminal device 3 of this embodiment includes: at least one processor 30 (only one is shown in fig. 3), a memory 31 and a computer program 32 stored in the memory 31 and executable on the at least one processor 30, the processor 30 implementing the following steps when executing the computer program 32:
acquiring a first byte code to be executed;
converting the first byte code into a second byte code with a custom format, wherein the second byte code comprises an index corresponding to each read-write data operation in the execution process of the first byte code;
determining a section of target memory based on the index, wherein the target memory comprises at least one virtual register, and each virtual register is identified by a different index;
and executing the second byte code based on the virtual register identified by each index in the second byte code.
Assuming that the first possible implementation manner is the first possible implementation manner, in a second possible implementation manner provided by the first possible implementation manner as a basis, the converting the first bytecode into the second bytecode in the custom format includes:
Traversing each instruction in the first byte code according to the instruction execution sequence;
for a current instruction, determining an index corresponding to read-write data operation included in the current instruction according to the meaning of the current instruction, wherein the current instruction is a currently traversed instruction;
generating a new instruction according to an index corresponding to the read-write data operation included in the current instruction and an operation code of the current instruction;
and serializing new instructions corresponding to the instructions in the first byte code to obtain the second byte code.
In a third possible implementation manner provided by the second possible implementation manner, the executing the second bytecode based on the virtual register identified by each index in the second bytecode includes:
executing a new instruction in the second byte code;
and executing the operation indicated by the operation code of the new instruction according to the virtual register identified by the index included in the new instruction.
In a fourth possible implementation manner provided by the second possible implementation manner, the determining, according to the meaning of the current instruction, an index corresponding to a read-write data operation included in the current instruction includes:
Judging whether a data writing operation exists in the data reading and writing operations included in the current instruction or not and whether a data reading operation exists or not according to the meaning of the current instruction;
if the data writing operation exists in the data writing operation included in the current instruction, carrying out self-increment on a preset count value, and taking the self-increment count value as an index corresponding to the data writing operation;
and if the read-write data operation included in the current instruction includes the read-write data operation, taking an index corresponding to a target write data operation as the index corresponding to the read data operation, wherein the target write data operation and the read data operation operate on the same data.
In a fifth possible implementation manner provided by the second possible implementation manner, the generating the new instruction according to the index corresponding to the read-write data operation included in the current instruction and the operation code of the current instruction includes:
and splicing the index corresponding to the read-write data operation included in the current instruction with the operation code of the current instruction to obtain the new instruction.
In a sixth possible implementation manner provided by the first possible implementation manner, the determining a segment of the target memory based on the index includes:
Determining the total number of virtual registers needed to be used in the execution process of the second byte code based on the index;
determining the memory size of the target memory according to the total number;
and determining an idle memory as the target memory according to the memory size.
In a seventh possible implementation manner provided by the sixth possible implementation manner, the determining the memory size of the target memory according to the total number includes:
taking the product of the total number and the preset memory size of the virtual register as the size of the target memory.
The terminal device 3 may be a computing device such as a desktop computer, a notebook computer, a palm computer, a cloud server, or the like. The terminal device may include, but is not limited to, a processor 30, a memory 31. It will be appreciated by those skilled in the art that fig. 3 is merely an example of the terminal device 3 and does not constitute a limitation of the terminal device 3, and may include more or less components than illustrated, or may combine certain components, or different components, such as may also include input-output devices, network access devices, etc.
The processor 30 may be a central processing unit (Central Processing Unit, CPU), the processor 30 may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 31 may in some embodiments be an internal storage unit of the terminal device 3, such as a hard disk or a memory of the terminal device 3. The memory 31 may also be an external storage device of the terminal device 3 in other embodiments, for example, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card) or the like, which are provided on the terminal device 3. Further, the memory 31 may include both the internal storage unit and the external storage device of the terminal device 3. The memory 31 is used for storing an operating system, an application program, a boot loader (BootLoader), data, other programs, and the like, such as program codes of the computer programs. The above-described memory 31 may also be used to temporarily store data that has been output or is to be output.
In the above-mentioned scheme, first byte codes to be executed are obtained first, the first byte codes are converted into second byte codes with a self-defined format, the second byte codes comprise indexes corresponding to each read-write data operation in the execution process of the first byte codes, then a section of target memory is determined based on the indexes, the target memory comprises at least one virtual register, each virtual register is identified by different indexes, and finally the second byte codes are executed based on the virtual registers identified by each index in the second byte codes. According to the method and the device, the first byte code to be executed is converted into the second byte code in the self-defined format, and the index corresponding to each read-write data operation in the execution process of the first byte code is added into the second byte code, so that the virtual register which is required to be used currently can be rapidly determined according to each index when the second byte code is interpreted and executed by the virtual machine, and the performance of the virtual machine for interpreting and executing the byte code can be improved.
It should be noted that, because the content of information interaction and execution process between the above devices/units is based on the same concept as the method embodiment of the present application, specific functions and technical effects thereof may be referred to in the method embodiment section, and will not be described herein again.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
The embodiments of the present application also provide a computer readable storage medium storing a computer program, which when executed by a processor, implements the steps of the respective method embodiments described above.
The present embodiments provide a computer program product for causing a terminal device to perform the steps of the respective method embodiments described above when the computer program product is run on the terminal device.
The integrated units described above, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the present application implements all or part of the flow of the method of the above embodiments, and may be implemented by a computer program to instruct related hardware, where the above computer program may be stored in a computer readable storage medium, where the computer program, when executed by a processor, may implement the steps of each of the method embodiments described above. The computer program comprises computer program code, and the computer program code can be in a source code form, an object code form, an executable file or some intermediate form and the like. The computer readable medium may include at least: any entity or device capable of carrying computer program code to a terminal device, a recording medium, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Such as a U-disk, removable hard disk, magnetic or optical disk, etc. In some jurisdictions, computer readable media may not be electrical carrier signals and telecommunications signals in accordance with legislation and patent practice.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus/network device and method may be implemented in other manners. For example, the apparatus/network device embodiments described above are merely illustrative, e.g., the division of modules or elements described above is merely a logical functional division, and there may be additional divisions in actual implementation, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.
The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (9)
1. A method for executing byte code, comprising:
acquiring a first byte code to be executed; the first byte code is a byte code to be executed, wherein the byte code is compiled by a compiler from a program source code to be executed;
Converting the first byte code into a second byte code in a custom format, wherein the second byte code comprises an index corresponding to each read-write data operation in the execution process of the first byte code, and the second byte code and the first byte code comprise the same operation code;
determining a section of target memory based on the index, wherein the target memory comprises at least one virtual register, and each virtual register is identified by a different index;
executing the second bytecode based on virtual registers identified by respective indexes in the second bytecode;
the determining a section of target memory based on the index includes:
determining the total number of virtual registers needed to be used in the execution process of the second byte code based on the index;
determining the memory size of the target memory according to the total number;
and determining an idle memory as the target memory according to the memory size, wherein the target memory is used for storing operation data generated in the execution process of the second byte code.
2. The method of claim 1, wherein the converting the first bytecode into a second bytecode in a custom format comprises:
Traversing each instruction in the first byte code according to the instruction execution sequence;
for a current instruction, determining an index corresponding to read-write data operation included in the current instruction according to the meaning of the current instruction, wherein the current instruction is a currently traversed instruction;
generating a new instruction according to an index corresponding to the read-write data operation included in the current instruction and an operation code of the current instruction;
and serializing new instructions corresponding to the instructions in the first byte code to obtain the second byte code.
3. The method of claim 2, wherein the executing the second bytecode based on the virtual registers identified by the respective indexes in the second bytecode comprises:
executing a new instruction in the second byte code;
and executing the operation indicated by the operation code of the new instruction according to the virtual register identified by the index included by the new instruction.
4. The method according to claim 2, wherein the determining, according to the meaning of the current instruction, an index corresponding to a read-write data operation included in the current instruction includes:
Judging whether a data writing operation exists in the data reading and writing operations included in the current instruction or not and whether a data reading operation exists or not according to the meaning of the current instruction;
if the data writing operation exists in the data reading and writing operations included in the current instruction, carrying out self-increment on a preset count value, and taking the self-increment count value as an index corresponding to the data writing operation;
and if the read-write data operation included in the current instruction includes the read-write data operation, taking an index corresponding to a target write data operation as the index corresponding to the read data operation, wherein the target write data operation and the read data operation are operated for the same data.
5. The method according to claim 2, wherein the generating a new instruction according to the index corresponding to the read-write data operation included in the current instruction and the operation code of the current instruction includes:
and splicing the index corresponding to the read-write data operation included in the current instruction with the operation code of the current instruction to obtain the new instruction.
6. The method of claim 1, wherein determining the memory size of the target memory based on the total number comprises:
Taking the product of the total number and the preset memory size of the virtual register as the size of the target memory.
7. A bytecode execution apparatus, comprising:
an acquisition unit configured to acquire a first bytecode to be executed; the first byte code is a byte code to be executed, wherein the byte code is compiled by a compiler from a program source code to be executed;
the conversion unit is used for converting the first byte code into a second byte code with a custom format, wherein the second byte code comprises an index corresponding to each read-write data operation in the execution process of the first byte code, and the second byte code and the first byte code comprise the same operation code;
a determining unit, configured to determine a section of target memory based on the index, where the target memory includes at least one virtual register, and each virtual register is identified by a different index;
an execution unit configured to execute the second bytecode based on virtual registers identified by respective indexes in the second bytecode;
the determination unit includes:
a total number determination subunit, configured to determine, based on the index, a total number of virtual registers that need to be used in the execution process of the second bytecode;
A memory size determining subunit, configured to determine a memory size of the target memory according to the total number;
and the memory determining subunit is used for determining an idle memory as the target memory according to the memory size, and the target memory is used for storing operation data generated in the execution process of the second byte code.
8. A terminal device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the method according to any of claims 1 to 6 when executing the computer program.
9. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the method according to any one of claims 1 to 6.
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| PCT/CN2020/139391 WO2022126710A1 (en) | 2020-12-14 | 2020-12-25 | Bytecode executing method, bytecode executing apparatus, and terminal device |
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| CN113760193B (en) * | 2021-08-26 | 2024-04-02 | 武汉天喻信息产业股份有限公司 | Data read-write method and device for resource-restricted device and instruction set |
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| US20070288909A1 (en) * | 2006-06-07 | 2007-12-13 | Hong Kong Applied Science and Technology Research Institute Company Limited | Hardware JavaTM Bytecode Translator |
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| CN104346132B (en) * | 2013-08-08 | 2017-06-09 | 上海复旦微电子集团股份有限公司 | It is applied to the control device and smart card virtual machine of smart card virtual machine operation |
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