CN112506569A - Bytecode execution method, bytecode execution device and terminal equipment - Google Patents
Bytecode execution method, bytecode execution device and terminal equipment Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/30134—Register stacks; shift registers
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
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Abstract
The application is applicable to the technical field of computers, and provides a bytecode execution method, a bytecode execution device and terminal equipment, wherein the method comprises the following steps: acquiring a first bytecode to be executed; converting the first byte code into a second byte code with a custom format, wherein the second byte code comprises an index corresponding to each read-write data operation in the execution process of the first byte code; determining a section of target memory based on the index, wherein the target memory comprises at least one virtual register, and each virtual register is identified by a different index; executing the second bytecode based on virtual registers identified by respective indices in the second bytecode. By the method, the performance of the virtual machine for interpreting and executing the byte codes can be improved.
Description
Technical Field
The present application belongs to the field of computer technologies, and in particular, to a bytecode execution method, a bytecode execution device, a terminal device, and a computer-readable storage medium.
Background
A Byte-code (Byte-code) is a binary file containing an execution program, consisting of a sequence of op code/data pairs, is an intermediate code. The bytecode can be interpreted and executed by a virtual machine. Currently, in the process of interpreting and executing bytecodes, the used memory of a virtual machine is designed based on a stack structure. However, the performance of reading and writing data using the stacked memory is very low.
Disclosure of Invention
In view of this, the present application provides a bytecode execution method, a bytecode execution device, a terminal device, and a computer-readable storage medium, which can improve the performance of a virtual machine in interpreting and executing the bytecode.
In a first aspect, the present application provides a bytecode execution method, including:
acquiring a first bytecode to be executed;
converting the first byte code into a second byte code with a custom format, wherein the second byte code comprises an index corresponding to each read-write data operation in the execution process of the first byte code;
determining a section of target memory based on the index, wherein the target memory comprises at least one virtual register, and each virtual register is identified by different indexes;
and executing the second bytecode based on the virtual register identified by each index in the second bytecode.
In a second aspect, the present application provides a bytecode execution device, including:
the device comprises an acquisition unit, a processing unit and a control unit, wherein the acquisition unit is used for acquiring a first bytecode to be executed;
a conversion unit, configured to convert the first bytecode into a second bytecode in a custom format, where the second bytecode includes an index corresponding to each read-write data operation during execution of the first bytecode;
a determining unit, configured to determine a segment of target memory based on the index, where the target memory includes at least one virtual register, and each virtual register is identified by a different index;
and an execution unit, configured to execute the second bytecode based on the virtual register identified by each index in the second bytecode.
In a third aspect, the present application provides a terminal device, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the method provided in the first aspect when executing the computer program.
In a fourth aspect, the present application provides a computer readable storage medium storing a computer program which, when executed by a processor, implements the method as provided in the first aspect.
In a fifth aspect, the present application provides a computer program product, which, when run on a terminal device, causes the terminal device to perform the method provided by the first aspect.
As can be seen from the above, in the present application, a first bytecode to be executed is first obtained, the first bytecode is converted into a second bytecode in a custom format, the second bytecode includes an index corresponding to each read-write data operation during the execution of the first bytecode, then a section of target memory is determined based on the index, the target memory includes at least one virtual register, each virtual register is identified by a different index, and finally the second bytecode is executed based on the virtual register identified by each index in the second bytecode. According to the scheme, the first byte code to be executed is converted into the second byte code in the custom format, and the index corresponding to each read-write data operation in the execution process of the first byte code is added into the second byte code, so that the virtual register required to be used at present can be quickly determined according to each index when the virtual machine explains and executes the second byte code, and the performance of explaining and executing the byte code by the virtual machine can be improved. It is understood that the beneficial effects of the second aspect to the fifth aspect can be referred to the related description of the first aspect, and are not described herein again.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic flowchart of a bytecode execution method according to an embodiment of the present application;
fig. 2 is a block diagram of a bytecode execution device according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a terminal device according to an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to" determining "or" in response to detecting ". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.
Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.
Fig. 1 shows a flowchart of a bytecode execution method provided in an embodiment of the present application, where the bytecode execution method is applied to a terminal device, and is detailed as follows:
In this embodiment, if a section of program source code needs to be executed, a user may compile the section of program source code into a bytecode to be executed through a compiler, where the bytecode may be referred to as a first bytecode. For example, for a piece of Java program source code that needs to be executed, a user may compile the piece of Java program source code into webassembly (wasm) bytecode, i.e., a first bytecode.
In this embodiment of the present application, the first bytecode includes a plurality of instructions having a sequential execution order, and the execution of the first bytecode, that is, the execution of the plurality of instructions in the first bytecode. When executing one instruction, the virtual machine may need to perform one or more than two read-write data operations, where the read-write data operations include a read-data operation and a write-data operation. In order to improve the execution efficiency of the bytecode, the embodiment of the application modifies the first bytecode and converts the first bytecode into a second bytecode in a custom format. The second bytecode includes an index corresponding to each read-write data operation during execution of the first bytecode, where the index is used to identify a virtual register, that is, a memory area in a memory of the terminal device. According to the corresponding index, the virtual register which is needed to be used currently in the data reading and writing operation can be determined.
It should be noted that, since the user actually needs to execute the first bytecode to implement the function of the first bytecode, it should be ensured that executing the second bytecode can implement the function of the first bytecode. The implementation of the function of the bytecode is determined by the operation code in the instruction, so that the second bytecode and the first bytecode can contain the same operation code, and thus, the execution of the second bytecode can be guaranteed to implement the function of the first bytecode. Further, since the second bytecode and the first bytecode include the same operation code, the data reading and writing operation during the execution of the second bytecode is also the same as the data reading and writing operation during the execution of the first bytecode. When any read-write data operation in the second bytecode execution process is performed, the virtual machine can quickly determine the virtual register which is needed to be used by the read-write data operation at present according to the index corresponding to the read-write data operation.
Optionally, the step 102 specifically includes:
a1, traversing each instruction in the first byte code according to the instruction execution sequence;
a2, aiming at the current instruction, determining an index corresponding to the read-write data operation included in the current instruction according to the meaning of the current instruction;
a3, generating a new instruction according to the index corresponding to the read-write data operation included in the current instruction and the operation code of the current instruction;
and A4, serializing new instructions corresponding to the instructions in the first bytecode to obtain a second bytecode.
In the embodiment of the present application, each instruction in the first bytecode may be traversed in the instruction execution order of the first bytecode. For example, assuming that the first bytecode is a WASM bytecode, since the length of the operation code in the WASM bytecode is one byte, the data in the first bytecode can be read sequentially, and the data with one byte length is read each time, and the data is converted into one instruction. Regarding the current traversed instruction, the instruction is recorded as the current instruction, and the index corresponding to each read-write data operation included in the current instruction can be determined according to the meaning of the current instruction. The meaning of the current instruction can be obtained according to the operation code of the current instruction, and the operation code of the current instruction is used for representing the operation characteristics and functions of the current instruction, namely the meaning of the current instruction. After determining the index corresponding to each data read-write operation included in the current instruction, a new instruction may be generated according to the index and the operation code of the current instruction, where the generated new instruction includes the operation code of the current instruction and the index corresponding to each data read-write operation included in the current instruction.
For example, the operation code of the current instruction and the index corresponding to each data read-write operation included in the current instruction may be spliced to obtain a new instruction. The new instruction has a composition structure of value ID (4 bytes) + opcode (1 byte) + operands, wherein the value ID is an index corresponding to a write data operation included in the current instruction and has a length of 4 bytes; the opcode is an operation code of the current instruction, and the length of the opcode is 1 byte; operands is an index corresponding to the read data operation included in the current instruction. It should be noted that if the data that needs to be read by the read data operation is an immediate operand, the operands may be the immediate operand that needs to be read by the read data operation, rather than the index corresponding to the read data operation. The immediate operand is a constant in the instruction and does not need to be read from the virtual register. In a new instruction, the operands may not be included, one operand may be included, or two or more operands may be included, the number of operands is the same as the number of data to be read by the current instruction, and each operand has a length of 4 bytes. For example, the current instruction includes a read data operation 1 and a read data operation 2, where the read data operation 1 needs to read one data 1 from the virtual register 1, and the read data operation 2 needs to read one data 2 (i.e., an immediate operand) from the first bytecode, then two operands, namely, an index for identifying the virtual register 1 and data 2, are included in the new instruction.
After steps a2 and A3 are performed on each instruction in the first bytecode to obtain a corresponding new instruction, the new instruction corresponding to each instruction in the first bytecode may be serialized to obtain a second bytecode. The serialization refers to a process of converting structured data into a specified format according to a certain coding specification.
Optionally, the step a2 specifically includes:
judging whether a data writing operation and a data reading operation exist in the read-write data operation included in the current instruction according to the meaning of the current instruction;
if the read-write data operation included in the current instruction has a data writing operation, performing self-increment on a preset count value, and taking the self-incremented count value as an index corresponding to the data writing operation;
and if the read-write data operation included in the current instruction has a read-data operation, taking the index corresponding to the target write-data operation as the index corresponding to the read-data operation.
In the embodiment of the application, whether a data writing operation exists in the read-write data operation included in the current instruction or not can be judged according to the meaning of the current instruction, and whether a data reading operation exists in the read-write data operation included in the current instruction or not can be judged. If there is a write data operation in the read-write data operation included in the current instruction, the preset count value may be incremented, and then the incremented count value is used as an index corresponding to the write data operation.
For example, a count value of 0 may be preset, and the size of each self-increment of the count value is 1. If the current instruction is the first instruction in the first bytecode according to the instruction execution order, and there is a write data operation in the read-write data operations included in the current instruction, the index corresponding to the write data operation may be set to 1. If the current instruction is the second instruction in the first bytecode according to the instruction execution order, and there is a write data operation in the read-write data operation included in the current instruction, the index corresponding to the write data operation may be set to 2, and so on, and according to the execution order of the write data operation, the index corresponding to each write data operation is equal to the index corresponding to the previous write data operation plus 1.
Considering that there may not be a write data operation in the read and write data operations included in the current instruction, based on this, the value id in the new instruction may be set to a preset invalid index, for example, the invalid index may be 0. Where the invalid index is not an identification of any one virtual register.
If there is a read data operation in the read-write data operations included in the current instruction, and the data that needs to be read by the read data operation is not an immediate operand, the index corresponding to the target write data operation may be used as the index corresponding to the read data operation. Wherein the target write data operation and the read data operation are for operating on the same data. For example, if the current instruction is the second instruction in the first bytecode according to the instruction execution order, and there is a read data operation in the read and write data operations included in the current instruction, the data that needs to be read by the read data operation is data a. And data a is written to the virtual register by a write data operation included by the first instruction in the first bytecode in instruction execution order. Therefore, the write data operation included in the first instruction is a target write data operation, and both the target write data operation and the read data operation included in the current instruction are used for operating data a.
If there is a read data operation in the read-write data operations included in the current instruction, and the data that needs to be read by the read data operation is an immediate operand, operands in the new instruction may be set as the immediate operand.
In the embodiment of the present application, since the index is used to identify the virtual register, the total number of virtual registers that need to be used in the execution process of the second bytecode may be determined based on each index included in the second bytecode. For example, an index stack may be preset, and after step a2, an index corresponding to a write data operation included in the current instruction may be pushed into the index stack, and an index corresponding to a read data operation included in the current instruction may be popped from the index stack, then the number of each index and the number of indexes in the index stack at this time are counted, and each index and the number of indexes in the index stack are stored as an index record, where the number of indexes in the index stack is the number of virtual registers in use when the current instruction is executed. Based on this, after traversing each instruction in the first bytecode, the terminal device stores an index record corresponding to each instruction, where the index record includes each index and the number of indexes in the index stack when the corresponding instruction is executed. It should be understood that when an index is popped from the index stack, the virtual register identified by the index is changed to an idle state; when an index is pushed onto the index stack, the virtual register identified by the index is changed into a use state. Therefore, in consideration of virtual register multiplexing, the index corresponding to the read-write data operation included in the instruction in the first bytecode may be updated based on the preset update rule and the index record. The preset update rule may be: for a write data operation included in an instruction in a first bytecode, judging whether an index which is popped before the index corresponding to the write data operation is pushed into an index stack exists, if so, taking any popped index as a new index corresponding to the write data operation, and updating a value ID in a new instruction corresponding to the instruction as the new index. Correspondingly, if the index corresponding to the write data operation is updated to the new index, the index corresponding to the read data operation that targets the write data operation should also be updated to the new index, and the operands in the new instruction corresponding to the read data operation should be updated to the new index. And finally, according to each updated index, the total number of the virtual registers required to be used in the execution process of the second byte code can be determined.
For example, assume that instruction 1, instruction 2, instruction 3, instruction 4, and instruction 5 are included in the first bytecode.
The instruction 1 includes a write data operation 1, and the step a2 is executed to obtain that the index corresponding to the write data operation 1 is 1, that is, the write data operation 1 should write data into the virtual register identified by the index 1, and then the index 1 will be pushed into the index stack, where the index included in the index stack is 1, and the number of indexes is 1.
The instruction 2 includes a data writing operation 2, the step a2 is executed to obtain that the index corresponding to the data writing operation 2 is 2, and then the index 2 is pushed into the index stack, where the indexes included in the index stack are 1 and 2, and the number of the indexes is 2.
The instruction 3 includes a data writing operation 3, the step a2 is executed to obtain that the index corresponding to the data writing operation 3 is 3, and then the index 3 is pushed into the index stack, where the indexes included in the index stack are 1, 2, and 3, and the number of indexes is 3.
The instruction 4 includes a read data operation 1, a read data operation 2, and a write data operation 4, the step a2 is executed to obtain that the index corresponding to the read data operation 1 is 1, the index corresponding to the read data operation 2 is 2, and the index corresponding to the write data operation 4 is 4, then the index 1 and the index 2 in the index stack are popped up, the index 4 is pushed into the index stack, at this time, the indexes included in the index stack are 3 and 4, and the number of the indexes is 2.
The instruction 5 includes a read data operation 4, the step a2 is executed to obtain that the index corresponding to the read data operation 4 is 4, and then the index 4 is popped from the index stack, where the index included in the index stack is 3 and the number of indexes is 1.
Since no indexes already popped before the index 1 is pushed into the index stack, that is, no idle virtual register exists, the index corresponding to the data writing operation 1 does not need to be updated; similarly, the indexes corresponding to write data operation 2 and write data operation 3 do not need to be updated. Before the index 4 is pushed into the index stack, the indexes 1 and 2 are popped, that is, after the data reading operation 1 and the data reading operation 2 are performed, the data in the virtual register identified by the index 1 and the data in the virtual register identified by the index 2 are both read, and at this time, the virtual register identified by the index 1 and the virtual register identified by the index 2 are in an idle state, so that the index corresponding to the data writing operation 4 can be updated to 1 or 2, that is, the data writing operation 4 can write the data into the virtual register identified by the index 1 or the virtual register identified by the index 2, and meanwhile, the value id in the new instruction corresponding to the instruction 4 is updated to the index 1 or the index 2. Since the data reading operation 4 and the data writing operation 4 operate the same data, that is, the data reading operation 4 uses the data writing operation 4 as a target data writing operation, after the index corresponding to the data writing operation 4 is updated to 1 or 2, the index corresponding to the data reading operation 4 using the data writing operation 4 as a target data writing operation should also be updated to 1 or 2, and the operands in the new instruction corresponding to the instruction 5 are updated to 1 or 2. Finally, according to each updated index, it can be determined that the total number of virtual registers that need to be used in the execution process of the second bytecode is 3, and the total number of virtual registers is respectively the virtual register identified by the index 1, the virtual register identified by the index 2, and the virtual register identified by the index 3.
After the total number of the virtual registers required to be used in the execution process of the second bytecode is obtained, the memory size of the target memory can be determined according to the total number. Illustratively, the total number may be multiplied by a preset memory size of the virtual register as the size of the target memory. For example, the preset memory size is 4, that is, the memory size of each virtual register is 4, and the total number of virtual registers that need to be used in the execution process of the second bytecode is 3, then the size of the target memory is 4 × 3 — 12. The target memory may be any continuous and free section of memory in the memory of the terminal device, and the target memory is used for storing the operation data generated in the execution process of the second bytecode. Based on the above example, the size of the target memory is 12, and the target memory includes 3 virtual registers, that is, the target memory is divided into 3 memory regions, and each memory region represents one virtual register.
In the embodiment of the present application, the second bytecode, that is, each new instruction in the second bytecode is executed, and the new instruction in the second bytecode has a structure of value id + opcode + operations. Upon execution of each new instruction in the second bytecode, the operation indicated by the opcode of the new instruction may be executed according to the virtual register identified by the index included in the new instruction. Specifically, the data writing operation included in the new instruction may be executed, and the data to be written is written into the virtual register identified by the value id; and executing the read data operation included in the new instruction, and reading needed data from the virtual register identified by the operands. For example, if a new instruction has a value id of 3 and operands of 2, and the opcode of the new instruction indicates that a write operation requires data a and a read operation requires data B, then the new instruction will be executed to write data a into the virtual register identified by index 3 and read data B from the virtual register identified by index 2. It should be noted that operands in the new instruction may be an immediate operand, and the virtual machine may determine, according to the operation code in the new instruction, whether a data reading operation included in the new instruction needs to read data from the memory, if the data needs to be read from the memory, it indicates that the operands are not the immediate operand, and if the data does not need to be read from the memory, it indicates that the operands are the immediate operand. In the case where operands are immediate operands, the virtual machine can directly use the operands to perform the logical operation indicated by the opcode. By the method, when the new instruction in the second byte code is executed, the virtual register which needs to be used currently can be quickly determined according to the value ID and operands in the new instruction, so that the execution speed of the instruction is accelerated.
As can be seen from the above, in the present application, a first bytecode to be executed is first obtained, the first bytecode is converted into a second bytecode in a custom format, the second bytecode includes an index corresponding to each read-write data operation during the execution of the first bytecode, then a section of target memory is determined based on the index, the target memory includes at least one virtual register, each virtual register is identified by a different index, and finally the second bytecode is executed based on the virtual register identified by each index in the second bytecode. According to the scheme, the first byte code to be executed is converted into the second byte code in the custom format, and the index corresponding to each read-write data operation in the execution process of the first byte code is added into the second byte code, so that the virtual register required to be used at present can be quickly determined according to each index when the virtual machine explains and executes the second byte code, and the performance of explaining and executing the byte code by the virtual machine can be improved.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
Fig. 2 shows a block diagram of a bytecode execution device according to an embodiment of the present application, and for convenience of description, only the relevant parts of the embodiment of the present application are shown.
The bytecode execution device 200 includes:
an obtaining unit 201, configured to obtain a first bytecode to be executed;
a converting unit 202, configured to convert the first bytecode into a second bytecode in a custom format, where the second bytecode includes an index corresponding to each read-write data operation during execution of the first bytecode;
a determining unit 203, configured to determine a segment of target memory based on the index, where the target memory includes at least one virtual register, and each virtual register is identified by a different index;
an execution unit 204 is configured to execute the second bytecode based on the virtual register identified by each index in the second bytecode.
Optionally, the converting unit 202 includes:
a traversal subunit, configured to traverse each instruction in the first bytecode according to an instruction execution order;
the index determining subunit is used for determining an index corresponding to read-write data operation included in the current instruction according to the meaning of the current instruction, and the current instruction is a currently traversed instruction;
a generating subunit, configured to generate a new instruction according to an index corresponding to the read-write data operation included in the current instruction and an operation code of the current instruction;
and the serialization subunit is used for serializing the new instruction corresponding to each instruction in the first bytecode to obtain the second bytecode.
Optionally, the executing unit 204 includes:
an instruction execution subunit, configured to execute a new instruction in the second bytecode;
and the operation execution subunit is used for executing the operation indicated by the operation code of the new instruction according to the virtual register identified by the index included in the new instruction.
Optionally, the index determining subunit includes:
the judging subunit is used for judging whether a data writing operation and a data reading operation exist in the read-write data operation included in the current instruction according to the meaning of the current instruction;
a first determining subunit, configured to, if there is a data writing operation in the read-write data operations included in the current instruction, perform self-increment on a preset count value, and use the self-incremented count value as an index corresponding to the data writing operation;
and a second determining subunit, configured to, if there is a data read operation in the read-write data operations included in the current instruction, use an index corresponding to a target data write operation as an index corresponding to the data read operation, where the target data write operation and the data read operation are used to operate on the same data.
Optionally, the generating subunit is specifically configured to splice an index corresponding to the read-write data operation included in the current instruction with the operation code of the current instruction, so as to obtain the new instruction.
Optionally, the determining unit 203 includes:
a total number determining subunit, configured to determine, based on the index, a total number of virtual registers that need to be used in an execution process of the second bytecode;
a memory size determining subunit, configured to determine a memory size of the target memory according to the total amount;
and the memory determining subunit is used for determining a free memory as the target memory according to the memory size.
Optionally, the memory size determining subunit is specifically configured to use a product of the total amount and a preset memory size of the virtual register as the size of the target memory.
As can be seen from the above, in the present application, a first bytecode to be executed is first obtained, the first bytecode is converted into a second bytecode in a custom format, the second bytecode includes an index corresponding to each read-write data operation during the execution of the first bytecode, then a section of target memory is determined based on the index, the target memory includes at least one virtual register, each virtual register is identified by a different index, and finally the second bytecode is executed based on the virtual register identified by each index in the second bytecode. According to the scheme, the first byte code to be executed is converted into the second byte code in the custom format, and the index corresponding to each read-write data operation in the execution process of the first byte code is added into the second byte code, so that the virtual register required to be used at present can be quickly determined according to each index when the virtual machine explains and executes the second byte code, and the performance of explaining and executing the byte code by the virtual machine can be improved.
Fig. 3 is a schematic structural diagram of a terminal device according to an embodiment of the present application. As shown in fig. 3, the terminal device 3 of this embodiment includes: at least one processor 30 (only one is shown in fig. 3), a memory 31, and a computer program 32 stored in the memory 31 and executable on the at least one processor 30, wherein the processor 30 executes the computer program 32 to perform the following steps:
acquiring a first bytecode to be executed;
converting the first byte code into a second byte code with a custom format, wherein the second byte code comprises an index corresponding to each read-write data operation in the execution process of the first byte code;
determining a section of target memory based on the index, wherein the target memory comprises at least one virtual register, and each virtual register is identified by different indexes;
and executing the second bytecode based on the virtual register identified by each index in the second bytecode.
Assuming that the above is the first possible implementation manner, in a second possible implementation manner provided on the basis of the first possible implementation manner, the converting the first bytecode into a second bytecode in a custom format includes:
traversing each instruction in the first byte code according to an instruction execution sequence;
determining an index corresponding to read-write data operation included by a current instruction according to the meaning of the current instruction, wherein the current instruction is a currently traversed instruction;
generating a new instruction according to the index corresponding to the read-write data operation included in the current instruction and the operation code of the current instruction;
and serializing new instructions corresponding to the instructions in the first byte codes to obtain the second byte codes.
In a third possible implementation form based on the second possible implementation form, the executing the second bytecode on the basis of the virtual registers identified by the respective indexes in the second bytecode includes:
executing a new instruction in the second bytecode;
and executing the operation indicated by the operation code of the new instruction according to the virtual register identified by the index included in the new instruction.
In a fourth possible implementation manner provided based on the second possible implementation manner, the determining, according to the meaning of the current instruction, an index corresponding to a read-write data operation included in the current instruction includes:
judging whether a data writing operation and a data reading operation exist in the read-write data operation included in the current instruction according to the meaning of the current instruction;
if the read-write data operation included in the current instruction has a data writing operation, performing self-increment on a preset count value, and taking the self-incremented count value as an index corresponding to the data writing operation;
and if the read-write data operation included in the current instruction comprises a read-write data operation, taking an index corresponding to a target write-data operation as an index corresponding to the read-write data operation, wherein the target write-data operation and the read-write data operation are used for operating the same data.
In a fifth possible implementation manner provided based on the second possible implementation manner, the generating a new instruction according to an index corresponding to a read-write data operation included in the current instruction and an opcode of the current instruction includes:
and splicing the index corresponding to the read-write data operation included in the current instruction with the operation code of the current instruction to obtain the new instruction.
In a sixth possible implementation manner provided on the basis of the first possible implementation manner, the determining a segment of target memory based on the index includes:
determining the total number of virtual registers required to be used in the execution process of the second bytecode based on the index;
determining the memory size of the target memory according to the total amount;
and determining a free memory as the target memory according to the memory size.
In a seventh possible implementation manner provided based on the sixth possible implementation manner, the determining the memory size of the target memory according to the total number includes:
and taking the product of the total amount and the preset memory size of the virtual register as the size of the target memory.
The terminal device 3 may be a desktop computer, a notebook, a palm computer, a cloud server, or other computing devices. The terminal device may include, but is not limited to, a processor 30, a memory 31. Those skilled in the art will appreciate that fig. 3 is only an example of the terminal device 3, and does not constitute a limitation to the terminal device 3, and may include more or less components than those shown, or combine some components, or different components, for example, and may further include an input/output device, a network access device, and the like.
The Processor 30 may be a Central Processing Unit (CPU), and the Processor 30 may be other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The storage 31 may be an internal storage unit of the terminal device 3, such as a hard disk or a memory of the terminal device 3. In other embodiments, the memory 31 may also be an external storage device of the terminal device 3, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like provided on the terminal device 3. Further, the memory 31 may include both an internal storage unit and an external storage device of the terminal device 3. The memory 31 is used for storing an operating system, an application program, a BootLoader (BootLoader), data, other programs, and the like, such as program codes of the computer programs. The above-mentioned memory 31 may also be used to temporarily store data that has been output or is to be output.
As can be seen from the above, in the present application, a first bytecode to be executed is first obtained, the first bytecode is converted into a second bytecode in a custom format, the second bytecode includes an index corresponding to each read-write data operation during the execution of the first bytecode, then a section of target memory is determined based on the index, the target memory includes at least one virtual register, each virtual register is identified by a different index, and finally the second bytecode is executed based on the virtual register identified by each index in the second bytecode. According to the scheme, the first byte code to be executed is converted into the second byte code in the custom format, and the index corresponding to each read-write data operation in the execution process of the first byte code is added into the second byte code, so that the virtual register required to be used at present can be quickly determined according to each index when the virtual machine explains and executes the second byte code, and the performance of explaining and executing the byte code by the virtual machine can be improved.
It should be noted that, for the information interaction, execution process, and other contents between the above-mentioned devices/units, the specific functions and technical effects thereof are based on the same concept as those of the embodiment of the method of the present application, and specific reference may be made to the part of the embodiment of the method, which is not described herein again.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned functions may be distributed as different functional units and modules according to needs, that is, the internal structure of the apparatus may be divided into different functional units or modules to implement all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
The embodiments of the present application further provide a computer-readable storage medium, where a computer program is stored, and the computer program, when executed by a processor, implements the steps in the above method embodiments.
Embodiments of the present application provide a computer program product, which, when running on a terminal device, causes the terminal device to execute the steps in the above-mentioned method embodiments.
The integrated unit may be stored in a computer-readable storage medium if it is implemented in the form of a software functional unit and sold or used as a separate product. Based on such understanding, all or part of the processes in the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium and can implement the steps of the embodiments of the methods described above when the computer program is executed by a processor. The computer program includes computer program code, and the computer program code may be in a source code form, an object code form, an executable file or some intermediate form. The computer-readable medium may include at least: any entity or apparatus capable of carrying computer program code to a terminal device, recording medium, computer Memory, Read-Only Memory (ROM), Random-Access Memory (RAM), electrical carrier wave signals, telecommunications signals, and software distribution medium. Such as a usb-disk, a removable hard disk, a magnetic or optical disk, etc. In certain jurisdictions, computer-readable media may not be an electrical carrier signal or a telecommunications signal in accordance with legislative and patent practice.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus/network device and method may be implemented in other ways. For example, the above-described apparatus/network device embodiments are merely illustrative, and for example, the division of the above modules or units is only one logical function division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A method for bytecode execution, comprising:
acquiring a first bytecode to be executed;
converting the first byte code into a second byte code with a custom format, wherein the second byte code comprises an index corresponding to each read-write data operation in the execution process of the first byte code;
determining a section of target memory based on the index, wherein the target memory comprises at least one virtual register, and each virtual register is identified by a different index;
executing the second bytecode based on virtual registers identified by respective indices in the second bytecode.
2. The bytecode execution method according to claim 1, wherein the converting the first bytecode into a second bytecode in a custom format includes:
traversing each instruction in the first bytecode according to an instruction execution sequence;
aiming at a current instruction, determining an index corresponding to read-write data operation included in the current instruction according to the meaning of the current instruction, wherein the current instruction is a currently traversed instruction;
generating a new instruction according to an index corresponding to the read-write data operation included in the current instruction and an operation code of the current instruction;
and serializing new instructions corresponding to all instructions in the first byte codes to obtain the second byte codes.
3. The bytecode execution method according to claim 2, wherein executing the second bytecode based on virtual registers identified by respective indices in the second bytecode includes:
executing a new instruction in the second bytecode;
and executing the operation indicated by the operation code of the new instruction according to the virtual register identified by the index included in the new instruction.
4. The bytecode execution method according to claim 2, wherein the determining, according to the meaning of the current instruction, an index corresponding to a read-write data operation included in the current instruction includes:
judging whether a data writing operation and a data reading operation exist in the read-write data operation included in the current instruction according to the meaning of the current instruction;
if the read-write data operation included in the current instruction has a data writing operation, performing self-increment on a preset count value, and taking the self-incremented count value as an index corresponding to the data writing operation;
and if the read-write data operation included in the current instruction comprises a read-write data operation, taking an index corresponding to a target write-data operation as an index corresponding to the read-write data operation, wherein the target write-data operation and the read-write data operation are used for operating the same data.
5. The bytecode execution method according to claim 2, wherein the generating a new instruction according to the index corresponding to the read-write data operation included in the current instruction and the operation code of the current instruction includes:
and splicing the index corresponding to the read-write data operation included in the current instruction with the operation code of the current instruction to obtain the new instruction.
6. The bytecode execution method of claim 1, wherein said determining a segment of target memory based on the index comprises:
determining the total number of virtual registers required to be used in the execution process of the second bytecode based on the index;
determining the memory size of the target memory according to the total number;
and determining an idle memory as the target memory according to the size of the memory.
7. The bytecode execution method according to claim 6, wherein the determining the memory size of the target memory according to the total number comprises:
and taking the product of the total number and the preset memory size of the virtual register as the size of the target memory.
8. A bytecode execution device, comprising:
the device comprises an acquisition unit, a processing unit and a control unit, wherein the acquisition unit is used for acquiring a first bytecode to be executed;
the conversion unit is used for converting the first byte code into a second byte code with a custom format, and the second byte code comprises an index corresponding to each read-write data operation in the execution process of the first byte code;
a determining unit, configured to determine a segment of target memory based on the index, where the target memory includes at least one virtual register, and each virtual register is identified by a different index;
and the execution unit is used for executing the second bytecode based on the virtual register identified by each index in the second bytecode.
9. A terminal device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the method according to any of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1 to 7.
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| CN202011465836.0A CN112506569B (en) | 2020-12-14 | 2020-12-14 | Byte code executing method, byte code executing device and terminal equipment |
| PCT/CN2020/139391 WO2022126710A1 (en) | 2020-12-14 | 2020-12-25 | Bytecode executing method, bytecode executing apparatus, and terminal device |
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