CN112505375A

CN112505375A - Circuit probe for electromagnetic shielding

Info

Publication number: CN112505375A
Application number: CN202010966176.8A
Authority: CN
Inventors: 彭经能; 王宪棠; 王敏哲; 赖启彰
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2019-09-16
Filing date: 2020-09-15
Publication date: 2021-03-16
Also published as: US20210080487A1; TW202113364A; US11726112B2

Abstract

A circuit probe for electromagnetic shielding, wherein the circuit probe comprises a shielding probe having a base and a conductive probe ring on the base. The shield is attached to the conductive probe ring and has an interior. The shield is configured to be positioned to contain the at least one integrated circuit formed on the wafer within an interior of the shield and to provide the at least one integrated circuit electromagnetic shield during testing of the at least one integrated circuit.

Description

Circuit probe for electromagnetic shielding

Technical Field

The disclosed embodiments relate to a circuit probe, and more particularly, to a circuit probe for electromagnetic shielding.

Background

In the fabrication of semiconductor devices, a large number of integrated circuits are formed on a semiconductor wafer. These individual integrated circuits are then typically tested at a stage of the semiconductor manufacturing process known as "wafer-level testing," which occurs before the individual integrated circuits are singulated into individual chips or dies. During wafer-level testing, these individual integrated circuits are inspected to detect failures and the corresponding die is marked as defective and excluded from subsequent packaging operations performed on the die.

Current advanced integrated circuits include components that require Radio Frequency (RF) testing of the integrated circuits during wafer level testing. This radio frequency testing includes extracting radio frequency parameters (e.g., S-parameters) to model the integrated circuit (modeling). The rf testing is performed at the Circuit Probe (CP) stage of the wafer level testing, with the test probes being positioned sequentially to electrically connect to each integrated circuit formed on the wafer. The test probes then apply and receive signals to and from each of the integrated circuits, thereby performing various tests on the integrated circuits. These tests typically include direct current trimming (DC trimming) of components in the integrated circuit, programming of one-time programmable (OTP) elements, and radio frequency testing as previously described. When performing radio frequency testing, electromagnetic waves that are not generated as part of the radio frequency testing, but are present in the environment of the wafer and the integrated circuits under test, may interfere with proper radio frequency testing of the integrated circuits.

Disclosure of Invention

According to some embodiments of the present disclosure, there is provided a circuit probe including a shield probe. The shielding probe includes a base, a conductive probe ring, and a shield can. The conductive probe is looped on the base. A shield is attached to the conductive probe ring and has an interior, the shield being configured to be positioned to include at least one integrated circuit formed on the wafer within the interior of the shield and to provide at least one integrated circuit electromagnetic shield during testing of the at least one integrated circuit.

According to some embodiments of the present disclosure, a circuit probe is provided that includes a shield probe and a test probe. The shielding probe includes a plurality of spaced apart conductive shielding elements, the shielding probe having an interior partially defined by the plurality of spaced apart conductive shielding elements, and the plurality of spaced apart conductive shielding elements configured to form a plurality of waveguides that provide electromagnetic shielding of electromagnetic waves external to the shielding probe. The test probe is inside the shield probe.

According to some embodiments of the present disclosure, a method of testing integrated circuits on a wafer is provided, including positioning a shield over the integrated circuits, the shield having an interior, and applying a plurality of electrical test signals to and receiving electrical test signals from the integrated circuits via a plurality of test contacts of a test probe in the interior of the shield, thereby testing the integrated circuits.

Drawings

Aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various features are not necessarily drawn to scale. In fact, the dimensions of the various features and geometries may be arbitrarily expanded or reduced for clarity.

Fig. 1 is a perspective view of a circuit probe including a shielding probe according to some embodiments.

Fig. 2 is a side view of the shielded probe of fig. 1 according to some embodiments.

Fig. 3A-3C illustrate shielding operations of the shielded probe of fig. 1 and 2, according to some embodiments.

Fig. 4A is a perspective view of a circuit probe including a shielding probe according to some embodiments.

Fig. 4B is a cross-sectional view of a circuit probe showing a circular conductive shielding element shielding the probe, according to some embodiments.

Fig. 5 is a cross-sectional view of a circuit probe including a shielded probe in which the conductive shielding element has a non-circular cross-section, according to some embodiments.

Fig. 6A is a perspective view of a circuit probe including a shield probe according to a further embodiment of the present disclosure.

Fig. 6B is a cutaway bottom view of a shielding probe according to further embodiments of the present disclosure.

Fig. 7A is a perspective view of a circuit probe including a shield probe having four conductive shield walls according to some embodiments.

Fig. 7B is a bottom view of a shielding probe according to some embodiments.

Fig. 8 is a perspective view illustrating the shield probes of fig. 1, 4A, 6A, or 7A positioned in contact with a conductive guard ring surrounding integrated circuits on a wafer, in accordance with some embodiments.

Figure 9 is a perspective view illustrating a shield probe including a conductive perimeter ring configured to be positioned over or in contact with an area of a wafer surrounding integrated circuits on the wafer, in accordance with some embodiments.

Fig. 10 is a perspective view illustrating the shielding probe of fig. 7A including four conductive shielding walls configured to be positioned over an area surrounding a wafer of integrated circuits under test and not in contact with the wafer, in accordance with some embodiments.

Fig. 11 is a perspective view of the shield probe of fig. 4A or 6A configured to be positioned over an area surrounding a wafer around an integrated circuit being tested and not in contact with the wafer, in accordance with some embodiments.

Fig. 12A-12F are plan views illustrating further embodiments of shield probes configured to surround a plurality of integrated circuits on a wafer, in accordance with some embodiments.

Figure 13A is an embodiment of a shield probe configured to surround an edge of a wafer according to some embodiments.

Fig. 13B is an embodiment of a shield probe configured to surround an outer perimeter of a mask boundary of a wafer according to some embodiments.

Fig. 14A and 14B illustrate a shielded probe including a multi-level shielding according to some embodiments.

Fig. 15 illustrates the use of the shielding probes of fig. 1-14B in circuit probe testing and Wafer Level Chip Scale Packaging (WLCSP) testing, in accordance with some embodiments.

Fig. 16 illustrates the application of the shielding probes of fig. 1-14B to chip-on-wafer-on-substrate (COWOS) testing, in accordance with some embodiments.

Fig. 17A to 17C show electromagnetic simulation results of a test with an existing circuit probe, electromagnetic simulation results of a test with a shield probe according to some embodiments, and electromagnetic simulation results of a test with a shield probe and a conductive guard ring according to some embodiments.

Fig. 18 illustrates the use of the shielded probe of fig. 1-14B in a 3 dimensional integrated circuit (3DIC) test, in accordance with some embodiments.

Fig. 19 illustrates the use of the shielding probes of fig. 1-14B in an integrated fanout (INFO) test, according to some embodiments.

Description of reference numerals:

100,400,500,600,700: circuit probe

102,402,502,602,702,900,1200,1202,1204,1206,1208,1210,1300,1304,1402,1404,1406,1408,1410,1412,1414a,1414b,1416a,1416b,1504,1606,1702,1704,1810,1902,1904: shielding probe

104,404,614,802,904,1000,1100,1302,1400,1502: wafer

106,406,506,606,908: conductive (shielding) element

106 a: first end

106b,406 b: second end

107,407,507,604,704,906: shielding grid/shielding cover

108,408,610,708: base seat

110,410,612,710,1812,1816,1910: conductive probe ring

112,412,615,800,1706: conductive guard ring

114,414,622,712: inner part

120: left side of the

122: right side of the

124: front side

126: rear side

416,616,912: dotted line

418: plane surface

420,618: arrow head

422,620,716: test probe

424,624,718: test contact

608,706,910: conductive shield plate/conductive shield wall

613,714: dotted line frame

902: conductive peripheral ring

1500: wafer level chip scale package device

1600: chip on wafer device on substrate

1602: chip and method for manufacturing the same

1604: silicon interposer

1700: metal plate

1802: three-dimensional integrated circuit

1804: multi-integrated circuit

1806: bottom die

1808: silicon wafer

1814: top die

1902: integrated fan-out package

1906: integrated circuit chip

1908: printed circuit board

a: width of

b: height

D: distance between two adjacent plates

IC: integrated circuit with a plurality of transistors

TE₁₀: mode(s)

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, if the specification states a first feature formed over or on a second feature, that embodiment may include the first feature in direct contact with the second feature, or that additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, in various examples, the present disclosure may use repeated reference characters and/or letters. Such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially related terms such as: the use of words of "below," "lower," "above," "upper," and the like in … … is used herein to facilitate describing the relationship of one element or feature to another element(s) or feature(s) in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be turned to a different orientation (rotated 90 degrees or at other orientations) and the spatially relative terms used herein should be interpreted accordingly.

Fig. 1 is a perspective view of a circuit probe 100 including a shield probe 102 according to some embodiments of the present disclosure. In the embodiment of fig. 1, the circuit probe 100 includes a shield probe 102 and a test probe (not shown), the shield probe being configured to surround the test probe and the integrated circuit IC on the wafer 104 during testing of the integrated circuit IC by the test probe, as will be described in more detail below. In the embodiment of fig. 1, the shielding probe 102 comprises a plurality of electrically conductive shielding elements 106 spaced apart and arranged in a shape forming a shielding grid or cage 107, the shielding grid or cage 107 providing electromagnetic shielding for the integrated circuit IC inside it, as will be described in more detail below. In the upper right part of this figure, the shielding probe 102 is also shown in a side view in dashed lines. Each conductive shield element 106 has a first end 106a attached to the base 108 of the shield probe 102 and has a second end 106b opposite the first end, the second end 106b configured to be positioned in contact with a conductive guard ring 112 on the wafer 104. More specifically, base 108, which in embodiments of the present disclosure is a Printed Circuit Board (PCB) or other suitable substrate, includes a conductive probe loop 110, and first ends 106a of the plurality of conductive shield elements 106 are spaced apart and connected to conductive probe loop 110. Where the base 108 is a printed circuit board, the conductive probe loop 110 is a conductive trace (trace) suitably formed on the printed circuit board and may have a shape other than the rectangular or square shape of FIG. 1. In the embodiment of fig. 1, the wafer 104 includes a conductive guard ring 112 formed on the wafer, the conductive guard ring 112 being around each integrated circuit IC. Conductive guard rings 112 are suitable conductive traces formed on the wafer around each integrated circuit IC. The second end 106b of the conductive shield element 106, which is indicated in the embodiment of fig. 1, is configured to contact a conductive guard ring 112 of a corresponding integrated circuit IC when testing the integrated circuit. As previously mentioned, the test probes are not shown in fig. 1, but the test probes will be positioned to extend into the interior 114 of the shield probe 102, as will be described in more detail below.

As seen in the side view portion of fig. 1, the plurality of electrically conductive shielding elements 106 are separated by a height b along a first dimension of the shielding grid 107 formed by these elements and have a width a along a second dimension of the shielding grid 107. Thus, the first ends 106a of the plurality of conductive shield elements 106 are connected to the conductive probe ring 110 and are separated by a height b. The spacing of the plurality of electrically conductive shield elements 106 at height b can be viewed as creating a small rectangular waveguide, and the height b and width a define the wavelength and frequency of the electromagnetic wave that can propagate in the waveguide. In this way, selecting the values of height b and width a can shield electromagnetic waves of a desired frequency, as will now be explained in more detail below with reference to fig. 2 and 3A-3C. A cartesian coordinate system having axes X, Y and Z is defined for shielding probe 102 in fig. 1, and shielding probe 102 will be described in more detail below with reference to fig. 2 and 3A-3C using the cartesian coordinate system. When describing a waveguide formed by adjacent conductive shield elements 106, the term "height" is used to describe distance b and the term "width" is used to describe distance a due to the orientation of these distances, as will be understood in the discussion below with respect to fig. 2 and 3A-3C.

Fig. 2 is a side view of the shielded probe 102 of fig. 1, and again shows the height b between the electrically-conductive shield elements 106 and the width a of these elements. A cartesian coordinate system having axes X, Y and Z is also defined in fig. 2 for shielding probe 102 and will be used to explain the structure and operating principles of the shielding probe in more detail. The height b between the conductive shielding elements 106 extends in a direction parallel to the Y-axis, while the width a of the conductive shielding elements extends parallel to the X-axis. The Z axis is not in the page of fig. 2. The operation of an adjacent pair of conductive shield elements 106 in forming waveguide 200 will now be described in more detail. A pair of adjacent conductive shield elements 106 forms such a waveguide 200 and operates as will now be described with reference to fig. 3A-3C.

Fig. 3A to 3C illustrate the shielding operation and the working principle of the waveguide 200 of the shielded probe 102. Adjacent pairs of conductive shield elements 106, in combination with corresponding portions of the conductive probe ring 110 and the conductive guard ring 112 extending between the two conductive shield elements, effectively form a rectangular waveguide 200 for propagating electromagnetic waves in a direction parallel to the Z-axis. FIG. 3A is a perspective view illustrating a rectangular waveguide 200 and illustrating X, Y and the Z-axis of the waveguide. As shown in fig. 3A, the propagation of waves along or parallel to the Z-axis is into or out of the page of this figure. Referring again to fig. 1, the propagation of electromagnetic waves parallel to the Z-axis corresponds to waves propagating from the exterior of the shielded probe 102 to the interior 114 of the shielded probe, such waves possibly interfering with the proper testing of the corresponding integrated circuit IC.

Each waveguide 200 has a permeability μ and a permittivity e, where permeability and permittivity are the values in air, respectively. As will be understood by those skilled in the art, the waveguide 200 functions as a high pass filter. The lateral dimension (transition dimension) of waveguide 200 is the width a of electrically-conductive shield element 106 and the height b between adjacent electrically-conductive shield elements. The larger of the two lateral dimensions, width a and height b, determines the cutoff frequency (cutoff frequency) fc of the waveguide. The cutoff frequency fc is independent of the length of the waveguide 200 along the Z-axis. In the rectangular waveguide 200, a transverse electric wave TE and a transverse magnetic wave TM can propagate through the waveguide. For transverse electric waves TE, the waveguide 200 has a mode of operation, generally denoted TE_mnWhere m is an integer associated with the X-axis dimension of waveguide 200, i.e., width a, and n is an integer associated with the Y-axis dimension of waveguide 200, i.e., height b.

In the rectangular waveguide 200, TE₁₀The mode is the main operation mode (m 1, n 0), in which case the width a is greater thanThe cut-off frequency fc of height b is fc ═ (c/2a), where c is the velocity of the electromagnetic wave in free space, about 3X10⁸M/s. In this mode, the cutoff wavelength λ c is 2 a/c. TE is shown in FIG. 3C₁₀Mode and shows that the integer m is expressed as the number of half-period changes of the electromagnetic wave along the X axis, at TE₁₀And 1 in the pattern. As shown in fig. 3B, in the waveguide 200, for the wavelength having a frequency fc (f) greater than the cutoff frequency fc>fc and λ<λ c) that enters the waveguide and undergoes internal reflection by the conductive elements of the waveguide 200 and propagates through the waveguide in the Z-axis direction. However, for signals having a frequency less than the cut-off frequency fc (f)<fc and λ>λ c) at a frequency f, the electromagnetic wave will not enter the waveguide and will not propagate through the waveguide, but will be reflected by the conductive elements of the waveguide 200 away from the waveguide entrance. In so doing, the waveguide 200 effectively operates as a filter or shield for electromagnetic waves having a frequency f less than the cutoff frequency fc. For the case where the height b is greater than the width a, the cutoff frequency of the waveguide 200 is fc ═ c/2 b.

Thus, by selecting the width a and height b associated with the conductive shielding elements 106 of the shielded probe 102, the respective waveguides 200 comprising these elements effectively block or shield electromagnetic waves of a particular frequency propagating outside the shielded probe and parallel to the Z-axis from entering the interior 114 of the shielded probe. The probe 102 is thereby effectively "shielded" from the integrated circuit IC in the probe's interior 114 from these external electromagnetic waves.

In this specification, the terms "internal" or "contained within" are used to describe the position of the integrated circuit IC when it is shielded by the shielding probe 102, as shown in fig. 1. In the embodiment of fig. 1, the shield 107, the pedestal 108, and the surface of the wafer 104 (including the integrated circuit ICs) define an interior 114 of the shield probe. The inner portion 114 corresponds to the three-dimensional space or area surrounded by these components, i.e. this area is surrounded by the conductive shield element 106 of the shield 107 and the top of this area is defined by the pedestal 108 and the bottom of this area is defined by the integrated circuit IC and the surface of the wafer 104 surrounding the integrated circuit IC including the conductive guard ring 112. Thus, when the shield probe 102 is in position over an integrated circuit IC under test, this integrated circuit is said to be in the "interior 114" or "contained within the interior 114" of the shield probe.

It should also be noted that in some embodiments of the shielded probe according to the present disclosure described below, the wafer does not include conductive guard rings or the shielded probe does not contact the surface of the wafer when testing integrated circuits ICs. It is again emphasized that even in these cases, when the probe is in position over the integrated circuit IC under test, whether or not the probe contacts the surface of the wafer, the integrated circuit IC under test will be described as being contained within the shielded probe. In these cases, the volume or area defining the interior of the shield probe will effectively comprise the area defined by the mask extending or projecting down to the wafer surface surrounding the integrated circuit IC being tested. Finally, in other embodiments of the shielding probe according to the present disclosure, which will be described below, the shielding probe is configured to shield a plurality of integrated circuits ICs. Again, in such embodiments, when the probe is in position over the plurality of integrated circuits, whether or not the probe contacts the surface of the wafer, the plurality of integrated circuit ICs will be described as being or contained within the shield probe.

Table 1 listed below shows example frequencies f of electromagnetic waves and corresponding wavelength λ and 1/2 λ values for each frequency.

TABLE 1

The 1/2 λ values in Table 1 correspond to TE₁₀The width a of the waveguide 200 of the operating mode. Thus, by selecting the dimensions of the shielding probe 102, i.e. the width a of the electrically conductive shielding elements 106 and the height b defining the spacing between adjacent electrically conductive shielding elements, the shielding probe provides shielding of electromagnetic waves having a frequency f smaller than the cut-off frequency fc of the waveguide 200.

Referring back to fig. 1, 2, and 3A-3C, the waveguide 200 depicted therein corresponds to one of the waveguides formed by the adjacent pair of conductive shielding elements 106 and corresponding portions of the conductive probe ring 110 and the conductive guard ring 112 on the left side 120 and the right side 122 of the shielded probe 102 in fig. 1. These waveguides 200 thus shield the integrated circuit IC under test from external electromagnetic waves propagating parallel to the Z-axis. The shielding probe 102 also includes conductive shielding elements 106 on the front side 124 and back side 126 of the shielding probe in fig. 1 and corresponding portions of the conductive probe ring 110 and the conductive guard ring 112. As shown in fig. 1, a waveguide 200, which includes a conductive shielding element 106 shielding the front side 124 and the back side 126 of the probe 102, shields an integrated circuit IC under test from external electromagnetic waves propagating parallel to the Y-axis. Further, the waveguide 200 described therein is similar to the waveguide formed by the conductive probe ring 110, the conductive shield element 106, and the conductive guard ring 112. The longest side dimension of the conductive probe loop 110 determines the cutoff frequency fc of the electromagnetic wave propagating parallel to the X-axis. Because the longest side dimension of the conductive probe loop 110 may be different from the larger of the width a and the height b, the cutoff frequency fc of the electromagnetic wave propagating parallel to the X axis may be different from the cutoff frequency fc of the electromagnetic wave propagating parallel to the Z axis and the Y axis. The continuous area of the wafer 104 coupled with the conductive guard ring 112 may increase the cutoff frequency fc of the electromagnetic wave traveling parallel to the X-axis, but attenuation of the electromagnetic wave propagating parallel to the X-axis through the wafer 104 may be limited due to the resistance of the wafer 104. The shielding probe 102 thus shields the integrated circuit IC under test (i.e. in the interior 114 of the shielding probe) from electromagnetic waves propagating in all directions and having a frequency less than the cut-off frequency fc.

Fig. 4A is a perspective view of a shielding probe 402 according to some embodiments of the present disclosure, and fig. 4B is a bottom view of the shielding probe 402 according to some embodiments of the present disclosure. The components 404-414 of the shield probe 402 are the same as or similar to the components 104-114 in the embodiment of fig. 1, and therefore will not be described in detail with reference to fig. 4A and 4B. In the embodiment of fig. 4A, the conductive probe ring 410 on the pedestal 408 is connected to a ground voltage reference node that receives a ground reference voltage, as indicated by the ground symbol via dashed line 416. This grounds (i.e., connects to the ground voltage reference node) all components of the shield probe 402 (i.e., the conductive probe ring 410, the conductive shield element 406, and the conductive guard ring 412).

In fig. 4A, plane 418 shows a point of the sectional bottom view in the direction indicated by arrow 420, and shows a point of the sectional view of fig. 4B. Fig. 4B shows that the cross-section of the conductive shield elements 406 is circular such that each conductive shield element is a cylindrical rod having a sharpened second end 406B for contacting the conductive guard ring 412 on the wafer 404. Fig. 4B also shows test probes 422, the test probes 422 being contained on the circuit probes 400 in the interior 414 of the shield probes 402. The test probes 422 are omitted from the view of fig. 4A to simplify the drawing. The test probes 422 include a plurality of test contacts 424, the test contacts 424 being represented by circles in the cross-sectional view of FIG. 4B. These test contacts 424 are configured to contact conductive pads or bumps of an integrated circuit IC (fig. 1) under test. The test contacts 424 are electrically conductive and in this way a test circuit (not shown) coupled to these test contacts provides electrical test signals to and receives electrical test signals from the integrated circuit IC, thereby testing the integrated circuit. As described above with reference to fig. 1, 2, and 3A-3B, the shielding probe 402 shields or isolates the interior 414 of the shielding probe from electromagnetic waves external to the circuit probe 400. Test contacts 424 of test probes 422 are located within interior 414 of shield probe 402 and in this manner shield the probe from or provide electrical isolation of these test contacts to allow proper testing of the integrated circuit IC under test. Referring again to fig. 1, the circuit probe 400 is identical to the circuit probe 100 of fig. 1 except that the conductive probe loop 410 is grounded in the circuit probe 400 and the conductive probe loop 110 is not grounded in the circuit probe 100.

Fig. 5 is another cross-sectional view of a circuit probe 500 according to some embodiments, wherein the conductive shielding element 506 of the shielding probe 502 has a non-circular cross-section. The structure of the circuit probe 500 is the same as the

circuit probe

100 or 400 of fig. 1, 4A, and 4B except for the sectional shape of the conductive shielding member 506. More specifically, in the embodiment of FIG. 5, the conductive shielding element 506 has an elliptical cross-section. In other embodiments, the electrically conductive shield element has a different cross-sectional shape, and the electrically conductive shield element of the shield probe of the present disclosure is not limited to the circular cross-section of fig. 1 and 4, or the elliptical cross-section of fig. 5.

Fig. 6A is a perspective view of a circuit probe 600 including a shielding probe 602 according to other embodiments of the present disclosure, and fig. 6B is a cutaway bottom view of the shielding probe 602 according to other embodiments of the present disclosure. The shielded probe 602 is similar to the shielded probes 102,402, and 502 described above, except that in the shielded probe 602, the shield enclosure 604 is formed by conductive shield elements 606 on two sides of the enclosure and by conductive shield tabs or walls 608 on the other two sides of the enclosure. Instead of having conductive shielding elements, such as shields 107 and 407 (fig. 1 and 4), on all four sides of the shield, shield 604 includes conductive shielding walls 608 forming both sides of the conductive shield. Each conductive shield wall 608 has a first side attached to one side of a conductive probe ring 612 and a second side opposite the first side. The shielding probe 602 includes a base 610 and a conductive probe ring 612 on the base, with one end of each conductive shielding element 606 and one end of each conductive shielding wall 608 attached to the conductive probe ring 612. The conductive probe ring 612 is grounded as indicated by dashed box 613. In this embodiment, the wafer 614 includes integrated circuits ICs (one of which is shown in fig. 6A) formed in the wafer, each integrated circuit including a conductive guard ring 615 on the wafer surrounding the respective integrated circuit.

The cross-sectional view of FIG. 6B of the circuit probe 600 is shown looking in the direction of arrow 618 at the plane indicated by dashed line 616. The circuit probe 600 includes a shield probe 602 and a test probe 620 within an interior 622 of the shield probe. The test probes 620 are not shown in fig. 6A to simplify the drawing. The test probes 620 include test contacts 624 and test the integrated circuit IC of the interior 622 of the shield probes 602, as operated as described above with respect to test probes 422 and test contacts 424 in fig. 4B. As shown in fig. 6B, each of the conductive shield elements 606 on the top and bottom sides of the shield 604 has a non-circular cross-sectional shape. The cross-section of the conductive shielding element 606 is elliptical in the embodiment of fig. 6B and is the same as or similar to the conductive shielding element 506 of fig. 5. It is also noted that in fig. 6A, the conductive shielding elements 606 are shown with a circular cross-section merely to simplify the drawing, and as clearly shown in fig. 6B, these conductive shielding elements have an oval cross-section.

In operation of the shielded probe 602, the pairs of conductive shield elements 606 at the top and bottom of the shield 604 act as waveguides, as previously described for the shields 107,407, and 507 in fig. 1, 4A, 4B, and 5. Thus, the waveguide formed by the conductive shielding element 606 and the conductive probe ring 612 and corresponding portion of the conductive guard ring 615 shields or isolates the test probe 620 within the interior 622 of the shielded probe 602 from electromagnetic waves propagating parallel to the Z-axis. The second side of the conductive shielding wall 608 of the shield probe 602 contacts the conductive guard ring 615 and serves to shield the test probe 620 from electromagnetic waves propagating parallel to the Y-axis. However, as can be appreciated by those skilled in the art, the conductive shielding wall 608 shields the interior 622 of the shielded probe 602 via the skin depth (skin depth) or skin effect (skin effect) of the conductive sheet, rather than acting as a waveguide. The skin depth of the conductive shielding wall 608 results in significant attenuation of electromagnetic waves that are outside of the shielded probe 602 and propagate parallel to the Y-axis. The probe 602 is shielded to shield the test probe 620 and the integrated circuit IC of the interior 622 of the probe 602 from external electromagnetic waves using two shielding methods. More specifically, as shown in fig. 6B, the shielded probe 602 provides shielding via a waveguide formed by a conductive shielding element 606 along the top and bottom sides of the shield 604, and via conductive shielding walls 608 forming the left and right sides of the shield.

Fig. 7A is a perspective view of a circuit probe 700 including a shield probe 702 according to other embodiments of the present disclosure, the shield probe 702 having a shield enclosure 704 including four conductive shield walls 706, and fig. 7B is a bottom view of the circuit probe 700 according to other embodiments of the present disclosure. The shield probe 702 is similar to the shield probes 102,402,502, and 602 described previously, except that in the shield probe 702, the shield enclosure 704 is formed by four conductive shield walls 706 on four sides of the enclosure and does not include a conductive shield element as part of the shield enclosure as in the previous embodiments. The shielding probe 702 also includes a base 708 and a conductive probe ring 710 on the base, with one end of each conductive shielding wall 706 attached to the conductive probe ring 710. The interior 712 of the shield probe 702 is inside the four conductive shield walls 706. The conductive probe ring 710 is grounded as indicated by dashed box 714. Fig. 7B shows a test probe 716, the test probe 716 including a plurality of test contacts 718 at the interior 712 of the shield probe 702. In operation of the shield probe 702, each conductive shield wall 706 functions to shield a test probe 716 at an interior 712 of the shield probe from electromagnetic waves propagating parallel to the Z-axis as well as the Y-axis. As described for the conductive shield wall 608 of fig. 6A, 6B, instead of functioning as a waveguide, the conductive shield wall 706 shields the interior 712 of the shield probe 702 via the skin depth or skin effect of the conductive patch, as will be understood by those skilled in the art.

Fig. 8 is a perspective view illustrating any of the shield probes 102,402,502,602, and 702 of fig. 1, 4A, 4B, 5, 6A, 6B, 7A, 7B positioned in contact with a conductive guard ring 800 surrounding an integrated circuit IC on a wafer 802, according to an embodiment of the present disclosure. In each of these embodiments, a conductive guard ring (such as conductive guard ring 800 of fig. 8) is formed on wafer 802 and around each integrated circuit IC on the wafer. The lower end or conductive shield wall (e.g., conductive shield wall 706 of fig. 7A, 7B) of the conductive shield element (e.g., conductive shield element 106 of fig. 1) of the corresponding shield can of the shielding probe contacts these conductive guard rings 800 when the shielding probe is positioned over the integrated circuit IC under test and provides shielding to the integrated circuit and the test probe (not shown in fig. 8) during such testing as described above. The formation of the conductive guard ring 800 on the wafer 802 occupies valuable space on the wafer, and thus, for at least this reason, it is not possible or desirable to form such a conductive guard ring on the wafer.

Fig. 9 is a perspective view illustrating a shielding probe 900 according to other embodiments of the present disclosure, the shielding probe 900 including a conductive perimeter ring 902 configured to be positioned over or in contact with an area of a wafer 904 surrounding integrated circuit ICs on the wafer 904. As shown in the enlarged partial view of the lower shielding probe in dashed line 912 in fig. 9, shielding probe 900 includes a shielding cage 906, and shielding cage 906 includes a conductive shielding element 908 or conductive shielding wall 910. The shield 906 comprises a conductive shielding element 908 on all four sides of the enclosure or a conductive shielding wall 910 on both sides of the enclosure forming the other two walls of the shield. Fig. 9 illustrates this structure by showing both the conductive shielding element 908 and the conductive shielding wall 910 on the left and right sides of the shield 906. Each of the left and right walls of the shield 906 is formed by a conductive shielding element 908 or a conductive shielding wall 910.

In this embodiment, the lower end of the conductive shielding element 908 is not sharp as in the previous embodiment, but is flat and attached to the conductive perimeter ring 902 as shown in the figure. The lower end of the conductive shield wall 910 is similarly attached to the conductive perimeter ring 902. The shield probe 900 also includes a pedestal 914 and a conductive probe ring 916, which is grounded in the embodiment of fig. 9. In operation, during testing of integrated circuits ICs on wafer 904, shield probes 900 can be positioned over the integrated circuits and conductive perimeter ring 902 is in contact with the surface of the wafer around the perimeter of the integrated circuits. Alternatively, the shielding probe 900 may be positioned a distance D above the integrated circuit IC under test as indicated by the dashed line 912. In this embodiment, the conductive perimeter ring 902 is a distance D above the surface of the wafer around the perimeter of the integrated circuit IC being tested. One or more conductive shield elements 908 may extend beyond the conductive perimeter ring 902 toward the integrated circuit IC and couple with the integrated circuit IC during testing.

Fig. 10 is a perspective view illustrating the shielding probes 702 of fig. 7A, the shielding probes 702 being positioned over an area of the wafer 1000 surrounding the wafer of integrated circuits ICs under test and not in contact with the wafer 1000, according to another embodiment. In operation, the shield probes 702 are positioned such that the lower ends of the conductive shield walls 706 are positioned a distance D above the surface of the wafer 1000 and above the integrated circuit IC under test. When the shield probe 702 is in this position, the test contacts of the test probe (not shown) will make contact with the contact pads of the integrated circuit IC, thereby testing the integrated circuit.

Fig. 11 is a perspective view of the shield probe 402 of fig. 4A or the shield probe 602 of fig. 6A configured to be positioned over an area of the wafer 1100 surrounding an integrated circuit IC under test without contacting this area of the wafer 1100 according to other embodiments of the present disclosure. In this embodiment, the wafer 1100 does not include conductive guard rings formed on the wafer around each integrated circuit IC.

Fig. 12A-12F are plan views illustrating other embodiments of shield probes configured to surround a plurality of integrated circuit ICs on a wafer, according to other embodiments of the present disclosure. Fig. 12A shows a shield probe 1200, which is represented by a dashed line, the shield probe 1200 being configured to surround three adjacent integrated circuits ICs contained in a row of such integrated circuits formed on a wafer. In fig. 12A to 12F, the integrated circuits ICs of one row are considered as a group of horizontally arranged integrated circuits, and the integrated circuits of one column are considered as a group of vertically arranged integrated circuits. Fig. 12B illustrates another embodiment of shield probes 1202, the shield probes 1202 being configured to surround a set of diagonally adjacent integrated circuit ICs in adjacent rows and columns of integrated circuits. Fig. 12C shows a shielded probe 1204 surrounding four adjacent integrated circuit ICs as shown. Fig. 12D shows a shielding probe 1206, the shielding probe 1206 comprising a plurality (in this example three) of individual shielding probes, each shielding probe surrounding a respective adjacent one of the integrated circuits IC of a row of integrated circuits. Fig. 12E shows shielding probes 1208, the shielding probes 1208 individually surrounding a set of diagonally adjacent integrated circuit ICs in adjacent rows and columns of integrated circuits on the wafer. Finally, fig. 12F shows shielding probes 1210, the shielding probes 1210 individually surrounding four adjacent integrated circuit ICs as shown. The embodiments of fig. 12A-12F illustrate that the shielded probes according to embodiments of the present application are not limited to surrounding individual integrated circuits ICs on a wafer, but may have different arrangements to surround multiple integrated circuits.

Fig. 13A is an embodiment of a shield probe 1300 configured to surround an edge of a wafer 1302, and fig. 13B is an embodiment of a shield probe 1304 configured to surround an outer perimeter of a mask boundary (mask boundary) of a wafer, according to other embodiments of the present disclosure. Thus, in fig. 13A, shield probes 1300 surround the edge of a wafer 1302 during testing of all integrated circuit ICs formed in the wafer. All integrated circuits ICs formed on the wafer 1302 have a "masking boundary" that corresponds to the outer perimeter of the combination of all integrated circuits formed in the wafer. The shield probes 1304 are configured to surround this mask boundary during testing of the integrated circuit.

Fig. 14A and 14B illustrate a shielded probe including a multi-level shielding according to other embodiments of the present disclosure. Fig. 14A shows a plurality of integrated circuits ICs formed in a wafer 1400. In this embodiment, shielding probes 1402 include multiple-level shielding probes. More specifically, the shield probes 1402 include individual-level shield probes 1404 that each surround an individual integrated circuit IC. Shielding probes 1402 also include group-level shielding probes 1406 that surround a group of individual integrated circuit ICs. Mask boundary level (mask boundary level) shield probes 1408 surround the mask boundaries of all integrated circuits ICs formed on the wafer 1400, and wafer-level shield probes 1410 are along the edge or perimeter of the wafer to surround the entire wafer. Fig. 14B shows a shielded probe 1412 that includes multiple levels of shielding at a repetition level. The shielding probes 1412 include dual group-

level shielding probes

1414a,1414b and repetitive mask

boundary shielding probes

1416a,1416 b.

Fig. 15 shows a shielded probe according to any of the embodiments of fig. 1-14B applied to a Circuit Probe (CP) test and a Wafer Level Chip Scale Package (WLCSP) test according to an embodiment of the present disclosure. In fig. 15, a wafer level chip scale package 1500 is formed on a wafer 1502 and shielded probes 1504 are used to test these wafer level chip scale packages, where the shielded probes 1504 may be any of the embodiments of the shielded probes described in fig. 1-14B.

Fig. 16 illustrates that the shielded probes of fig. 1-14B may also be used to test multiple Chip On Wafer (COWOS) devices 1600 in other embodiments of the present disclosure. The chip-on-substrate device 1600 utilizes wafer-level multi-chip (wafer-level multi-chip) packaging technology that combines multiple chips 1602 side-by-side on a silicon interposer 1604 to achieve better interconnect density and performance. The chips are bonded to the silicon interposer via micro-bumps (micro-bumps) to form a chip-on-wafer (COW). A package frame is added to each on-chip wafer to form the on-substrate wafer-on-wafer device 1600. The silicon interposer 1604 provides external connection locations using Through Silicon Vias (TSVs). These external connection locations can be used to couple the shield probes 1606 to one or more of the on-wafer-substrate-chip devices 1600 prior to singulation into separate on-wafer-chip devices 1600.

17A-17C illustrate results of electromagnetic simulations of prior circuit probe testing, using shielded probes according to some embodiments of the present disclosure, and using shielded probes according to some embodiments and conductive guard rings. Fig. 17A shows a prior art circuit probe without any shielding except for a metal plate 1700 on top of the circuit probe, and the corresponding graph shows the simulation results in the corresponding frequency range. Fig. 17B shows a shielded probe 1702 according to an embodiment of the present disclosure, and the simulation results are shown in the corresponding figure. The shield probes 1702 do not include conductive guard rings on the wafer. Fig. 17C shows a shielded probe 1704 including a conductive guard ring 1706 on a wafer and corresponding simulation results are shown in the graph. The shielded probe 1702 provides significant attenuation (-100dB) of electromagnetic signals in the frequency range of 2.3 to 2.7GHz compared to the prior art circuit probe of FIG. 17A (-70dB), and the shielded probe 1704 with the conductive guard ring 1706 provides further attenuation (-110 dB).

The shielded probe of fig. 1-14B may also be used to test a three-dimensional integrated circuit (3DIC) as shown in fig. 18, where two three-dimensional integrated circuits 1802 are shown for clarity. The three-dimensional integrated circuit 1802 includes multiple-integrated circuits (multi-integrated circuits) 1804, the multiple integrated circuits 1804 being stacked and bonded to each other using bottom dies 1806 on a silicon wafer 1808. When dies are stacked on top of each other, probe testing may occur. The shield probes 1810 are shown coupled to a conductive probe ring 1812 on a top die 1814 of the three-dimensional integrated circuit 1802. Alternatively, the shield probes may be sized to couple to a conductive probe ring 1816 (not shown coupled to the shield probes) around the bottom die 1806 on the silicon wafer 1806.

The shield probes of fig. 1-14B may also be used to test integrated circuits packaged using integrated fanout (INFO) technology. Referring to fig. 19, two integrated fan-out packages 1902 are shown, one integrated fan-out package 1902 coupled to shield probes 1904 and one second integrated fan-out package 1902 for clarity. The integrated circuit chip 1906 is coupled to a printed circuit board 1908. Conductive probe loops 1910 on printed circuit board 1908 are used to couple to shield probes 1904.

In an embodiment of the present disclosure, the circuit probes include shielding probes that provide electromagnetic shielding for integrated circuits on a wafer being tested. This enables the integrated circuit to be tested also reliably.

In some embodiments, a circuit probe includes a shield probe having a base and a conductive probe ring on the base. The shield is attached to the conductive probe ring and has an interior space. The shield is configured to be positioned to contain at least one integrated circuit formed on the wafer within an interior of the shield and to provide electromagnetic shielding to the at least one integrated circuit during testing of the at least one integrated circuit. In some embodiments, the shield includes a plurality of conductive shield members, each conductive shield member having a first end and a second end opposite the first end, the first ends of the plurality of conductive shield members being spaced apart and connected to the conductive probe ring. In some embodiments, each of the conductive shielding elements has a non-circular cross-section. In some embodiments, each second end of the electrically conductive shield element is sharp. In some embodiments, the shield includes a plurality of conductive shield walls, each conductive shield wall having a first side attached to the conductive probe ring and a second side opposite the first side. In some embodiments, the shield can includes four conductive shield walls. In some embodiments, the shield includes a conductive perimeter ring and a plurality of conductive shield elements extending between the conductive perimeter ring and the conductive probe ring. In some embodiments, each of the plurality of conductive shield elements has a circular cross-section. In some embodiments, the circuit probe further includes a first conductive shield wall extending between the conductive perimeter ring and the conductive probe ring and a second conductive shield wall extending between the conductive perimeter ring and the conductive probe ring. In some embodiments, the conductive probe ring is coupled to a ground voltage reference node configured to receive a ground reference voltage. In some embodiments, the circuit probe further includes a test probe positioned inside the shield probe.

In other embodiments, the circuit probe includes a shielded probe having a plurality of spaced apart conductive shielding elements. The shielding probe has an interior defined by a plurality of spaced apart conductive shielding elements, and the plurality of spaced apart conductive shielding elements are configured to form a plurality of waveguides that provide electromagnetic shielding of electromagnetic waves external to the shielding probe. The test probes are positioned inside the shield probes. In some embodiments, each of the spaced apart conductive shield elements comprises a cylindrical rod. In some embodiments, each of the spaced apart conductive shielding elements has a width, and the spaced apart conductive shielding elements are spaced apart by a height, the width and the height having values that form a rectangular waveguide having a desired cutoff frequency. In some embodiments, the shielding probe further comprises a plurality of conductive shielding walls.

Other embodiments are a method of testing integrated circuits on a wafer. The method includes positioning a shield over the integrated circuit. The shield has an interior. The method then includes applying and receiving electrical test signals to and from the integrated circuit via the test contacts of the test probe inside the shield can, thereby testing the integrated circuit. In some embodiments, positioning the shield includes positioning the shield to contact a surface of the wafer surrounding the integrated circuits. In some embodiments, positioning the shield includes positioning the shield above a surface of the wafer surrounding the integrated circuits and at a distance not in contact with the surface. In some embodiments, the wafer includes a plurality of integrated circuits, and wherein positioning the shield further includes positioning the shield around the plurality of integrated circuits. In some embodiments, the wafer includes an edge, and wherein positioning the shield further comprises positioning the shield around the edge of the wafer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that the present disclosure may be readily utilized as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent arrangements do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A circuit probe for electromagnetic shielding, comprising:

a shielded probe, comprising:

a base;

a conductive probe ring on the base; and

a shield attached to the conductive probe ring and having an interior, the shield configured to be positioned to contain at least one integrated circuit formed on a wafer in the interior of the shield and to provide the at least one integrated circuit electromagnetic shield during testing of the at least one integrated circuit.