CN112491417A

CN112491417A - Analog-to-digital converter

Info

Publication number: CN112491417A
Application number: CN201910864360.9A
Authority: CN
Inventors: 陈志龙; 黄诗雄
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2019-09-12
Filing date: 2019-09-12
Publication date: 2021-03-12

Abstract

The invention discloses an analog-digital converter which is used for receiving an analog input signal and generating a digital code. The analog-to-digital converter comprises a delta-sigma modulator, a down-conversion filter and a detection circuit. The delta-sigma modulator includes a loop filter, a quantizer and a digital-to-analog converter. The loop filter is used for receiving the analog input signal. The quantizer is coupled to the loop filter and is configured to quantize an output of the loop filter to generate a digital output signal. The digital-to-analog converter is coupled with the quantizer and the loop filter. The down filter is coupled to the delta-sigma modulator for converting the digital output signal into the digital code. The detection circuit is coupled to the delta-sigma modulator and is used for detecting a node voltage of the delta-sigma modulator and generating a control signal. The control signal is used to control the loop filter, the quantizer, a feedback path of the delta-sigma modulator, and/or a feedforward path of the delta-sigma modulator.

Description

Analog-to-digital converter

Technical Field

The present invention relates to analog-to-digital converters (ADCs), and more particularly to ADCs based on delta modulators.

Background

A sigma-delta modulator (SDM) is a common means of implementing an ADC, however, the signal applied to a SDM typically has the following characteristics: out-of-band signals exist outside the signal bandwidth (signal bandwidth) of the in-band signal, which have larger amplitudes (magnitudes) than the in-band signal, and which interfere with the delta-sigma modulator may be referred to as image (image) or blocker (blocker). Therefore, detecting and suppressing these unwanted out-of-band signals is an important issue in the art.

Disclosure of Invention

In view of the shortcomings of the prior art, an object of the present invention is to provide an ADC to improve the stability of the ADC.

The invention also discloses an analog-digital converter which is used for receiving an analog input signal and generating a digital code. The analog-to-digital converter comprises a delta-sigma modulator, a down-conversion filter, a detection circuit and a control circuit. The delta-sigma modulator includes a loop filter, a quantizer and a digital-to-analog converter. The loop filter is used for receiving the analog input signal. The quantizer is coupled to the loop filter and is configured to quantize an output of the loop filter to generate a digital output signal. The digital-to-analog converter is coupled with the quantizer and the loop filter. The down filter is coupled to the delta-sigma modulator for converting the digital output signal into the digital code. The detection circuit is coupled to the delta-sigma modulator and is used for detecting a node voltage of the delta-sigma modulator and generating a detection result. The control circuit is coupled to the detection circuit and used for generating a control signal according to the detection result. The control signal is used to control the loop filter, the quantizer, a feedback path of the delta-sigma modulator, and/or a feedforward path of the delta-sigma modulator.

The ADC provided by the invention detects the node voltage of the delta-sigma modulator by using the detection circuit, and adaptively adjusts the ADC according to the detection result so as to improve the stability of the ADC and reduce the power consumption. Compared with the traditional technology, the ADC provided by the invention can detect and inhibit the unnecessary out-of-band signals, so that the operation of the ADC is more stable.

The features, implementations, and technical effects of the present invention are described in detail below with reference to the accompanying drawings.

Drawings

FIG. 1 is a circuit diagram of an ADC according to an embodiment of the present invention;

FIG. 2 is a circuit diagram of a resonator according to an embodiment of the present invention;

FIG. 3 is a circuit diagram of a clamp circuit according to an embodiment of the present invention;

FIG. 4 is a circuit diagram of an ADC according to another embodiment of the present invention;

FIG. 5 is a functional block diagram of a detection circuit according to an embodiment of the present invention; and

FIG. 6 is a functional block diagram of a detection circuit according to another embodiment of the present invention.

Description of the symbols

10. 15 analog-to-digital converter

100 low-pass filter

200 delta-sigma modulator

210 loop filter

212a, 212b, 500 resonator

214. 240 switch

220 quantizer

230D/A converter

245 feedback path

250 impedance circuit

255 feed forward path

300a, 300b, 300c, 300d detection circuit

400a, 400b, 400c, 400d clamp circuits

900 frequency-reducing filter

Cd 1-Cd 4, Cdx control signals

S1-S10, S control signal

Vin analog input signal

Dout digital output signal

D digital code

510. 520 integrator

512. 522 operational amplifier

530 impedance

532 variable resistor

412. 414, 416, 418 transistors

N1, N2 node

610a, 610b integrator or operational amplifier

700 control circuit

800 memory

DR 1-DR 4, DRx, DR detection result

310 low-resolution analog-to-digital converter

320 area control circuit

330 comparator

Vn node voltage

Detailed Description

The technical terms in the following description refer to the conventional terms in the technical field, and some terms are explained or defined in the specification, and the explanation of the some terms is based on the explanation or the definition in the specification.

The present disclosure includes a delta-sigma modulator based ADC. Since some of the elements included in the ADC of the present invention may be known elements alone, details of known elements will be omitted from the following description without affecting the full disclosure and feasibility of the invention.

Fig. 1 is a circuit diagram of an ADC according to an embodiment of the invention. The ADC 10 is an ADC based on a delta-sigma modulator, and includes a low-pass filter (LPF) 100, an SDM 200, a down-conversion filter (reduction filter)900, a plurality of detection circuits 300 (including a detection circuit 300a, a detection circuit 300b, a detection circuit 300c, and a detection circuit 300d in the example of fig. 1), and a plurality of clamp circuits 400 (including a clamp circuit 400a, a clamp circuit 400b, a clamp circuit 400c, and a clamp circuit 400d in the example of fig. 1). The low-pass filter 100 low-pass filters the analog input signal Vin, and the SDM 200 converts the low-pass filtered analog input signal Vin into a digital output signal Dout, which is processed by the down-converter 900 to generate the digital code D. The digital code D is the output of the ADC 10. The operation of the down filter 900 is well known in the art and will not be described further.

SDM 200 includes a loop filter (loop filter)210, a quantizer 220, a digital-to-analog converter (DAC) 230, a switch 240, and an impedance circuit 250. Loop filter 210 receives and filters low-pass filtered analog input signal Vin and includes resonator 212a, resonator 212b, and switch 214. The quantizer 220 is coupled to the loop filter and is used for quantizing the output of the loop filter 210 to generate a digital output signal Dout. The switch 240 is coupled between the DAC 230 and the loop filter 210. The operation principle of the SDM 200 is well known to those skilled in the art, and thus, will not be described in detail. The order of the loop filter 210 in fig. 1 is merely an example and is not intended to limit the present invention.

The resonator 212a is controlled by a control signal S1; the resonator 212b is controlled by a control signal S2; switch 214 is controlled by control signal S3; the quantizer 220 is controlled by a control signal S4; switch 240 is controlled by control signal S5; impedance circuit 250 is controlled by control signal S6; and the clamp circuits 400a to 400d are controlled by the control signals S7 to S10, respectively.

The detection circuit 300 detects several node voltages of the SDM 200 and generates the control signal Cdx (in the example of FIG. 1, x is an integer and 1 ≦ x ≦ 4). More specifically, the detection circuit 300a detects the voltage at the input of the SDM 200 (i.e., the output of the low pass filter 100, the input of the resonator 212 a) and generates the control signal Cd 1; the detection circuit 300b detects the voltage of the internal node of the resonator 212a, and generates a control signal Cd 2; the detection circuit 300c detects the output voltage of the resonator 212a (i.e., the input voltage of the resonator 212 b), and generates a control signal Cd 3; the detection circuit 300d detects the output voltage of the resonator 212b (i.e., the input voltage of the quantizer 220), and generates the control signal Cd 4. The control signal Cdx may be used to control: (1) a loop filter 210; (2) a quantizer 220; (3) feedback path 245 of SDM 200; (4) the feed-forward path 255 of the SDM 200; and (5) a clamp circuit 400. The following discussion is separately directed to the various control scenarios described above.

Scenario (1): the control signal Cdx controls the loop filter 210. Referring to fig. 2, fig. 2 is a circuit diagram of a resonator 500 according to an embodiment of the invention. The resonator 500 includes an integrator 510, an integrator 520, and an impedance 530. The resonators 212a and 212b of fig. 1 may be implemented as a resonator 500. The integrator 510 and the integrator 520 each include a resistor R, a capacitor C, and an

operational amplifier

512 or 522, the connection of the components is as shown in fig. 2, and the operation principle of the integrator 510 and the integrator 520 is well known to those skilled in the art and therefore will not be described again. The impedance 530 is located in the feedback path of the resonator 500, and has one end coupled to the output end of the operational amplifier 522 of the integrator 520 and the other end coupled to one of the input ends of the operational amplifier 512 of the integrator 510. The impedance 530 includes a variable resistor 532. Integrator 510 and/or integrator 520 may operate in a passive mode under the control of control signal S1. More specifically, the control signal S1 may turn off the operational amplifier 512 and/or the operational amplifier 522, such that only passive components (i.e., the resistor R and the capacitor C) remain in the integrator 510 and the integrator 520. Turning off the operational amplifier 512 and/or the operational amplifier 522 helps stabilize the circuit when the mirroring or blocking in the SDM 200 is too large. In addition, turning off the operational amplifier 512 and/or the operational amplifier 522 has the technical effect of saving power.

Returning to fig. 1, the control signal Cdx may also reduce the order of the loop filter 210. More specifically, when the switch 214 is controlled by the control signal S3 to be turned on, the resonator 212a is bypassed (bypass), which is equivalent to two-step down of the order of the loop filter 210. The bypass resonator 212a is equivalent to the control resonator 212a being inactive (inactive). Reducing the order of the loop filter 210 helps stabilize the circuit when the mirroring or blocking in the SDM 200 is too large. In addition, reducing the order of the loop filter 210 also has the technical effect of saving power.

Scenario (2): the control signal Cdx controls the input operating range of the quantizer 220. More specifically, the detection circuit 300c may measure the output swing (output swing) of the resonator 212a, thereby turning on/off the comparator in the quantizer 220 or adjusting the binary search cycle (binary search cycle) of the quantizer 220. For example, when the detection circuit 300c detects that the output swing of the resonator 212a is smaller than a first predetermined value (representing that the most significant bit of the digital output signal Dout may be logic 0) or larger than a second predetermined value (representing that the most significant bit of the digital output signal Dout may be logic 1) (the second predetermined value is larger than the first predetermined value), the control signal S4 turns off the comparator corresponding to the higher bit in the quantizer 220, or controls the quantizer 220 to skip the first cycles corresponding to the higher bit in the binary search. In other words, the input working range of the quantizer 220 may be the number of active comparators or the number of cycles of the binary search actually performed.

Scenario (3): the control signal Cdx controls the switch 240 to couple the output of the DAC 230 to either the input of the resonator 212a or the input of the resonator 212 b. When the resonator 212a is bypassed, the control signal Cdx may conformingly control the switch 240 to couple the output of the DAC 230 to the input of the resonator 212 b. When the resonator 212a is not bypassed, the control signal Cdx may control the switch 240 to couple the output of the DAC 230 to the input of the resonator 212a or the input of the resonator 212 b.

Scenario (4): the control signal Cdx controls the impedance circuit 250. The feed-forward path 255 connects the input of the loop filter 210 and the output of the loop filter 210 and includes an impedance circuit 250. The impedance of the impedance circuit 250 is adjustable (e.g., the impedance circuit 250 includes a variable resistor and/or a variable capacitor), and the control signal S6 adjusts the feed forward of the SDM 200 by adjusting the equivalent impedance of the impedance circuit 250.

Scenario (5): the control signal Cdx adjusts the clamping voltage of the clamping circuit 400 to limit the voltage value of the corresponding node, thereby suppressing mirroring or blocking, and making the circuit more stable.

Referring to fig. 2, the detection circuit 300b is coupled to the output terminal of the integrator 510 and the input terminal of the integrator 520, and is used for detecting the voltage of the internal node of the resonator 500 to generate the control signal Cd 2. The clamp circuit 400b is coupled to the output terminal of the integrator 510 and the input terminal of the integrator 520, and is used for limiting the node voltage of the output terminal of the integrator 510 and the input terminal of the integrator 520. Note that the detection circuit 300 and the clamping circuit 400 electrically connected to the internal node of the resonator 212b are not shown in fig. 1 for simplicity, however, those skilled in the art can implement the detection circuit 300 and the clamping circuit 400 according to the disclosure of fig. 1 and 2.

In some embodiments, the aforementioned control signal Cdx is used to control an element electrically connected to the detection circuit 300 that generates the control signal Cdx. More specifically, the control signal S1 may be the control signal Cd1, the control signal Cd2, or the control signal Cd 3; the control signal S2 may be the control signal Cd3 or the control signal Cd 4; the control signal S3 may be the control signal Cd1 or the control signal Cd 2; the control signal S4 may be the control signal Cd 4; the control signal S7 may be the control signal Cd 1; the control signal S8 may be the control signal Cd 2; the control signal S9 may be the control signal Cd 3; and the control signal S10 may be the control signal Cd 4. Additionally, control signal S5 may be equal to control signal S3; the control signal S6 may be any one of the control signals Cdx.

In other embodiments, any one of the control signals S1-S10 may be equal to any one of the control signals Cd 1-Cd 4.

Fig. 3 is a circuit diagram of a clamp circuit 400 according to an embodiment of the invention. The clamp circuit 400 mainly includes a transistor 412, a transistor 414, a transistor 416, a transistor 418, and a plurality of switches. The clamping voltage (i.e., the voltage difference between the node N1 and the node N2) of the clamp circuit 400 may be adjusted by switching the plurality of switches. The node N1 and the node N2 are electrically connected to the output terminals of the integrator or operational amplifier 610a and the integrator or operational amplifier 610b, so that the output voltages of the integrator or operational amplifier 610a and the integrator or operational amplifier 610b are limited to the clamping voltage of the clamping circuit 400. The number of transistors and the number of switches of the clamp circuit 400 are not limited to those shown in fig. 3, and the operation principle of the clamp circuit 400 is well known in the art, and therefore will not be described herein again. Similar to the

integrators

510 and 520, the integrators or op-

amps

610a and 610b may be adjusted to operate in a passive mode.

Fig. 4 is a circuit diagram of an ADC according to another embodiment of the invention. The embodiment of fig. 4 is similar to the embodiment of fig. 1, except that the ADC 15 of fig. 4 further includes a control circuit 700 and a memory 800. In the embodiment of fig. 4, the control signal S (including S1 to S10) is generated by the control circuit 700 according to the detection result DR (including DR1 to DR4) of the detection circuit 300, rather than being directly generated by the detection circuit 300. More specifically, the control circuit 700 may be a circuit or an electronic component having a program execution capability, such as a central processing unit, a microprocessor, a micro-processing unit, or a digital signal processor, which is controlled by executing program codes or program instructions stored in the memory 800. In some embodiments, the memory 800 stores a lookup table, and the control circuit 700 uses the detection result DR to find out a corresponding control mode in the lookup table, so as to suppress mirroring or blocking in the SDM 200 and achieve the technical effect of saving power.

Compared to the ADC 10 of fig. 1, the ADC 15 of fig. 4 can simultaneously consider voltages of multiple nodes of the SDM 200 to make a comprehensive consideration of the above control scenarios, thereby achieving the following preferred combination of circuit characteristics: the order of the loop filter 210; coefficients of a Signal Transfer Function (STF) and/or a Noise Transfer Function (NTF); the amplitude of oscillation; the clamping voltage of the clamping circuit 400; maximum signal-to-noise ratio (SNR); maximum dynamic range (dynamic range), maximum vector magnitude of Error (EVM); maximum swing stability (swing stability); maximum blocking (coexistence) ability (blocker (co-existence) ability); and the lowest power consumption. The embodiment of FIG. 1 has faster response time, i.e., faster circuit adjustment; the embodiment of fig. 4 has a more comprehensive and diverse adjustment strategy. Please note that, the control circuit 700 of fig. 4 can also be adjusted for the above-mentioned situations; in other words, at least one of the control signals S1-S10 has no dependency on other control signals.

FIG. 5 is a functional block diagram of an embodiment of a detection circuit 300. The detection circuit 300 includes a low resolution ADC 310 and a zone control circuit 320. The low-resolution ADC 310 converts the node voltage Vn into a detection result DRx (in the example of fig. 4, x is an integer and is greater than or equal to 1 and less than or equal to 4), and the area control circuit 320 generates a control signal Cdx according to the detection result DRx. The number of bits of the low-resolution ADC 310 is smaller than the number of bits of the

ADCs

10 and 15. For example, the low resolution ADC 310 can be implemented as a 2-bit ADC to obtain the detection result DRx quickly. The area control circuit 320 may be a logic circuit formed by a plurality of transistors, and those skilled in the art can implement the area control circuit 320 according to the above. When the detection circuit 300 of fig. 5 is applied to the embodiment of fig. 4, the detection circuit 300 includes the low resolution ADC 310 but does not include the area control circuit 320. When the node voltage Vn is large (e.g., the swing of the node is large due to the presence of mirroring or blocking), the detection result DRx is also large.

Fig. 6 is a functional block diagram of another embodiment of a detection circuit 300. The detection circuit 300 includes a comparator 330 and a region control circuit 320. The comparator 330 compares the node voltage Vn with a predetermined voltage to generate a detection result DRx, and the area control circuit 320 generates a control signal Cdx according to the detection result DRx. The comparator 330 can be considered as a one-bit low resolution ADC 310. When the detection circuit 300 of fig. 6 is applied to the embodiment of fig. 4, the detection circuit 300 includes the comparator 330 but does not include the area control circuit 320.

In summary, the ADC of the present invention utilizes the detection circuit to detect the node voltage of the delta-sigma modulator, and adaptively adjusts the ADC according to the detection result, so as to improve the stability of the ADC and reduce the power consumption.

It should be noted that the shapes, sizes, proportions and the like of the elements in the drawings are illustrative only, and are not intended to limit the invention, which is understood by those skilled in the art.

Although the embodiments of the present invention have been described above, the embodiments are not intended to limit the present invention, and those skilled in the art can make variations on the technical features of the present invention according to the explicit or implicit contents of the present invention, and all such variations may fall within the scope of the patent protection sought by the present invention.

Claims

1. An analog-to-digital converter for receiving an analog input signal and generating a digital code, comprising:

a delta-sigma modulator, comprising:

a loop filter for receiving the analog input signal;

a quantizer, coupled to the loop filter, for quantizing an output of the loop filter to generate a digital output signal; and

a digital-to-analog converter coupled to the quantizer and the loop filter;

a down filter coupled to the delta-sigma modulator for converting the digital output signal into the digital code; and

a detection circuit coupled to the delta-sigma modulator for detecting a node voltage of the delta-sigma modulator and generating a control signal;

wherein the control signal is used to control the loop filter, the quantizer, a feedback path of the delta-sigma modulator, and/or a feedforward path of the delta-sigma modulator.

2. An analog to digital converter as recited in claim 1, wherein said loop filter comprises a resonator, said resonator comprises an operational amplifier, and said control signal is used to turn off said operational amplifier.

3. An analog to digital converter as claimed in claim 1, wherein the loop filter comprises a resonator and the control signal is used to control the resonator to be inoperative.

4. The adc of claim 3, wherein the resonator is a first resonator, the loop filter further comprises a second resonator, an input of the second resonator is coupled to an output of the first resonator, the sigma delta modulator further comprises a switch coupled between the loop filter and the dac, and the control signal is used to control the switch such that an output of the dac is coupled to the input of the second resonator when the first resonator is inactive.

5. The adc of claim 1, wherein the loop filter comprises a first resonator and a second resonator, an input terminal of the second resonator is coupled to an output terminal of the first resonator, the sigma-delta modulator further comprises a switch coupled between the loop filter and the dac, and the control signal is used to control the switch to control an output terminal of the dac to be coupled to an input terminal of the first resonator or the input terminal of the second resonator.

6. The analog-to-digital converter of claim 1, wherein the feedforward path comprises an impedance circuit, and the control signal is used to adjust an equivalent impedance of the impedance circuit.

7. The analog-to-digital converter of claim 1, wherein the control signal is used to control an input operating range of the quantizer.

8. The adc of claim 1, wherein the adc further comprises a clamping circuit coupled to the delta-sigma modulator, the control signal being used to control a clamping voltage of the clamping circuit.

9. The ADC of claim 1, wherein the detection circuit comprises a low resolution ADC, and the number of bits of the low resolution ADC is smaller than the number of bits of the ADC.

10. An analog-to-digital converter for receiving an analog input signal and generating a digital code, comprising:

a delta-sigma modulator, comprising:

a loop filter for receiving the analog input signal;

a digital-to-analog converter coupled to the quantizer and the loop filter;

a down filter coupled to the delta-sigma modulator for converting the digital output signal into the digital code;

a detection circuit coupled to the delta-sigma modulator for detecting a node voltage of the delta-sigma modulator and generating a detection result; and

a control circuit coupled to the detection circuit for generating a control signal according to the detection result;