CN112490180A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN112490180A
CN112490180A CN201910866417.9A CN201910866417A CN112490180A CN 112490180 A CN112490180 A CN 112490180A CN 201910866417 A CN201910866417 A CN 201910866417A CN 112490180 A CN112490180 A CN 112490180A
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layer
forming
initial
top surface
substrate
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张田田
张�浩
肖张茹
荆学珍
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor structure and a method of forming the same, comprising: providing a substrate, wherein the substrate is provided with a semiconductor material structure; forming a dielectric layer on the surface of the substrate, wherein the dielectric layer is internally provided with a first opening which exposes the top surface of the semiconductor material structure; forming an insulating layer on the surface of the side wall of the first opening, wherein modified ions are doped in the insulating layer; forming initial contact layers on the surface of the semiconductor material structure and the top surface of the dielectric layer; forming a protective layer on the surface of the initial contact layer; forming a conductive plug filling the first opening on the top surface of the protective layer and the surface of the side wall of the insulating layer; and annealing to react the insulating layer, the modified ions and the conductive plug and form a barrier layer on the surface of the side wall of the conductive plug. According to the technical scheme, the thickness of the formed barrier layer is reduced, the space occupied by the conductive plug and the protective layer is reduced, the contact area among the conductive plug, the protective layer and the contact layer is effectively increased, and the contact resistance is further reduced.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the continuous progress of semiconductor technology, the feature size of semiconductor devices is gradually becoming smaller. The shrinking of critical dimensions means that a greater number of transistors can be placed on a chip, while placing greater demands on the semiconductor process. As the size of semiconductor devices shrinks, the contact resistance of MOS transistors has an increasing impact on the performance of MOS transistors and the entire semiconductor chip. In order to improve the performance of the semiconductor chip, it is necessary to reduce the contact resistance of the MOS transistor
However, the semiconductor structure formed by the prior art has the problem of large contact resistance.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a semiconductor structure and a forming method thereof, which can effectively increase the contact area among a conductive plug, a protective layer and a contact layer, further reduce the contact resistance among the conductive plug, the protective layer and the contact layer, and improve the electrical property of the finally formed semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate is provided with a semiconductor material structure; forming a dielectric layer on the top surface of the substrate, wherein the dielectric layer is internally provided with a first opening which exposes the top surface of the semiconductor material structure; forming an insulating layer on the surface of the side wall of the first opening, wherein modified ions are doped in the insulating layer; forming initial contact layers on the top surface of the semiconductor material structure and the top surface of the dielectric layer; forming a protective layer on the top surface of the initial contact layer; forming a conductive plug filling the first opening on the top surface of the protective layer and the surface of the side wall of the insulating layer; and annealing to enable the initial contact layer to react with the semiconductor material structure, forming a contact layer on the top surface of the semiconductor material structure, enabling the insulating layer, the modified ions and the conductive plug to react, and forming a barrier layer on the side wall surface of the conductive plug.
Optionally, the substrate is a single-layer structure or a multi-layer structure.
Optionally, when the substrate is a single-layer structure, the method for forming the semiconductor material structure includes: forming a substrate opening in the substrate; and forming the semiconductor material structure in the substrate opening by adopting an epitaxial process.
Optionally, when the substrate is a multilayer structure, the substrate includes a base and a device layer located on a top surface of the base; the device layer includes: the device structure is positioned on the substrate, and the device dielectric layer surrounds the device structure; the device structure includes the semiconductor material structure.
Optionally, the method for forming the dielectric layer and the first opening includes: forming an initial dielectric layer on the substrate; forming a mask structure on the initial dielectric layer; forming a patterned layer on the mask structure, the patterned layer having an opening that exposes a portion of the mask structure; etching part of the mask structure and the initial dielectric layer by taking the patterning layer as a mask until the top surface of the semiconductor material structure is exposed to form the dielectric layer and the first opening; and after the dielectric layer and the first opening are formed, removing the patterning layer and the mask structure.
Optionally, the method for forming the insulating layer includes: forming initial insulating layers on the bottom surface and the side wall surface of the first opening and the top surface of the dielectric layer; doping modified ions in the initial insulating layer; and etching back the initial insulating layer on the top surface of the dielectric layer and the bottom surface of the first opening until the top surface of the dielectric layer and the top surface of the semiconductor material structure are exposed to form the insulating layer.
Optionally, the forming process of the initial insulating layer adopts an atomic layer deposition process.
Optionally, the material of the initial insulating layer includes silicon nitride, silicon oxynitride, or silicon oxycarbide.
Optionally, the modifying ions include carbon ions, silicon ions, or nitrogen ions.
Optionally, the semiconductor material structure is doped with a first type of ions.
Optionally, the process of doping the first type of ions in the semiconductor material structure is an in-situ doping process; the first type of ions are P-type ions or N-type ions.
Optionally, the forming method of the protection layer and the conductive plug includes: forming an initial protective layer on the top surface of the initial contact layer; forming an initial conductive plug on the top surface of the initial protection layer and the surface of the side wall of the insulating layer; and flattening the initial conductive plug and the initial protective layer until the top surface of the dielectric layer is exposed to form the conductive plug and the protective layer.
Optionally, a physical vapor deposition process is used for forming the initial contact layer and the initial protection layer.
Optionally, the parameters of the annealing treatment include: the annealing temperature is 600-1200 ℃, and the annealing time is 2-15 min.
Optionally, the material of the initial contact layer comprises titanium, nickel or platinum.
Optionally, the material of the initial protection layer comprises titanium nitride.
Optionally, the material of the initial conductive plug comprises tungsten, cobalt, copper or aluminum.
Accordingly, the present invention also provides a semiconductor structure formed by any of the above methods, comprising: a substrate having a semiconductor material structure therein; a dielectric layer located on the top surface of the substrate, wherein the dielectric layer has a first opening exposing the top surface of the semiconductor material structure; the insulating layer is positioned on the surface of the side wall of the first opening; the barrier layer is positioned on the surface of the side wall of the insulating layer; a contact layer located within the semiconductor material structure; a protective layer on the top surface of the contact layer; and the conductive plug is positioned on the top surface of the protective layer and the surface of the side wall of the barrier layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the technical scheme, modified ions are doped in the insulating layer, then the insulating layer, the modified ions and the conductive plug are reacted through annealing treatment, a barrier layer is formed on the surface of the side wall of the conductive plug, the barrier layer can effectively block the conductive plug, and metal diffusion of the conductive plug and metal pollution are effectively prevented; the barrier layer formed after the annealing treatment is of a single-layer structure, so that the thickness of the barrier layer is effectively reduced compared with the thickness of a double-layer barrier layer structure in the prior art, the space occupied by the conductive plug and the protective layer is further reduced, the contact area among the conductive plug, the protective layer and the contact layer is effectively increased, the contact resistance among the conductive plug, the protective layer and the contact layer is reduced, and the electrical property of the finally formed semiconductor structure is further improved.
In addition, the thickness of the barrier layer in the first opening is reduced, so that the width of the first opening is correspondingly increased, the aspect ratio of the first opening is effectively reduced under the condition that the depth of the first opening is not changed, and the conductive plug and the protective layer are easier to deposit in the first opening under the condition that the aspect ratio is smaller, so that the process difficulty is effectively reduced.
Further, in the technical scheme of the invention, the forming process of the initial contact layer and the initial protection layer adopts a physical vapor deposition process, the barrier layer is formed by reacting the insulating layer, the modified ions and the conductive plug after annealing treatment, and in order to ensure that the modified ions and the conductive plug are fully reacted, the initial protection layer does not need to be formed on the side wall of the insulating layer. The physical vapor deposition process is characterized in that materials are mainly deposited on the top surface of the object, and few materials are deposited on the side wall surface of the object, so that the process requirement can be directly realized through the physical vapor deposition process, the problem that other processes are adopted and need to be further processed is solved, and the production efficiency is effectively improved.
Drawings
FIGS. 1-6 are schematic structural diagrams of steps of a method for forming a semiconductor structure;
FIGS. 7-15 are schematic structural views of steps of a method for forming a semiconductor structure according to an embodiment of the present invention;
fig. 16 and 17 are schematic structural views of steps of a semiconductor structure forming method according to another embodiment of the present invention.
Detailed Description
As described in the background art, the semiconductor structure formed by the prior art has a problem of large contact resistance. Fig. 1 to 6 are schematic structural diagrams of steps of a method for forming a semiconductor structure, which will be described below with reference to fig. 1 to 6.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 having an epitaxial layer 101 therein; forming a dielectric layer 102 on the surface of the substrate 100, wherein a first opening 110 exposing the epitaxial layer 101 is formed in the dielectric layer 102; and forming an initial insulating layer 103 on the surface of the first opening 110 and the surface of the dielectric layer 102 by adopting an atomic layer deposition process.
Referring to fig. 2, the initial insulating layer 103 on the top surface of the epitaxial layer 101 and the top surface of the dielectric layer 102 is removed to form an insulating layer 104.
Referring to fig. 3, an initial contact layer 105 is formed on the top surface of the epitaxial layer 101; an atomic layer deposition process is used to form a first barrier layer 106 within the first opening 110.
Referring to fig. 4, an annealing process is performed on the initial contact layer 105 to form a contact layer 107.
Referring to fig. 5, an atomic layer deposition process is used to form a second barrier layer 108 on the surface of the first barrier layer 106.
Referring to fig. 6, a conductive plug 109 is formed on the surface of the second barrier layer 108.
In the above embodiment, the first barrier layer 106 functions to prevent the initial contact layer 105 from being oxidized and damaged by being exposed to air for a long time before annealing, and also functions to provide a barrier for the subsequently formed conductive plug 109, so as to prevent the metal of the conductive plug 109 from diffusing into the dielectric layer 102 and causing metal contamination. Since the first barrier layer 106 is damaged by the high temperature of the annealing process during the annealing process, and the ability of the first barrier layer 106 to block the metal diffusion of the conductive plug 109 is greatly reduced, a second barrier layer 108 needs to be deposited on the surface of the first barrier layer 106 again for the purpose of enhancing the barrier effect and preventing metal contamination. However, due to the deposition of the two barrier layers, most of the space in the first opening 110 is occupied, which results in a corresponding reduction in the contact area of the subsequently formed conductive plug 109, and thus results in a higher contact resistance of the conductive plug 109, which affects the electrical performance of the finally formed semiconductor structure.
On the basis, the invention provides a semiconductor structure and a forming method thereof, wherein modified ions are doped in an insulating layer, then the insulating layer, the modified ions and the electric conduction are reacted through annealing treatment, and a barrier layer is formed on the surface of the side wall of the conductive plug and can effectively block the conductive plug, so that the metal diffusion of the conductive plug and the metal pollution are effectively prevented; after the barrier layer is formed, the thickness of the barrier layer is effectively reduced, the space occupied by the conductive plug and the protective layer is reduced, the contact area among the conductive plug, the protective layer and the contact layer is effectively increased, the contact resistance is further reduced, and the electrical performance of the formed semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 7 to 15 are schematic structural views illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 7, a substrate 200 is provided, the substrate 200 having a semiconductor material structure 201 therein.
The substrate 200 includes a single-layer structure or a multi-layer structure, in this embodiment, the substrate 200 is a single-layer structure, and the method for forming the semiconductor material structure 201 includes: forming a substrate opening (not labeled) in the substrate 200; the semiconductor material structure 201 is formed within the substrate opening using an epitaxial process.
In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate material may be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide; in other embodiments, the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In the present embodiment, the semiconductor material structure 201 is doped with a first type of ions.
In this embodiment, the process of doping the first type of ions in the semiconductor material structure 201 is an in-situ doping process; the first type ions are P-type ions, and the P-type ions are boron ions; in other embodiments, the P-type ions may be indium ions; in other embodiments, the first type of ion may also be an N-type ion, which may be a phosphorous ion or an arsenic ion.
Referring to fig. 8, a dielectric layer 202 is formed on the top surface of the substrate 200, and the dielectric layer 202 has a first opening 203 therein to expose the top surface of the semiconductor material structure 201.
In this embodiment, the method for forming the dielectric layer 202 and the first opening 203 includes: forming an initial dielectric layer (not shown) on the substrate 200; forming a mask structure (not shown) on the initial dielectric layer; forming a patterning layer (not shown) on the mask structure, the patterning layer having an opening that exposes a portion of the mask structure; etching a part of the mask structure and the initial dielectric layer by using the patterning layer as a mask until the surface of the initial semiconductor structure is exposed to form the dielectric layer 202 and the first opening 203; after the dielectric layer 202 and the first opening 203 are formed, the patterning layer and the mask structure are removed.
The material of the initial dielectric layer comprises one or more of silicon dioxide, low-k dielectric materials (dielectric materials with a dielectric constant lower than 3.9) and ultra-low-k dielectric materials (dielectric materials with a dielectric constant lower than 2.5). When the initial dielectric layer is made of a low-k dielectric material or an ultra-low-k dielectric material, the initial dielectric layer is made of carbon silicon oxide hydride (SiCOH), fluorine-doped silicon dioxide (FSG), boron-doped silicon dioxide (BSG), phosphorus-doped silicon dioxide (PSG), boron-phosphorus-doped silicon dioxide (BPSG), hydrogen silsesquioxane or methyl silsesquioxane.
In this embodiment, the material of the initial dielectric layer is an ultra-low k dielectric material (dielectric constant less than 2.5), and the ultra-low k dielectric material is silicon oxy-carbon hydride (SiCOH).
The process for forming the initial dielectric layer comprises an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process or a spin coating process; in this embodiment, the formation process of the initial dielectric layer adopts a chemical vapor deposition process.
In this embodiment, the mask structure includes a first mask layer located on the initial dielectric layer, and a second mask layer located on a surface of the first mask layer; in other embodiments, the first mask structure may also be a single-layer structure.
In this embodiment, the first mask layer is made of nitrogen-doped silicon oxycarbide; the first mask layer formed by the nitrogen-doped silicon oxycarbide has good combining capacity with the initial dielectric layer, and when the initial dielectric layer is etched by taking the etched first mask layer as a mask, the first mask layer is not easy to peel off or warp, so that the first mask layer has good capacity of keeping an etched pattern, and the accuracy of the etched pattern is effectively improved.
In this embodiment, the second mask layer is made of titanium nitride, the bonding capability between the second mask layer and the first mask layer is good, and the second mask layer can protect the surface of the first mask layer during subsequent etching of the initial dielectric layer, so that the first mask layer is not thinned; and the physical strength of the second mask layer is high, and when the initial dielectric layer is etched subsequently, the patterns of the second mask layer and the first mask layer can be kept stable, so that an opening with good appearance can be formed.
In other embodiments, the material of the second mask layer may also be silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
In this embodiment, the first mask layer and the second mask layer are formed by an atomic layer deposition process; in other embodiments, the first mask layer and the second mask layer may be formed by a chemical vapor deposition process, a physical vapor deposition process, or a spin-on process.
In this embodiment, the material of the patterning layer includes a photoresist, and the forming process of the patterning layer includes a photolithography patterning process.
The process for removing the patterned layer includes a wet stripping process or an ashing process, wherein the gas of the ashing process is an oxygen-containing gas, such as oxygen or ozone.
In this embodiment, the process for removing the mask structure is a wet etching process; in other embodiments, the process for removing the mask structure may also be a dry etching process.
In this embodiment, an insulating layer is formed on the sidewall surface of the first opening 203, and the insulating layer is doped with modified ions. Fig. 9 to 11 are specific examples of the process of forming the insulating layer.
Referring to fig. 9, an initial insulating layer 204 is formed on the bottom surface, sidewall surface and top surface of the first opening 203 and the dielectric layer 202.
In this embodiment, the forming process of the initial insulating layer 204 adopts an atomic layer deposition process, and the initial insulating layer 204 formed by the atomic layer deposition process has better uniformity, step coverage and thickness control capability.
In the present embodiment, the material of the initial insulating layer 204 is silicon nitride; in other embodiments, the material of the initial insulating layer may also be silicon oxynitride or silicon oxycarbide.
In the present embodiment, the thickness of the initial insulating layer 204 is 20 to 150 angstroms.
Referring to fig. 10, modifying ions 205 are doped into the initial insulating layer 204.
In this embodiment, the modifying ions 205 are carbon ions; in other embodiments, the modifying ions may also be silicon ions or nitrogen ions.
In this embodiment, the modified ions 205 are doped by an ion implantation process, which uses an angled implantation, and the angle of the angled implantation is determined according to the aspect ratio of the first opening 203.
Referring to fig. 11, the initial insulating layer 204 on the top surface of the dielectric layer 202 and the bottom surface of the first opening 203 is etched back until the top surface of the dielectric layer 202 and the top surface of the semiconductor material structure 201 are exposed, so as to form the insulating layer 206.
The etch-back includes dry etching or wet etching, and in this embodiment, the etch-back employs anisotropic dry etching.
Referring to fig. 12, an initial contact layer 208 is formed on the top surface of the semiconductor material structure 201 and the top surface of the dielectric layer 202.
In the present embodiment, the initial contact layer 208 is formed by a physical vapor deposition process.
In the present embodiment, the material of the initial contact layer 208 is titanium; in other embodiments, the material of the initial contact layer may also adopt nickel or platinum.
In this embodiment, a protection layer is subsequently formed on the top surface of the initial contact layer 208; a conductive plug filling the first opening 203 is formed on the top surface of the protection layer and the sidewall surface of the insulation layer 206. Please refer to fig. 13 and 14 for a specific forming process.
Referring to fig. 13, an initial protection layer 209 is formed on the top surface of the initial contact layer 208; an initial conductive plug 210 is formed on the top surface of the initial protection layer 209 and the sidewall surface of the insulating layer 206.
The initial protection layer 209 is located on the surface of the initial contact layer 208, and the function of the initial protection layer 209 is to prevent the initial contact layer 208 from being oxidized and damaged by long-term exposure to air.
In this embodiment, the material of the initial protection layer 209 is titanium nitride.
In this embodiment, the material of the initial conductive plug 210 is tungsten; in other embodiments, the material of the initial conductive plug may also be cobalt, copper or aluminum.
In the present embodiment, the formation process of the initial contact layer 208 and the initial protection layer 209 adopts a physical vapor deposition process.
Since the barrier layer to be formed subsequently is formed by reacting the insulating layer 206, the modifying ions 205 and the conductive plug after the annealing process, in order to ensure that the modifying ions 205 and the conductive plug react sufficiently, a protective layer is not required to be formed on the sidewall of the insulating layer 206. The physical vapor deposition process is a technology of gasifying solid or liquid surface of material source into gaseous atom, molecule or ion by means of physical method in vacuum condition and depositing film with certain special function on the surface of the substrate through low pressure gas (or plasma) process. The physical vapor deposition process is characterized in that the physical vapor deposition process is mainly formed on the surface of the substrate and rarely formed on the side wall of the object, so that the process requirements can be directly realized by utilizing the characteristics of the physical vapor deposition process, the problem that other processes need to be further processed is solved, and the production efficiency is effectively improved.
Referring to fig. 14, the initial conductive plug 210 and the initial passivation layer 209 are planarized until the top surface of the dielectric layer 202 is exposed, forming a conductive plug 212 and a passivation layer 211.
In the present embodiment, the process of planarizing the initial conductive plug 210 and the initial passivation layer 209 employs a chemical mechanical polishing process; in other embodiments, the planarization process may also employ an etching process.
Referring to fig. 15, an annealing process is performed to react the initial contact layer 208 with the semiconductor material structure 201, form a contact layer 213 on the top surface of the semiconductor material structure 201, and react the insulating layer 206, the modified ions 205 and the conductive plug 212 to form a barrier layer 207 on the sidewall surface of the conductive plug 212.
In this embodiment, the parameters of the annealing process include: the annealing temperature is 600-1200 ℃, and the annealing time is 2-15 min
In this embodiment, the material of the barrier layer 207 formed by the reaction after the annealing treatment is one or more of tungsten carbonitride (WCN), tungsten carbide (WC), and tungsten nitride (WN). The barrier layer 207 formed by these materials has good compactness and adhesion, can effectively prevent the metal diffusion of the conductive plug 212, and has a high barrier effect.
With reference to fig. 15, the present invention further provides a semiconductor structure formed by the above method, including: a substrate 200, the substrate 200 having a semiconductor material structure 201 therein; a dielectric layer 202 located on the top surface of the substrate 200, wherein the dielectric layer 202 has a first opening therein to expose the surface of the top 201 of the semiconductor material structure; an insulating layer 206 on a sidewall surface of the first opening; a barrier layer 207 on the sidewall surface of the insulating layer 206; a contact layer 213 located on a top surface of the semiconductor material structure 201; a protective layer 211 on the top surface of the contact layer 213; and a conductive plug 212 located on the top surface of the protection layer 211 and the sidewall surface of the barrier layer 207.
Fig. 16 and 17 are schematic structural views of steps of a semiconductor structure forming method according to another embodiment of the present invention.
Referring to fig. 16, a substrate 300 is provided, the substrate 300 having a semiconductor material structure 301 therein.
In this embodiment, the substrate 300 is a multi-layer structure, the substrate 300 includes a base 302 and a device layer 303 located on a top surface of the base 302, and the device layer 303 includes: a device structure on the substrate 302 and a device dielectric layer (not labeled) surrounding the device structure, the device structure including the semiconductor material structure 301.
The material of the semiconductor material structure 301 comprises silicon, germanium, silicon germanium or silicon carbide.
In this embodiment, the device structure is a gate structure, and the semiconductor material structure 302 is the device structure. In other embodiments, the device structure may also be one or more of a resistive structure, a capacitive structure, an inductive structure, and a storage gate structure.
Referring to fig. 17, a dielectric layer 304 is formed on the top surface of the substrate 300, and the dielectric layer 304 has a first opening (not labeled) therein to expose the top surface of the semiconductor material structure 301.
In this embodiment, the dielectric layer 304 is formed on the surfaces of the device dielectric layer and the semiconductor material structure 301.
With reference to fig. 17, an insulating layer 305 is formed on the sidewall surface of the first opening, and the insulating layer 305 is doped with modified ions; forming an initial contact layer on the top surface of the semiconductor material structure 301 and the top surface of the dielectric layer 304; forming a protective layer 308 on the top surface of the initial contact layer; forming a conductive plug 307 filling the first opening on the top surface of the protection layer 308 and the sidewall surface of the insulation layer 305; and annealing to enable the initial contact layer to react with the semiconductor material structure 301, forming a contact layer 309 on the top surface of the semiconductor material structure 301, and enabling the insulating layer 305, the modified ions and the conductive plug 307 to react, so as to form a barrier layer 306 on the side wall surface of the conductive plug 307.
The formation processes of the insulating layer 305, the protection layer 308, the conductive plug 307 and the contact layer 309 can refer to fig. 9 to fig. 15 and the related description, which are not repeated herein.
Correspondingly, the embodiment of the invention also provides the semiconductor structure shown in fig. 17.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (18)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a semiconductor material structure;
forming a dielectric layer on the top surface of the substrate, wherein the dielectric layer is internally provided with a first opening which exposes the top surface of the semiconductor material structure;
forming an insulating layer on the surface of the side wall of the first opening, wherein modified ions are doped in the insulating layer;
forming initial contact layers on the top surface of the semiconductor material structure and the top surface of the dielectric layer;
forming a protective layer on the top surface of the initial contact layer;
forming a conductive plug filling the first opening on the top surface of the protective layer and the surface of the side wall of the insulating layer;
and annealing to enable the initial contact layer to react with the semiconductor material structure, forming a contact layer on the top surface of the semiconductor material structure, enabling the insulating layer, the modified ions and the conductive plug to react, and forming a barrier layer on the side wall surface of the conductive plug.
2. The method of forming a semiconductor structure of claim 1, wherein the substrate is a single layer structure or a multi-layer structure.
3. The method of forming a semiconductor structure of claim 2, wherein when the substrate is a single layer structure, the method of forming a semiconductor material structure comprises: forming a substrate opening in the substrate; and forming the semiconductor material structure in the substrate opening by adopting an epitaxial process.
4. The method of forming a semiconductor structure of claim 2, wherein when the substrate is a multilayer structure, the substrate comprises a base and a device layer on a top surface of the base; the device layer includes: the device structure is positioned on the substrate, and the device dielectric layer surrounds the device structure; the device structure includes the semiconductor material structure.
5. The method of forming a semiconductor structure of claim 1, wherein the method of forming the dielectric layer and the first opening comprises: forming an initial dielectric layer on the substrate; forming a mask structure on the initial dielectric layer; forming a patterned layer on the mask structure, the patterned layer having an opening that exposes a portion of the mask structure; etching part of the mask structure and the initial dielectric layer by taking the patterning layer as a mask until the top surface of the semiconductor material structure is exposed to form the dielectric layer and the first opening; and after the dielectric layer and the first opening are formed, removing the patterning layer and the mask structure.
6. The method of forming a semiconductor structure of claim 1, wherein the method of forming the insulating layer comprises: forming initial insulating layers on the bottom surface and the side wall surface of the first opening and the top surface of the dielectric layer; doping modified ions in the initial insulating layer; and etching back the initial insulating layer on the top surface of the dielectric layer and the bottom surface of the first opening until the top surface of the dielectric layer and the top surface of the semiconductor material structure are exposed to form the insulating layer.
7. The method of forming a semiconductor structure of claim 6, wherein the initial insulating layer is formed using an atomic layer deposition process.
8. The method of forming a semiconductor structure of claim 6, wherein a material of the initial insulating layer comprises silicon nitride, silicon oxynitride, or silicon oxycarbide.
9. The method of claim 6, wherein the modifying ions comprise carbon ions, silicon ions, or nitrogen ions.
10. The method of claim 3, wherein the semiconductor material structure is doped with a first type of ion.
11. The method of claim 10, wherein the process of doping the first type of ions in the semiconductor material structure is an in-situ doping process; the first type of ions are P-type ions or N-type ions.
12. The method of forming a semiconductor structure of claim 1, wherein the method of forming the passivation layer and the conductive plug comprises: forming an initial protective layer on the top surface of the initial contact layer; forming an initial conductive plug on the top surface of the initial protection layer and the surface of the side wall of the insulating layer; and flattening the initial conductive plug and the initial protective layer until the top surface of the dielectric layer is exposed to form the conductive plug and the protective layer.
13. The method of claim 12, wherein the initial contact layer and the initial protection layer are formed by a physical vapor deposition process.
14. The method of forming a semiconductor structure of claim 1, wherein the parameters of the annealing process comprise: the annealing temperature is 600-1200 ℃, and the annealing time is 2-15 min.
15. The method of forming a semiconductor structure of claim 1, wherein a material of the initial contact layer comprises titanium, nickel, or platinum.
16. The method of forming a semiconductor structure of claim 12, wherein a material of the initial protective layer comprises titanium nitride.
17. The method of forming a semiconductor structure of claim 12 wherein a material of said initial conductive plug comprises tungsten, cobalt, copper or aluminum.
18. A semiconductor structure formed by the method of any of claims 1 to 17, comprising:
a substrate having a semiconductor material structure therein;
a dielectric layer located on the top surface of the substrate, wherein the dielectric layer has a first opening exposing the top surface of the semiconductor material structure;
the insulating layer is positioned on the surface of the side wall of the first opening;
the barrier layer is positioned on the surface of the side wall of the insulating layer;
a contact layer located within the semiconductor material structure;
a protective layer on the top surface of the contact layer;
and the conductive plug is positioned on the top surface of the protective layer and the surface of the side wall of the barrier layer.
CN201910866417.9A 2019-09-12 2019-09-12 Semiconductor structure and forming method thereof Pending CN112490180A (en)

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