CN112489922A - Inductance device - Google Patents
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- CN112489922A CN112489922A CN202010825100.3A CN202010825100A CN112489922A CN 112489922 A CN112489922 A CN 112489922A CN 202010825100 A CN202010825100 A CN 202010825100A CN 112489922 A CN112489922 A CN 112489922A
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Abstract
An inductance device comprises a first wire, a second wire, a third wire, a fourth wire, a first capacitor and a second capacitor. The first wire includes at least two sub-wires, and one end of the at least two sub-wires is coupled to the first node. The second trace comprises at least two sub-traces, and one end of each of the at least two sub-traces is coupled to the second node. One end of the third wire is coupled to the second wire, and the other end of the third wire is coupled to the first input/output end. One end of the fourth wire is coupled to the first wire, and the other end of the fourth wire is coupled to the second input/output end. The first capacitor is coupled between the first node and the second node. The second capacitor is coupled between the first node and the first input/output end, or between the first node and the second input/output end, or between the first input/output end and the second input/output end.
Description
Technical Field
The present disclosure relates to electronic devices, and more particularly, to an inductive device.
Background
Radio Frequency (RF) devices generate harmonic doublets (harmonic), harmonic triplets …, etc. when operating, which may adversely affect other circuits. For example, the double frequency harmonics of a 2.4GHz circuit can produce a 5GHz signal that can adversely affect an integrated circuit (SOC).
The common solution to the above-mentioned harmonic influences on the circuit is to arrange a filter outside the circuit to sense the high frequency signals of the adjacent elements and to design and select the desired frequency and the frequency that does not need to be filtered. However, the filter disposed outside the circuit may affect the performance of the circuit itself and additional cost, such as: the cost of installing a Printed Circuit Board (PCB).
Disclosure of Invention
One technical implementation of the present disclosure relates to an inductance device, which includes a first trace, a second trace, a third trace, a fourth trace, a first capacitor, and a second capacitor. The first wire includes at least two sub-wires, and one end of the at least two sub-wires is coupled to the first node. The second trace comprises at least two sub-traces, and one end of each of the at least two sub-traces is coupled to the second node. The third wire and the first wire are arranged on the first side, one end of the third wire is coupled to one of the at least two sub-wires of the second wire, and the other end of the third wire is coupled to the first input/output end. The fourth trace and the second trace are disposed on the second side, one end of the fourth trace is coupled to one of the at least two sub-traces of the first trace, and the other end of the fourth trace is coupled to the second input/output end. The first capacitor is coupled between the first node and the second node. The second capacitor is coupled between the first node and the first input/output end, or between the first node and the second input/output end, or between the first input/output end and the second input/output end.
Therefore, according to the technical content of the present disclosure, the capacitor in the inductance device shown in the embodiment of the present disclosure may form a low frequency blocking function, so that the low frequency signal induced by the inductance device cannot pass through but the high frequency signal can pass through directly. For example, a low frequency signal, such as 2.4GHz main operating frequency, cancels an induced signal of the main operating frequency through a meandering inductor structure (folded inductor) of the inductor device, so the meandering inductor structure does not affect the characteristics of the inductor operating frequency, and the induced signal on the meandering two lines is cancelled by inversion, and if the central inductor structure has a high frequency signal, such as 2 times harmonic 5GHz, because the high frequency signal capacitor is on, the high frequency signal forms an induced inductor surrounding a circle through the capacitor by the meandering inductor structure, and then a corresponding 5GHz harmonic signal more than ten times of 2.4GHz is induced in the inductor structure of the present disclosure. The user then applies the 5GHz signal to the circuit, for example, amplifies the signal and then cancels the 5GHz harmonic of the operating frequency, and the application of the amplifying circuit can be optimized by the well-known circuit designer. Thus, the adverse effect on the 5GHz circuit can be reduced.
Furthermore, since the filter is disposed in the inductive device, the filter does not need to be disposed outside the inductive device, thereby preventing the external filter from affecting the performance of the circuit itself or increasing extra cost. In addition, the capacitor in the inductance device of the embodiment of the disclosure can form a low-frequency filtering function (for example, filtering second-order harmonics), and can guide and filter higher-frequency signals (for example, fourth-order harmonics) in a short circuit manner through the configuration among a plurality of capacitors, so as to avoid adverse effects of fourth-order harmonics of the original circuit.
Drawings
In order to make the aforementioned and other objects, features, advantages and embodiments of the disclosure more comprehensible, the following description is given:
fig. 1 is a schematic diagram illustrating an inductive device, according to an embodiment of the present disclosure.
Fig. 2 is a schematic diagram illustrating an inductive device, according to an embodiment of the present disclosure.
Fig. 3 is a schematic diagram illustrating an inductive device, according to an embodiment of the present disclosure.
Fig. 4 is a schematic diagram illustrating an inductive device, according to an embodiment of the present disclosure.
Fig. 5 is a schematic diagram illustrating an inductive device, according to an embodiment of the present disclosure.
Fig. 6 is a schematic diagram illustrating an inductive device, according to an embodiment of the present disclosure.
Fig. 7 is a schematic diagram illustrating experimental data for an inductive device, according to an embodiment of the present disclosure.
In accordance with conventional practice, the various features and elements of the drawings are not drawn to scale in order to best illustrate the specific features and elements associated with the present disclosure. Moreover, the same or similar reference numbers are used throughout the different drawings to reference like elements/components.
Description of the symbols
1000. 1000A to 1000D: inductance device
1100. 1100A-1100C: first wire
1110. 1110A to 1110C: first sub-routing
1120. 1120A to 1120C: second sub-routing
1200. 1200A to 1200C: second routing
1210. 1210A-1210C: third sub-routing
1220. 1220A to 1220C: fourth sub-routing
1300. 1300A to 1300C: third routing
1310. 1310A-1310C: fifth sub-routing
1320. 1320A to 1320C: sixth sub-wiring
1400. 1400A-1400C: fourth wire
1410. 1410A to 1410C: seventh sub-routing
1420. 1420A to 1420C: eighth sub-routing
1500. 1500A-1500C: central tap end
5000C, 5000D: inductance
C1, C2, C3: capacitor with a capacitor element
E1, E2: curve line
IO1, IO 2: input/output terminal
N1: first node
N2: second node
Detailed Description
Fig. 1 is a schematic diagram illustrating an inductive device 1000 according to an embodiment of the disclosure. To facilitate understanding of the inductance device 1000 in fig. 1, the structural design diagram of the inductance device 1000 in fig. 1 is simplified to a schematic diagram of the inductance device 1000 in fig. 2.
Referring to fig. 1 and fig. 2, the inductive device 1000 includes a first trace 1100, a second trace 1200, a third trace 1300, a fourth trace 1400, a first capacitor C1, and a second capacitor C2. Furthermore, the first trace 1100 includes at least two sub-traces 1110 and 1120. The second trace 1200 includes at least two sub-traces 1210, 1220.
In one embodiment, one end (e.g., the lower end) of at least two sub-traces 1110 and 1120 is coupled to the first node N1. One end (e.g., the lower end) of the at least two sub-traces 1210, 1220 is coupled to the second node N2. The first capacitor C is coupled between the first node N1 and the second node N2.
In addition, the first trace 1100 and the third trace 1300 are disposed on the first side of the inductive device 1000. For example, the first trace 1100 and the third trace 1300 are disposed on the left side of the inductive device 1000, and the third trace 1300 is disposed on the outer side of the first trace 1100. One end of the third trace 1300 is coupled to one of the at least two sub-traces 1210 and 1220 of the second trace 1200, and the other end of the third trace 1300 is coupled to the first input/output port IO 1.
In addition, the second trace 1200 and the fourth trace 1400 are disposed on the second side of the inductive device 1000. For example, the second trace 1200 and the fourth trace 1400 are disposed on the right side of the inductive device 1000, and the fourth trace 1400 is disposed on the outer side of the second trace 1200. In addition, one end of the fourth trace 1400 is coupled to one of the at least two sub-traces 1110 and 1120 of the first trace 1100, and the other end of the fourth trace 1400 is coupled to the second input/output port IO 2. In an embodiment, the first side and the second side are located at two opposite sides of the inductive device 1000.
Furthermore, the first capacitor C1 is coupled between the first node N1 and the second node N2. The second capacitor C2 is coupled between the first node N1 and the first input/output terminal IO 1. Thus, when a low frequency signal is to be transmitted from the first node N1 to the second node N2, the low frequency signal is blocked by the first capacitor C1, for example, a 2.4GHz signal is blocked by the first capacitor C1. In addition, when a high frequency signal is to be transmitted from the first node N1 to the second node N2, the high frequency signal can be transmitted through the first capacitor C1, for example, a 5GHz signal can be transmitted from the first node N1 to the second node N2 through the first capacitor C1. Furthermore, if a higher frequency signal is to be transmitted from the first node N1 to the second node N2, the higher frequency signal is guided to the first input/output terminal IO1 through the second capacitor C2 and filtered, for example, a 10GHz signal is guided by the second capacitor C2 and filtered.
In an embodiment, each of the at least two sub-traces 1110, 1120 of the first trace 1100 includes a U-shaped sub-trace. For example, the sub-traces 1110 and 1120 are both U-shaped sub-traces. In addition, each of the at least two sub-traces 1210, 1220 of the second trace 1200 also includes a U-shaped sub-trace. For example, the sub-traces 1210 and 1220 are U-shaped sub-traces. In addition, the third trace 1300 includes a U-shaped trace, and the fourth trace 1400 includes a U-shaped trace. However, the present disclosure is not limited to the embodiment of fig. 2, and in other embodiments, the traces and sub-traces may have other suitable shapes according to actual requirements.
In another embodiment, the first trace 1100, the second trace 1200, the third trace 1300 and the fourth trace 1400 are cross-coupled (cross) on a third side (e.g., an upper side). In one embodiment, the first capacitor C1 and the second capacitor C2 are located on the fourth side (e.g., the lower side). The third side and the fourth side are located on two opposite sides of the inductive device 1000.
In one embodiment, as shown in fig. 1 and 2, the inductive device 1000 further includes a third capacitor C3. The third capacitor C3 is coupled between the second node N2 and the second input/output terminal IO 2. Therefore, when the low frequency signal is going to be transmitted from the second node N2 to the first node N1, the low frequency signal is blocked by the first capacitor C1. When a high frequency signal is to be transmitted from the second node N2 to the first node N1, the high frequency signal can be transmitted through the first capacitor C1. Furthermore, if a higher frequency signal is to be transmitted from the second node N2 to the first node N1, the higher frequency signal is guided to the second input/output port IO2 through the third capacitor C3 and filtered, for example, a 10GHz signal is guided by the third capacitor C3 and filtered.
Referring to fig. 1 and fig. 2, the first trace 1100 includes a first sub-trace 1110 and a second sub-trace 1120. Furthermore, the first sub-trace 1110 and the second sub-trace 1120 both include a first end and a second end. As shown, the second end (e.g., lower end) of the first sub-trace 1110 is coupled to the second end (e.g., lower end) of the second sub-trace 1120.
In addition, the second trace 1200 includes a third sub-trace 1210 and a fourth sub-trace 1220. Furthermore, the third sub-trace 1210 and the fourth sub-trace 1220 each include a first end and a second end. As shown, a second end (e.g., a lower end) of the third sub-trace 1210 is coupled to a second end (e.g., a lower end) of the fourth sub-trace 1220.
Referring to fig. 1 and fig. 2, the third trace 1300 includes a fifth sub-trace 1310 and a sixth sub-trace 1320. Furthermore, the fifth sub-trace 1310 and the sixth sub-trace 1320 each include a first end and a second end. As shown, a first end (e.g., upper end) of the fifth sub-trace 1310 is coupled to a first end (e.g., upper end) of the fourth sub-trace 1220. A first end (e.g., upper end) of the sixth sub-trace 1320 is coupled to a first end (e.g., upper end) of the third sub-trace 1210. In addition, a second end (e.g., a lower end) of the sixth sub-trace 1320 is coupled to the first input/output port IO 1. Furthermore, a second end (e.g., a lower end) of the sixth sub-trace 1320 is coupled to the first node N1 through a second capacitor C2. In one embodiment, the first input/output port IO1 is not coupled to the fifth sub-trace 1310.
Referring to fig. 1 and fig. 2, the fourth trace 1400 includes a seventh sub-trace 1410 and an eighth sub-trace 1420. Furthermore, the seventh sub-trace 1410 and the eighth sub-trace 1420 both include a first end and a second end. As shown, a first end (e.g., the upper end) of the seventh sub-trace 1410 is coupled to a first end (e.g., the upper end) of the second sub-trace 1120, and a second end (e.g., the lower end) of the seventh sub-trace 1410 is coupled to the second input/output port IO 2. Furthermore, a second end (e.g., a lower end) of the seventh sub-trace 1410 is coupled to the second node N2 through a third capacitor C3. A first end (e.g., upper end) of the eighth sub-trace 1420 is coupled to a first end (e.g., upper end) of the first sub-trace 1110, and a second end (e.g., lower end) of the eighth sub-trace 1420 is coupled to a second end (e.g., lower end) of the fifth sub-trace 1310. In an embodiment, the second input/output end IO2 is not coupled to the eighth sub-trace 1420.
In another embodiment, the inductive device 1000 further includes a central tap 1500. The central tap end 1500 is disposed and coupled to a junction of the third trace 1300 and the fourth trace 1400. It should be noted that the present disclosure is not limited to the structure shown in fig. 2, and is only used to illustrate one implementation manner of the present disclosure.
Fig. 3 is a schematic diagram illustrating an inductive device 1000A according to an embodiment of the disclosure. Compared to the inductive device 1000 shown in fig. 2, the inductive device 1000A in fig. 3 has a different coupling manner of the second capacitor C2 and the third capacitor C3. As shown in fig. 3, the second capacitor C2 is coupled between the first node N1 and the second input/output terminal IO2, and the third capacitor C3 is coupled between the second node N2 and the first input/output terminal IO 1. It should be noted that, in the embodiment of fig. 3, the element numbers are similar to those in fig. 2, and have similar structural features, and are not described herein again for brevity of the description. Furthermore, the present disclosure is not limited to the structure shown in fig. 3, which is merely used to exemplarily show one of the implementations of the present disclosure.
Fig. 4 is a schematic diagram illustrating an inductive device 1000B according to an embodiment of the disclosure. Compared to the inductive device 1000 shown in fig. 2, the inductive device 1000B of fig. 4 has a different coupling manner of the second capacitor C2. As shown in fig. 4, the second capacitor C2 is coupled between the first input/output end IO1 and the second input/output end IO 2. It should be noted that, in the embodiment of fig. 4, the element numbers are similar to those in fig. 2, and have similar structural features, and are not described herein again for brevity of the description. Furthermore, the present disclosure is not limited to the structure shown in fig. 4, which is merely used to exemplarily show one of the implementations of the present disclosure.
Fig. 5 is a schematic diagram illustrating an inductive device 1000C according to an embodiment of the present disclosure. Compared to the inductive device 1000 shown in fig. 1, an inductor 5000C may be disposed inside the inductive device 1000C shown in fig. 5. It should be noted that, in the embodiment of fig. 5, the element numbers are similar to those in fig. 1, and have similar structural features, and are not described herein again for brevity of the description. Furthermore, the present disclosure is not limited to the embodiment of fig. 5, and in other embodiments, other types and kinds of inductive devices may be configured inside the inductive device 1000C, depending on the actual requirements. Furthermore, the present disclosure is not limited to the structure shown in fig. 5, which is merely used to exemplarily show one of the implementations of the present disclosure.
Fig. 6 is a schematic diagram illustrating an inductive device, according to an embodiment of the present disclosure. In contrast to fig. 5, in which inductor 5000C is disposed within inductor 1000C, fig. 6 illustrates inductor 1000D disposed within inductor 5000D. It should be noted that, in the embodiment of fig. 6, the element numbers are similar to those in fig. 5, and have similar structural features, and are not repeated herein for brevity of the description. Furthermore, the disclosure is not limited to the embodiment of fig. 6, and in other embodiments, other types and kinds of inductance devices, such as the inductance devices 1000 to 1000B shown in fig. 1 to 4, may be disposed inside the inductor 5000D, depending on the actual requirements. In addition, the present disclosure is not limited to the structure shown in fig. 6, which is only used to exemplarily show one of the implementations of the present disclosure.
Fig. 7 is a schematic diagram illustrating experimental data for an inductive device, according to an embodiment of the present disclosure. As shown, the experimental curves of the S parameter (scattering parameter) using the architecture of the present disclosure are E1 and E2, and the curve E1 is an experimental curve of the inductor using the same capacitance, for example, 330fF (farad) for all the capacitors of the inductor. Curve E2 is an experimental curve of capacitance for inductive devices with different capacitance values, for example, 330fF for partial capacitance and 150fF for partial capacitance. As can be seen, either curve E1 or curve E2 effectively filters out signals at 2.4GHz and allows signals at 5GHz to pass through. Furthermore, as shown, the signals above 8GHz are all decreasing no matter curve E1 or curve E2, so the architecture configuration of the present disclosure can further filter signals above 8GHz, for example, can effectively filter signals at 10 GHz.
As can be seen from the above-described embodiments of the present disclosure, the following advantages can be obtained by applying the present disclosure. The inductor device shown in the embodiments of the present disclosure can induce a high frequency signal, such as a second harmonic, of a central inductor (e.g., inductor 5000C of fig. 5), and after additional circuit amplification, the adverse effect of the second harmonic of the original circuit can be cancelled. For example, the capacitor of the inductor device is mainly used for the technical effects of passing high frequency and blocking low frequency, so that the same inductor device has two different signal induction modes relative to high frequency and low frequency.
Furthermore, since the filter is disposed in an Integrated Circuit (IC), the filter does not need to be disposed outside the inductive device, thereby preventing the external filter from affecting the performance of the circuit itself and the extra cost thereof. In addition, the capacitor in the inductance device of the embodiment of the disclosure can form a low-frequency filtering function (for example, filtering second-order harmonics), and can guide and filter higher-frequency signals (for example, fourth-order harmonics) in a short circuit manner through the configuration among a plurality of capacitors, so as to avoid adverse effects of fourth-order harmonics of the original circuit.
Claims (10)
1. An inductive device, comprising:
a first trace including at least two sub-traces, wherein one end of the at least two sub-traces is coupled to a first node;
a second trace including at least two sub-traces, wherein one end of the at least two sub-traces is coupled to a second node;
a third trace disposed on a first side of the first trace, wherein one end of the third trace is coupled to one of the at least two sub-traces of the second trace, and the other end of the third trace is coupled to a first input/output end;
a fourth trace disposed on a second side of the second trace, wherein one end of the fourth trace is coupled to one of the at least two sub-traces of the first trace, and the other end of the fourth trace is coupled to a second input/output end;
a first capacitor coupled between the first node and the second node; and
and the second capacitor is coupled between the first node and the first input and output end, or between the first node and the second input and output end, or between the first input and output end and the second input and output end.
2. The inductive device of claim 1, further comprising:
and a third capacitor coupled between the second node and the first input/output end or between the second node and the second input/output end, wherein the second capacitor is coupled between the first node and the first input/output end, and the third capacitor is coupled between the second node and the second input/output end.
3. The inductive device of claim 2, wherein the at least two sub-traces of the first trace include:
a first sub-trace, comprising:
a first end; and
a second end; and
a second sub-trace, comprising:
a first end; and
a second end coupled to the second end of the first sub-trace at the first node;
wherein the at least two sub-traces of the second trace include:
a third sub-trace, comprising:
a first end; and
a second end; and
a fourth sub-trace, comprising:
a first end; and
a second end coupled to the second node with the second end of the third sub-trace.
4. The inductive device of claim 3, wherein the third trace includes:
a fifth sub-trace, comprising:
a first end coupled to the first end of the fourth sub-trace; and
a second end; and
a sixth sub-trace, comprising:
a first end coupled to the first end of the third sub-trace; and
a second end coupled to the first input/output end and coupled to the first node through the second capacitor;
wherein the at least two sub-traces of the fourth trace comprise:
a seventh sub-trace, comprising:
a first end coupled to the first end of the second sub-trace; and
a second end coupled to the second input/output end and coupled to the second node through the third capacitor; and
an eighth sub-trace, comprising:
a first end coupled to the first end of the first sub-trace; and
a second end coupled to the second end of the five sub-traces.
5. The inductive device of claim 1, further comprising:
and a third capacitor coupled between the second node and the first input/output end or between the second node and the second input/output end, wherein the second capacitor is coupled between the first node and the second input/output end, and the third capacitor is coupled between the second node and the first input/output end.
6. The inductive device of claim 5, wherein the at least two sub-traces of the first trace include:
a first sub-trace, comprising:
a first end; and
a second end; and
a second sub-trace, comprising:
a first end; and
a second end coupled to the second end of the first sub-trace at the first node;
wherein the at least two sub-traces of the second trace include:
a third sub-trace, comprising:
a first end; and
a second end; and
a fourth sub-trace, comprising:
a first end; and
a second end coupled to the second node with the second end of the third sub-trace.
7. The inductive device of claim 6, wherein the third trace includes:
a fifth sub-trace, comprising:
a first end coupled to the first end of the fourth sub-trace; and
a second end; and
a sixth sub-trace, comprising:
a first end coupled to the first end of the third sub-trace; and
a second terminal coupled to the first input/output terminal and coupled to the second node through the third capacitor;
wherein the at least two sub-traces of the fourth trace comprise:
a seventh sub-trace, comprising:
a first end coupled to the first end of the second sub-trace; and
a second end coupled to the second input/output end and coupled to the first node through the second capacitor; and
an eighth sub-trace, comprising:
a first end coupled to the first end of the first sub-trace; and
a second end coupled to the second end of the five sub-traces.
8. The inductive device of claim 1, wherein each of the at least two sub-traces of the first trace comprises a U-shaped sub-trace, wherein each of the at least two sub-traces of the second trace comprises a U-shaped sub-trace, wherein the third trace comprises a U-shaped trace, and wherein the fourth trace comprises a U-shaped trace.
9. The inductive device of claim 1, wherein the third trace is disposed outside the first trace, wherein the fourth trace is disposed outside the second trace, and wherein the first side and the second side are located on opposite sides of the inductive device.
10. The inductive device of claim 1, wherein the first trace, the second trace, the third trace, and the fourth trace are cross-coupled at a third side, wherein the first capacitor and the second capacitor are located at a fourth side, and wherein the third side and the fourth side are located at two opposite sides of the inductive device.
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| Application Number | Priority Date | Filing Date | Title |
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| US201962898618P | 2019-09-11 | 2019-09-11 | |
| US62/898,618 | 2019-09-11 | ||
| US201962904750P | 2019-09-24 | 2019-09-24 | |
| US62/904,750 | 2019-09-24 |
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| CN112489922A true CN112489922A (en) | 2021-03-12 |
| CN112489922B CN112489922B (en) | 2022-04-29 |
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| CN202010825100.3A Active CN112489922B (en) | 2019-09-11 | 2020-08-17 | Inductance device |
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| US11901399B2 (en) | 2019-09-11 | 2024-02-13 | Realtek Semiconductor Corporation | Enhanced sensing coil for semiconductor device |
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Also Published As
| Publication number | Publication date |
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| TWI722946B (en) | 2021-03-21 |
| TW202111740A (en) | 2021-03-16 |
| CN112489922B (en) | 2022-04-29 |
| TW202111737A (en) | 2021-03-16 |
| CN112490360A (en) | 2021-03-12 |
| TWI715513B (en) | 2021-01-01 |
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