CN112489709A - Two-step writing operation method of resistive random access memory array - Google Patents
Two-step writing operation method of resistive random access memory array Download PDFInfo
- Publication number
- CN112489709A CN112489709A CN202011506701.4A CN202011506701A CN112489709A CN 112489709 A CN112489709 A CN 112489709A CN 202011506701 A CN202011506701 A CN 202011506701A CN 112489709 A CN112489709 A CN 112489709A
- Authority
- CN
- China
- Prior art keywords
- random access
- access memory
- resistive random
- gate
- resistance state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0071—Write using write potential applied to access device gate
Landscapes
- Semiconductor Memories (AREA)
- Static Random-Access Memory (AREA)
Abstract
The invention provides a two-step writing operation method of a resistive random access memory array, which comprises the following steps: enabling initial states of a gate and a resistive random access memory in a resistive random access memory array to be in a high-resistance state; applying a first write pulse signal to the resistive random access memory array to enable the gate to be in a low-resistance state and the resistive random access memory to be in a high-resistance state; applying a second write pulse signal to the resistive random access memory array to enable the gate and the resistive random access memory to be in a low-resistance state; reducing the amplitude of the second write pulse signal to zero, enabling the gate to be in a high-resistance state, enabling the resistive random access memory to be in a low-resistance state, and completing the write operation; the amplitude of the second write pulse signal is larger than the write operation voltage of the resistive random access memory, the amplitude of the first write pulse signal is larger than the forward starting threshold voltage of the gate, the pulse length of the first write pulse signal is larger than the forward starting delay of the gate, and the pulse length of the second write pulse signal is larger than the write delay of the resistive random access memory. The invention can reduce the influence of the writing operation process on the performance of the gating device and reduce the power consumption and the crosstalk of the resistance change device in the writing process.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a two-step writing operation method of a resistive random access memory array.
Background
The Resistive Random Access Memory (RRAM) has the advantages of small area, low power consumption, high speed, simple structure, multi-value storage, compatibility with a CMOS (complementary metal oxide semiconductor) process and the like, so that the RRAM has wide application prospect in the fields of high-density storage technology, large-scale neural network computing systems, wearable electronics, Internet of things and the like. In order to improve the storage density, in practical application, the resistive random access memory array architecture generally adopts a cross array structure: each memory cell is defined by upper and lower electrodes formed of Word Lines (WL) and Bit Lines (BL) crossing each other. However, parasitic leakage current may exist during the operation of the cross array structure, which causes problems of read crosstalk, etc., which greatly limits the size of the array and increases the system power consumption. In order to suppress leakage current and reduce crosstalk, a device (Selector) with a gating function is generally connected in series with a resistive memory device to form a gate-one-resistor (1S 1R) cross structure array, as shown in fig. 1.
Among many gates, the threshold switch gate has a large switching ratio, can effectively suppress leakage current in a cross array, has a low operating voltage and a simple structure, and is convenient to integrate with a resistive random access memory to form a 1S1R structure, thereby gaining wide attention. The threshold switch gate is initially high-impedance, and when the voltage applied between the upper and lower electrodes of the device is greater than the threshold voltage V of the devicethWhen the device is started, a conductive filament is formed in the gate, the resistance value is changed into low resistance, and the device is conducted; when the voltage applied between the gate electrodes of the threshold switch is less than the holding voltage V of the deviceholdWhen the device is turned off, the conductive filament inside the gate is spontaneously broken, the device is changed back to a high-resistance state, and the I-V curve of the device is shown in figure 2.
At present, the method for implementing the write operation of the resistive random access memory array generally sets the resistive random access memory device to the target resistance state by using a plurality of continuous pulses. Referring to fig. 1, when a write operation is performed on a certain resistance change cell, a write pulse signal V is applied to a row where the cell is locatedSThe column in which the cell is located is grounded. Other rows and columns are connected with V according to different voltage schemesWAnd VB. Take the writing process as an example, the concrete operationThe working process is as follows: the initial state gate and the resistance change device are in high resistance state, and the resistance values are R respectivelyshAnd RhAnd has RSh＞＞Rh(ii) a When the device is in the row, a write pulse V is appliedS(VS＞Vth) When due to RSh＞＞RhThe voltage is mainly applied to the gate so that the gate voltage division is greater than the threshold voltage VthThe gate changes to a low resistance state RslThe gate is started; due to Rsl＜RhAfter the gate is started, the partial pressure of the resistive random access memory is increased, and when the partial pressure is larger than the writing voltage V of the resistive random access memorysetWhen the resistance random access memory is set to be in a low resistance state RlAnd the write operation is complete. Referring to FIG. 3, there is a delay t in the gating process of 1S1R arraydIn order to ensure that the resistive random access memory can be effectively written in, the pulse width PW is adopted in the writing processwrThe length should be extended accordingly; however continuously large amplitude (V)wr>Vset>Vth) Long Pulse Width (PW)wr>td) The application of the pulse may cause the fatigue characteristic (endplay) of the gating device to be reduced, and even cause the device to fail; the increase of the pulse amplitude and width in the writing process can also increase the power consumption in the writing process, and aggravate the crosstalk between the devices, so that the devices are operated by mistake (set-disturb).
Therefore, a new operation method is needed to improve these problems and increase the writing efficiency of the 1S1R array.
Disclosure of Invention
The invention aims to avoid the failure of a gate caused by the writing operation process of the 1S1R array and reduce the power consumption and crosstalk in the writing process, and provides a two-step writing operation method of a resistive random access memory array.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention provides a two-step writing operation method of a resistive random access memory array, which is characterized by comprising the following steps of:
enabling initial states of a gate and a resistive random access memory in a resistive random access memory array to be in a high-resistance state;
applying a first write pulse signal to the resistive random access memory array to enable the gate to be in a low-resistance state and the resistive random access memory to be in a high-resistance state;
applying a second write pulse signal to the resistive random access memory array to enable the gate to keep a low-resistance state and the resistive random access memory to be in the low-resistance state;
reducing the amplitude of the second write pulse signal to zero, enabling the gate to be in a high-resistance state, enabling the resistive random access memory to be in a low-resistance state, and completing the write operation;
wherein the amplitude V of the first write pulse signal1Sum pulse length PW1The voltage and pulse length required for opening the gate in the forward direction, and the amplitude V of the second write pulse signal2Sum pulse length PW2The voltage and the pulse length required by the writing operation of the resistive random access memory are respectively, and all the parameters simultaneously meet the following requirements: (a) v2>Vset>V1>Vth，(b)PW1>td，(c)PW2>tset；VsetAnd VthThe minimum voltage at which the resistive random access memory can be written and the threshold voltage t at which the gate is turned on in the forward directiondAnd tsetRespectively a forward opening delay of the gate and a writing delay of the resistance random access memory.
Further, the method also comprises the following steps:
applying a first reset pulse signal to the resistive random access memory array to enable the gate to be in a low-resistance state and the resistive random access memory to be in the low-resistance state;
applying a second reset pulse signal to the resistive random access memory array to enable the gate to keep a low-resistance state and the resistive random access memory to be in a high-resistance state;
reducing the amplitude of the second reset pulse signal to zero, enabling the gate and the resistive random access memory to be in a high-resistance state, and finishing the reset operation;
wherein an amplitude-V of the first reset pulse signal1Sum pulse length PWn1Voltage and pulse length required for reversely turning on the gate, amplitude-V of the second reset pulse signal2Sum pulse length PWn2The voltage and the pulse length required by the reset operation of the resistive random access memory are respectively needed, and all the parameters simultaneously meet the following requirements: (e) -V2<Vreset<-V1<-Vth，(d)PWn1>tnd，(f)PWn2>treset；Vresetand-VthIs the minimum voltage at which the resistive random access memory can be reset and the threshold voltage at which the gate is turned on in reverse, tndAnd tresetRespectively a gate reverse turn-on delay and a resistive random access memory reset delay.
The invention has the characteristics and beneficial effects that:
(1) according to the two-step writing operation method of the resistive random access memory array, in the starting process of the first-step writing operation gate, the starting voltage amplitude and the pulse width of the gate are limited, the gate is prevented from being broken down under high voltage, the service life of the gate is prolonged, and the array is ensured to normally work;
(2) the invention carries out writing operation in two steps, reduces the large voltage pulse time in the writing process and reduces the power consumption in the writing process;
(3) the invention adjusts the pulse length PW of the second step of writing operation2And crosstalk brought to unselected resistive random access devices in the writing process is reduced by using the starting delay of the gating device.
In summary, the invention realizes the segmented operation of the gate and the resistive switching device by adjusting the voltage amplitude and the pulse width of the write pulse in different steps, reduces the influence of the write operation process on the performance of the gate, and reduces the power consumption in the write process and the crosstalk of the resistive switching device.
Drawings
Fig. 1 is a schematic structural diagram of a conventional 1S1R crossbar array.
Fig. 2 is an I-V plot of a prior art threshold switching gate.
Fig. 3 is a delay profile of the turn-on process of the gating devices in the 1S1R crossbar array shown in fig. 1.
Fig. 4 is a flowchart of a two-step writing operation method of a resistive random access memory array according to the present invention.
Fig. 5 is a pulse waveform diagram of a two-step write operation (set) of a resistive random access memory array according to the present invention.
Fig. 6 is a waveform diagram of a two-step reset operation (reset) pulse of a resistive random access memory array according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the detailed description and specific examples, while indicating the scope of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.
For better understanding of the present invention, an application example of a two-step write operation method of a resistive random access memory array proposed by the present invention is explained in detail below.
The invention provides a two-step writing operation method of a resistive random access memory array, which realizes the segmented operation of a gate and a resistive random access device by adjusting the voltage amplitude and the pulse width of a writing pulse and reduces the influence of the writing operation process on the performance of the gate.
Referring to fig. 1, the resistive random access memory array structure applicable to the present invention includes n word lines (WL 1-WLn) and n bit lines (BL 1-BLn) arranged in a crossing manner, and a memory cell is disposed at each crossing point of the bit lines and the word lines, and the memory cell includes a switching element (in this embodiment, a gate Selector) and a resistive random access element (in this embodiment, a resistive random access memory RRAM) connected to each other. The two-step write operation method of the present invention comprises the steps of:
enabling initial states of a gate and a resistive random access memory in a resistive random access memory array to be in a high-resistance state;
applying a first write pulse signal to the resistive random access memory array to enable the gate to be in a low-resistance state and the resistive random access memory to be in a high-resistance state;
applying a second write pulse signal to the resistive random access memory array to enable the gate to keep a low-resistance state and the resistive random access memory to be in the low-resistance state;
reducing the amplitude of the second write pulse signal to zero, enabling the gate to be in a high-resistance state, enabling the resistive random access memory to be in a low-resistance state, and completing the write operation;
wherein the first pulseAmplitude V of the impulse signal1Sum pulse length PW1The amplitude V of the second write pulse signal is the voltage and pulse length required for turning on the gate in the forward direction2Sum pulse length PW2The voltage and the pulse length required by the writing operation of the resistive random access memory are respectively, and all the parameters simultaneously meet the following requirements: (a) v2>Vset>V1>Vth，(b)PW1>td，(c)PW2>tset；VsetAnd VthRespectively, a write voltage of the resistive random access memory (i.e., a minimum voltage at which the resistive random access memory can be set-operated) and a threshold voltage at which the gate is turned on in a forward direction, tdAnd tsetRespectively a gate forward turn-on delay and a resistive random access memory write delay (i.e., a minimum pulse length required for the resistive random access memory to be set-operated).
Specifically, when a write operation is performed on the 1S1R array, the operation method is as shown in fig. 4, and includes the following steps:
(1) the initial states of a gate and a resistive random access memory in the resistive random access memory array are both in a high-resistance state and are recorded as a state 0, and the resistance values of the gate and the resistive random access memory are respectively RshAnd RhAnd has RSh＞＞Rh；
(2) The first step of writing operation, the positive opening process of the gating device: applying a first write pulse signal to the resistive random access memory array to enable the gate to be in a low-resistance state and the resistive random access memory to be in a high-resistance state; amplitude V of the first write pulse signal1Sum pulse length PW1The voltage and the pulse length required by the gate are respectively positively started, and the following conditions are met: vset>V1>VthAnd PW1>tdWhen the voltage is mainly applied to the gate, the gate is turned on in the forward direction and is recorded as the state 1, and the resistance of the gate is changed into the low resistance Rsl(ii) a The resistive random access memory is still in a high-resistance state, namely still in a state of '0', and the write (set) pulse waveform of the invention is shown in figure 5;
(3) the second step of writing operation, the writing process of the resistive random access memory: applying a second write pulse signal to the resistive random access memory array to enable the gate to keep a low-resistance state and the resistive random access memory to be in a low-resistance state(ii) a Amplitude V of the second write pulse signal2Sum pulse length PW2The voltage and the pulse length required by the writing operation of the resistive random access memory are respectively satisfied: v2>Vset，PW2>tsetAnd R ish>RslWhen the voltage is mainly applied to the resistive random access memory, the resistance value of the resistive random access memory is set to be low resistance RlAnd is marked as state "1"; the gate remains in the low resistance state, i.e., remains in the state "1";
(4) and reducing the amplitude of the second write pulse signal to zero, turning off the gate, recording as the state of 0, and finishing the write operation.
The invention also includes resetting the 1S1R array after completing the write operation, which includes the following steps:
(5) the first step of reset operation, the gating reverse opening process: applying a first reset pulse signal to the resistive random access memory array to enable the gate to be in a low-resistance state and the resistive random access memory to be in the low-resistance state; amplitude-V of the first reset pulse signal1Sum pulse length PWn1The voltage and the pulse length required by the gate are respectively reversely started, and the following conditions are met: -V1<-VthAnd PWn1>tndWhen the voltage is mainly applied to the gate, the resistance of the gate is set to the low resistance RslAnd is marked as state "1"; the resistive random access memory is still in a low resistance state, namely still in a state of 1; -VthIs the threshold voltage of the gate turned on in reverse, tndFor the reverse turn-on delay of the gate, VholdFor the forward holding voltage of the gate (i.e., the minimum voltage at which the gate can remain on after it has been turned on in the forward direction), -VholdA reverse holding voltage for the gate (i.e., a minimum voltage at which the gate can be kept in an on state after being reversely turned on); the reset pulse waveform of the present invention is shown in fig. 6;
(6) a second step of resetting operation, wherein the resetting process of the resistive random access memory comprises the following steps: applying a second reset pulse signal to the resistive random access memory array to enable the gate to keep a low-resistance state and the resistive random access memory to be in a high-resistance state; amplitude-V of the second reset pulse signal2Sum pulse length PWn2Respectively for resetting the voltage and pulse required by the resistive random access memoryLength, and satisfies: -V2<Vreset<-V1<-VthAnd PWn2>tresetWhen a voltage is applied to the resistive random access memory, the resistance value of the resistive random access memory is set to be high resistance RhAnd is marked as state "0", the gate is still in low resistance state, namely state "1"; vresetand-VthRespectively, the minimum voltage, t, at which the resistive random access memory is resetresetA reset delay for the resistive random access memory (i.e., a minimum pulse length required for the resistive random access memory to be reset-operated);
(7) and reducing the amplitude of the second reset pulse signal to zero, turning off the gate, recording as the state of 0, and finishing the reset operation.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (4)
1. A two-step writing operation method of a resistive random access memory array is characterized by comprising the following steps:
enabling initial states of a gate and a resistive random access memory in a resistive random access memory array to be in a high-resistance state;
applying a first write pulse signal to the resistive random access memory array to enable the gate to be in a low-resistance state and the resistive random access memory to be in a high-resistance state;
applying a second write pulse signal to the resistive random access memory array to enable the gate to keep a low-resistance state and the resistive random access memory to be in the low-resistance state;
reducing the amplitude of the second write pulse signal to zero, enabling the gate to be in a high-resistance state, enabling the resistive random access memory to be in a low-resistance state, and completing the write operation;
wherein the amplitude V of the first write pulse signal1Sum pulse length PW1The voltage and pulse length required for opening the gate in the forward direction, and the amplitude V of the second write pulse signal2Sum pulse length PW2Respectively, resistive random access memoryThe voltage and the pulse length required by the writing operation of the device are satisfied, and the parameters simultaneously satisfy the following requirements: (a) v2>Vset>V1>Vth，(b)PW1>td，(c)PW2>tset；VsetAnd VthThe minimum voltage at which the resistive random access memory can be written and the threshold voltage t at which the gate is turned on in the forward directiondAnd tsetRespectively a forward opening delay of the gate and a writing delay of the resistance random access memory.
2. The two-step write operation method according to claim 1, further comprising the steps of:
applying a first reset pulse signal to the resistive random access memory array to enable the gate to be in a low-resistance state and the resistive random access memory to be in the low-resistance state;
applying a second reset pulse signal to the resistive random access memory array to enable the gate to keep a low-resistance state and the resistive random access memory to be in a high-resistance state;
reducing the amplitude of the second reset pulse signal to zero, enabling the gate and the resistive random access memory to be in a high-resistance state, and finishing the reset operation;
wherein an amplitude-V of the first reset pulse signal1Sum pulse length PWn1Voltage and pulse length required for reversely turning on the gate, amplitude-V of the second reset pulse signal2Sum pulse length PWn2The voltage and the pulse length required by the reset operation of the resistive random access memory are respectively needed, and all the parameters simultaneously meet the following requirements: (d) -V2<Vreset<-V1<-Vth，(e)PWn1>tnd，(f)PWn2>treset；Vresetand-VthIs the minimum voltage at which the resistive random access memory can be reset and the threshold voltage at which the gate is turned on in reverse, tndAnd tresetRespectively a gate reverse turn-on delay and a resistive random access memory reset delay.
3. The two-step write operation method according to claim 1 or 2, wherein when both the gate and the resistive random access memory in the resistive random access memory array are in a high resistance state, a resistance value of the resistive random access memory is much larger than a resistance value of the gate.
4. The two-step write operation method according to claim 1 or 2, wherein the resistive random access memory array includes a plurality of word lines and bit lines arranged in a crossing manner, a memory cell is disposed at each crossing point of the bit lines and the word lines, and the memory cell includes a gate and a resistive random access memory connected to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011506701.4A CN112489709B (en) | 2020-12-18 | 2020-12-18 | Two-step writing operation method of resistive random access memory array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011506701.4A CN112489709B (en) | 2020-12-18 | 2020-12-18 | Two-step writing operation method of resistive random access memory array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112489709A true CN112489709A (en) | 2021-03-12 |
| CN112489709B CN112489709B (en) | 2022-12-09 |
Family
ID=74914654
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011506701.4A Active CN112489709B (en) | 2020-12-18 | 2020-12-18 | Two-step writing operation method of resistive random access memory array |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112489709B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113643741A (en) * | 2021-08-16 | 2021-11-12 | 湖北大学 | Logic operation unit and operation method based on 1S1R |
| CN114400032A (en) * | 2022-03-24 | 2022-04-26 | 之江实验室 | Method, device and medium for dynamically accelerating resistance value setting of resistive random access memory |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103337255A (en) * | 2013-06-21 | 2013-10-02 | 华中科技大学 | Quick write verification method and system aiming at resistive random access memory (RRAM) |
| US9171617B1 (en) * | 2014-06-27 | 2015-10-27 | Samsung Electronics Co., Ltd. | Resistive memory device and method programming same |
| CN105719691A (en) * | 2016-01-22 | 2016-06-29 | 清华大学 | Resistive random access memory operation method and resistive random access memory device |
-
2020
- 2020-12-18 CN CN202011506701.4A patent/CN112489709B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103337255A (en) * | 2013-06-21 | 2013-10-02 | 华中科技大学 | Quick write verification method and system aiming at resistive random access memory (RRAM) |
| US9171617B1 (en) * | 2014-06-27 | 2015-10-27 | Samsung Electronics Co., Ltd. | Resistive memory device and method programming same |
| CN105719691A (en) * | 2016-01-22 | 2016-06-29 | 清华大学 | Resistive random access memory operation method and resistive random access memory device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113643741A (en) * | 2021-08-16 | 2021-11-12 | 湖北大学 | Logic operation unit and operation method based on 1S1R |
| CN113643741B (en) * | 2021-08-16 | 2023-12-15 | 湖北大学 | 1S 1R-based logic operation unit and operation method |
| CN114400032A (en) * | 2022-03-24 | 2022-04-26 | 之江实验室 | Method, device and medium for dynamically accelerating resistance value setting of resistive random access memory |
| CN114400032B (en) * | 2022-03-24 | 2022-08-05 | 之江实验室 | Method, device and medium for dynamically accelerating resistance value setting of resistive random access memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112489709B (en) | 2022-12-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112489709B (en) | Two-step writing operation method of resistive random access memory array | |
| US8462580B2 (en) | Memory system with reversible resistivity-switching using pulses of alternatrie polarity | |
| US6944051B1 (en) | Data restore in thryistor based memory devices | |
| CN110111827B (en) | Multi-value resistive random access memory based on multiple single-value resistive random access memories | |
| US20140340956A1 (en) | Memory device and method of controlling memory device | |
| CN110569962B (en) | Convolution calculation accelerator based on 1T1R memory array and operation method thereof | |
| US8238138B2 (en) | Semiconductor memory device and its operation method | |
| TW202203228A (en) | Accessing a multi-level memory cell | |
| US9042159B2 (en) | Configuring resistive random access memory (RRAM) array for write operations | |
| US20230044537A1 (en) | Resistive random access memory array and operation method therefor, and resistive random access memory circuit | |
| US20210035636A1 (en) | Resistive random-access memory and architecture with select and control transistors | |
| CN111179991B (en) | Resistive random access memory array, operation method thereof and resistive random access memory circuit | |
| JP2012203926A (en) | Resistance change memory | |
| US8081506B2 (en) | Amorphous semiconductor threshold switch volatile memory cell | |
| CN113517008A (en) | Dynamic clamping memory computing circuit, memory and electronic equipment | |
| CN111146236B (en) | Resistive random access memory unit and array structure | |
| WO2020177089A1 (en) | 2t2r resistive random access memory with differential architecture, and mcu and device | |
| CN112071346B (en) | 3D cross array structure based on memristor cluster | |
| CN104752607A (en) | Resistive random access memory and manufacturing method | |
| US7733714B2 (en) | MIS-transistor-based nonvolatile memory for multilevel data storage | |
| CN110428857B (en) | Memory based on hysteresis characteristic device | |
| CN102789812A (en) | NOR memory cell based on resistance-changeable gate dielectric, its array and its operation method | |
| CN102842340A (en) | SRAM circuit based on PNPN structure, and reading and writing methods thereof | |
| CN116686430A (en) | Memory device and access method and manufacturing method thereof | |
| CN111755046A (en) | Biasing method of memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |