CN112486440B - Algorithm verification method and algorithm verification system - Google Patents
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Abstract
The application discloses an algorithm verification method and an algorithm verification system. The method comprises the following steps: acquiring video image data and video resolution thereof; identifying video resolution, and if the video resolution is the first resolution, rearranging video image data and converting a segmentation state to obtain first video image data; if the resolution is the second resolution, copying the video image data to obtain second video image data; and processing the first or second video image data to obtain output data, and performing frequency multiplication processing on the output data to output the output data. The method and the device can verify according to the actual refresh frequency of the display panel, and can verify the actual improvement effect of the video image algorithm on the display panel.
Description
Technical Field
The application relates to the technical field of display, in particular to an algorithm verification method and an algorithm verification system.
Background
Liquid Crystal Displays (LCDs) are now pursuing large-size, high resolution. As the size of the thin film transistor liquid crystal display (tft_lcd) is larger and larger, the resolution is higher and higher, and the corresponding data amount is multiplied in order to better ensure the quality of the panel. Most of the existing tft_lcd algorithms (including video image hardware algorithms and video image software algorithms) are verification effects in the static state.
Fig. 1 is a functional block diagram of an algorithm verification system in the prior art. The system shown in fig. 1 is used to verify the correctness of a video image hardware algorithm or a video image software algorithm. The algorithm verification system comprises: the system comprises a PC end 11, a conversion module 12, an algorithm verification module 13, a time sequence controller 14 and a signal connection plate 15.
The PC terminal 11 is configured to output test video image data. The conversion module 12 is configured to convert the test video image data into a Low-voltage differential signal (Low-Voltage Differential Signaling, abbreviated as LVDS) data signal, and output the Low-voltage differential signal, for example, the Low-voltage differential signal is converted into LVDS by HDMI/DVI (High Definition Multimedia Interface/Digital Visual Interface, high-definition multimedia interface/digital video interface) and output the LVDS to the algorithm verification module 13. The algorithm verification module 13 is an FPGA (FieldProgrammable Gate Array ) chip. The algorithm verification module 13 is configured to parse the acquired data signal to obtain test video image data in LVDS form, and perform a down-conversion process on the test video image data, and reduce the frequency of the test video image data below the refresh frequency of the panel 16 to obtain output video data. The algorithm verification module 13 further outputs output video data to the timing controller 14 (Timing Controller, TCON). The timing controller 14 is disposed on the timing control board C/B, and is configured to convert the output video data into corresponding driving control signals, and output the driving control signals to the panel 16 through the signal connection board 15 (X/B) to control the panel 16 to display corresponding video images. Wherein a video image hardware algorithm or a video image software algorithm is provided inside the algorithm verification module 13.
Currently, the high resolution (Ultra High Definition, UD or UHD for short) display technologies supporting ud@120hz and 8k@60hz, 8k@120hz, that is, the FPGA algorithm verification platform with the display technology having the resolution of 3840×2160 (4 k×2k) and above (e.g., 8K) is realized by reducing the output refresh frequency (i.e., the down-conversion process, or the dot-half screen) of the video source. Thus, only whether the data of the algorithm is correct or not can be verified, and the actual effect of the algorithm on the display panel cannot be completely verified.
Therefore, it is necessary to provide an algorithm verification method, which solves the defect that the effect of the algorithm on the display panel cannot be verified according to the actual frequency under the high resolution and high refresh frequency (8K@120hz) of the existing FPGA algorithm platform.
Disclosure of Invention
In order to solve the technical problems, the application provides an algorithm verification method and an algorithm verification system, which can verify the effect of an algorithm on a display panel according to actual frequency, so that the actual improvement effect of a video image algorithm on the display panel can be verified, a hardware system is simplified, and the display hardware cost under 8K resolution is reduced.
According to a first aspect of the present application, there is provided an algorithm verification method comprising the steps of: s1, acquiring initial video image data and video resolution thereof; s2, identifying the video resolution and obtaining an identification result; s3, if the identification result is that the video resolution is the first resolution, rearranging the initial video image data, converting the rearranged video image data from a first segmentation state to a second segmentation state, acquiring first video image data, and executing a step S5; s4, if the identification result is that the video resolution is the second resolution, copying and processing the initial video image data to obtain second video image data, and executing a step S5; s5, carrying out algorithm processing on the first video image data or the second video image data according to a preset algorithm to obtain first output data; s6, performing frequency multiplication processing on the first output data to obtain second output data and outputting the second output data, wherein the frequency of the second output data is equal to that of the initial video image data.
According to a second aspect of the present application, there is provided an algorithm verification system comprising an algorithm verification module comprising: the data acquisition unit is used for acquiring initial video image data and video resolution thereof; the read-write controller is used for identifying the video resolution and acquiring an identification result, if the identification result is that the video resolution is the first resolution, the initial video image data is rearranged, the rearranged video image data is converted into a second segmentation state from the first segmentation state, the first video image data is acquired, and if the identification result is that the video resolution is the second resolution, the initial video image data is duplicated and processed, and the second video image data is acquired; the algorithm processing unit is used for carrying out algorithm processing on the first video image data or the second video image data according to a preset algorithm to obtain first output data; and the frequency multiplication controller is used for carrying out frequency multiplication processing on the first output data, obtaining second output data and outputting the second output data, wherein the frequency of the second output data is equal to the frequency of the initial video image data.
The application has the following beneficial effects:
the method and the device can verify according to the actual refresh frequency of the display panel, and can verify the actual improvement effect of the video image algorithm on the display panel. Meanwhile, the display driving mode under the 8K resolution is converted, and on the basis that the display effect is equivalent to the traditional 8K resolution, the hardware system is simplified, and the display cost is reduced.
Drawings
Technical solutions and other advantageous effects of the present application will be made apparent from the following detailed description of specific embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a functional block diagram of an algorithm verification system in the prior art.
FIG. 2 is a flow chart of an embodiment of an algorithm verification method of the present application.
FIG. 3 is a block diagram of one embodiment of an algorithm verification system of the present application.
Fig. 4 is a block diagram of the algorithm verification module of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
The following disclosure provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not in themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize the application of other processes and/or the use of other materials.
Referring to fig. 2, a flowchart of an embodiment of an algorithm verification method is shown. As shown in fig. 2, the algorithm verification method of the present application includes the following steps: s1, acquiring initial video image data and video resolution thereof; s2, identifying the video resolution and obtaining an identification result; s3, if the identification result is that the video resolution is the first resolution, rearranging the initial video image data, converting the rearranged video image data from a first segmentation state to a second segmentation state, acquiring first video image data, and executing a step S5; s4, if the identification result is that the video resolution is the second resolution, copying and processing the initial video image data to obtain second video image data, and executing a step S5; s5, carrying out algorithm processing on the first video image data or the second video image data according to a preset algorithm to obtain first output data; s6, performing frequency multiplication processing on the first output data to obtain second output data and outputting the second output data, wherein the frequency of the second output data is equal to that of the initial video image data. A detailed description is given below.
With respect to the step S1, an initial video image data and a video resolution thereof are acquired.
The step S1 further includes: and receiving test data, acquiring a data signal according to the test data, and analyzing the data signal to acquire the initial video image data and the video resolution.
Specifically, the PC side may output the test data and corresponding display parameter information, where the display parameter information includes the video resolution. And then a conversion module receives the display parameter information and converts the display parameter information into a signal of corresponding serial data to be output. The conversion module receives the test data, encodes the test data to obtain the data signal, and outputs the data signal, wherein the data signal can be a Low Voltage Differential Signal (LVDS). And then analyzing the data signals to obtain the initial video image data and the display parameter information. Specifically, the display parameter information includes the video resolution. The data signal may be parsed by an FPGA, for example.
Regarding the step S2, the video resolution is identified and an identification result is obtained.
Specifically, in the step S2, a DDR3 (Double-Data-Rate Three) controller may identify the video resolution and obtain the identification result.
Regarding the step S3, if the identification result is that the video resolution is the first resolution, the initial video image data is rearranged, the rearranged video image data is converted from the first segmentation state to the second segmentation state, the first video image data is obtained, and the step S5 is executed.
Specifically, the first resolution is 8K; the 8K resolution is also 8K UHD (Ultra High Definition ), which means that the horizontal resolution of the display device is 7680 pixels (pixels) and the total image size is (7680×4320). The horizontal and vertical resolution of 8K UHD is twice that of 4K UHD, and the total pixel is four times that. The first segmentation state is characterized in that equal-value segmentation is carried out according to two rows and two columns, and the first segmentation state is in a shape of a Chinese character 'tian'; the second segmentation state is to perform equivalent segmentation according to one row and four columns and is in a shape of Chinese character Chuan.
The step S3 further includes: s31, after the initial video image data are rearranged, a segmentation signal is obtained; s32, converting the segmentation signals into one complementary code signal corresponding to the initial video image data through a complementary code algorithm; s33, the complementary code signals are cut into 4 sub-complementary code signals according to one row, four columns and the equivalent; s34, dividing the initial video image data according to the sub-complement signals.
And under the condition that the video resolution is 8K, rearranging the initial video image data, and writing the rearranged initial video image data into a memory bank of a DDR3 controller. Changing the dividing state of the initial video image data for driving, acquiring the first video image data according to the second dividing state, and outputting the first video image data from left to right. That is, the four-way video data which is originally driven according to the first division state (the 'field' shape) in the prior art is changed to be driven according to the second division state (the 'Chuan' shape). The whole identification and processing process is completed in the DDR3 controller. The DDR3 controller may be the same as the DDR3 controller used in step S2.
The step S3 further includes: and processing the segmented initial video image data according to a preset mode, so that the frequency of the first video image data is smaller than that of the initial video image data. Wherein the frequency of the initial video image data is included in the display parameter information, that is, the frequency of the initial video image data may be acquired in step S1.
The DDR3 controller reads data requiring down-conversion reading for processing by an algorithm, and the preset pattern may cause the frequency of the first video image data to be lower than the refresh frequency of the display panel, so that the frequency of the first video image data is lower than the frequency of the initial video image data. The memory FIFO (First Input First Output) and buffer are typically used to perform the correlation operations after convolution or pooling calculations.
Regarding the step S4, if the identification result is that the video resolution is the second resolution, the initial video image data is copied and processed to obtain second video image data, and step S5 is executed.
Specifically, the second resolution is 4K. The step S4 further includes: and processing the second video image data according to a preset mode, so that the frequency of the second video image data is smaller than that of the initial video image data. The second video image data is obtained by copying four times of the initial video image data, and the resolution of the second video image data is 8K. That is, by performing a copy process on the initial video image data of 4K, an 8K image composed of four 4K UD (Ultra High Definition) is output.
Step S4 and step S3 and step S2 may be performed in the same DDR3 controller. The preset pattern in step S4 is used for the down-conversion process, and the down-conversion process used in step S3 may be continued, that is, the memory FIFO (First Input First Output) and the buffer may be used, and the relevant operations may be performed after convolution or pooling calculation.
Regarding the step S5, according to a preset algorithm, the first video image data or the second video image data is subjected to algorithm processing to obtain first output data.
The preset algorithm is a corresponding algorithm developed by TFT_LCD manufacturers and can be stored in an FPGA chip.
And regarding the step S6, performing frequency multiplication processing on the first output data to obtain second output data and outputting the second output data. Wherein the frequency of the second output data is equal to the frequency of the initial video image data.
The step S6 may be completed in another DDR3 controller. The second output data has a lower frequency relative to the initial video image data, and is also typically below the refresh frequency of the display panel. And performing frequency multiplication operation on the second output data, so that the corresponding panel can be driven, and further, the actual improvement effect of the video image hardware algorithm or the video image software algorithm on the display panel is completely verified.
The method and the device can verify according to the actual refresh frequency of the display panel, and can verify the actual improvement effect of the video image algorithm on the display panel. Meanwhile, the display driving mode under the 8K resolution is converted, and on the basis that the display effect is equivalent to the traditional 8K resolution, the hardware system is simplified, and the display cost is reduced.
Based on the same inventive concept, the application also provides an algorithm verification system.
Referring to fig. 3 and fig. 4 together, fig. 3 is a block diagram illustrating an embodiment of an algorithm verification system according to the present application, and fig. 4 is a block diagram illustrating an algorithm verification module according to the present application. As shown in fig. 3, the algorithm verification system 3 includes an algorithm verification module 30. As shown in fig. 4, the algorithm verification module 30 mainly includes: a data acquisition unit 301, a read-write controller 302, an algorithm processing unit 303, and a frequency multiplication controller 304.
Specifically, the algorithm verification module 30 is an FPGA (Field Programmable Gate Array ) chip, including an embedded memory.
The data acquisition unit 301 is configured to acquire an initial video image data and a video resolution thereof.
The read-write controller 302 is configured to identify the video resolution and obtain an identification result. If the identification result is that the video resolution is the first resolution, rearranging the initial video image data, converting the rearranged video image data from a first segmentation state to a second segmentation state, and acquiring first video image data; and if the identification result is that the video resolution is the second resolution, copying the initial video image data to obtain second video image data. Wherein, when the initial video image data is duplicated, the initial video image data should be duplicated four times.
The read/write controller 302 may be a DDR3 (Double-Data-Rate Three) controller, which is used in conjunction with DDR3 memory. The read-write controller 302 may also be used to set the drive partition of the video to be single-chip or multi-chip, and alleviate the hardware pressure by partitioning.
The algorithm processing unit 303 is configured to perform algorithm processing on the first video image data or the second video image data according to a preset algorithm to obtain first output data. The algorithm processing unit 303 is mostly an IP core.
The frequency multiplication controller 304 is configured to perform frequency multiplication processing on the first output data, obtain second output data, and output the second output data. Wherein the frequency of the second output data is equal to the frequency of the corresponding initial video image data. The frequency doubling controller 304 may also be a DDR3 controller, and may be used in conjunction with DDR3 memory.
In a further embodiment, as shown in fig. 4, the algorithm verification module 30 further includes a parameter control unit 305 and a video rearrangement unit 306.
The parameter control unit 305 is configured to perform parameter configuration on the video rearrangement unit 306, the read-write controller 301, the algorithm processing unit 303, and the frequency multiplication controller 304, and control the algorithm verification module 30 to work.
The video rearrangement unit 306 is respectively connected to the data acquisition unit 301 and the read-write controller 302, and is configured to rearrange the initial video image data with a video resolution of a first resolution, acquire rearranged video image data, write the rearranged video image data into the read-write controller 302, and acquire the first video image data according to the rearranged video image data.
Specifically, if the identification result is the first resolution (8K), the video rearrangement unit 306 is called to rearrange the initial video image data; the rearranged video image data is converted from the first segmentation state to the second segmentation state, the first video image data is obtained, and the algorithm processing unit 303 is invoked. That is, the four-way video data which is originally driven according to the first division state (the 'field' shape) in the prior art is changed to be driven according to the second division state (the 'Chuan' shape).
As shown in fig. 3, the algorithm verification system 3 further includes a PC terminal 31 and a timing controller 32. Wherein: the PC terminal 31 may be connected to the algorithm verification module 30 through a conversion module 33. The timing controller 32 may be connected to the display panel 4 through a signal connection board 34, and outputs a driving control signal corresponding to the second output data to the display panel 4 through the signal connection board 34.
Referring to fig. 3, specifically, the PC terminal 31 is configured to output the test data and the corresponding display parameter information to the conversion module 33. The serial interface in the conversion module 33 receives the display parameter information and outputs the display parameter information to the algorithm verification module 30. The digital video interface/high definition multimedia interface (HDMI/DVI interface) in the conversion module 33 receives the test data, encodes the test data to obtain the data signal, and outputs the data signal to the algorithm verification module 30. Wherein the data signal may be a Low Voltage Differential Signal (LVDS). The display parameter information may include the video resolution and the frequency of the initial video image data.
Preferably, the data acquisition unit 301 is connected to the conversion module 33, and is configured to parse the data signal output by the conversion module 33 to acquire the initial video image data and the display parameter information including the video resolution.
The algorithm verification module 30 and the timing controller 32 may be connected through a VB1 (V-BY-one) interface. The algorithm verification module 30 converts the second output data in the form of the low-voltage differential signal into the second video data in the form of the corresponding VB1 signal according to the VB1 protocol, and transmits the second video data through a VB1 interface.
The timing controller 32 may be connected to the display panel 4 through a signal connection board 34, and is configured to obtain a corresponding driving control signal according to the second video data, and output the driving control signal to the display panel 4, so as to control the display panel 4 to display a corresponding video image. The test video image data is processed, and then the display effect of the display panel 4 is tested and analyzed to judge whether the video data processed by the algorithm meets the requirement, so that the algorithm is judged to be correct, and the purpose of verifying the video image algorithm is achieved.
Aiming at the defect that the effect of the conventional FPGA algorithm platform on the panel cannot be verified according to the actual frequency under the high-resolution high-refresh frequency (8K@120 hz), the embodiment provides a method for realizing the effect of the conventional FPGA algorithm platform on the panel according to the actual frequency. The verification can be performed according to the actual refresh frequency of the display panel, and the actual improvement effect of the video image algorithm on the display panel can be verified. Meanwhile, the display driving mode under the 8K resolution is converted, and on the basis that the display effect is equivalent to the traditional 8K resolution, the hardware system is simplified, and the display cost is reduced.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
The foregoing has described in detail a method and system for verifying an algorithm provided by the embodiments of the present application, and specific examples are applied to illustrate the principles and embodiments of the present application, where the foregoing description of the embodiments is only for helping to understand the technical solution and core ideas of the present application; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.
Claims (8)
1. An algorithm verification method is characterized by comprising the following steps:
s1, acquiring initial video image data and video resolution thereof;
s2, identifying the video resolution and obtaining an identification result;
s3, if the identification result is that the video resolution is the first resolution, rearranging the initial video image data, converting the rearranged video image data from a first segmentation state to a second segmentation state, acquiring first video image data, and executing a step S5;
s4, if the identification result is that the video resolution is the second resolution, copying and processing the initial video image data to obtain second video image data, and executing a step S5;
s5, carrying out algorithm processing on the first video image data or the second video image data according to a preset algorithm to obtain first output data;
s6, performing frequency multiplication processing on the first output data to obtain second output data and outputting the second output data, wherein the frequency of the second output data is equal to that of the initial video image data;
wherein, the step S3 includes: processing the segmented initial video image data according to a preset mode, so that the frequency of the first video image data is smaller than that of the initial video image data;
wherein, the step S4 includes: and processing the second video image data according to a preset mode, so that the frequency of the second video image data is smaller than that of the initial video image data.
2. The algorithm verification method according to claim 1, wherein the step S1 further comprises: and receiving test data, acquiring a data signal according to the test data, and analyzing the data signal to acquire the initial video image data and the video resolution.
3. The algorithm verification method according to claim 1, wherein in the step S3, the first segmentation state is equal-value segmentation according to two rows and two columns, and the second segmentation state is equal-value segmentation according to one row and four columns.
4. The algorithm verification method according to claim 1, wherein the step S3 further comprises:
s31, after the initial video image data are rearranged, a segmentation signal is obtained;
s32, converting the segmentation signals into one complementary code signal corresponding to the initial video image data through a complementary code algorithm;
s33, the complementary code signals are cut into 4 sub-complementary code signals according to one row, four columns and the equivalent;
s34, dividing the initial video image data according to the sub-complement signals.
5. The algorithm verification method according to claim 1, wherein in the step S4, the resolution of the second video image data is the first resolution.
6. An algorithm verification system, the algorithm verification system comprising an algorithm verification module, the algorithm verification module comprising:
the data acquisition unit is used for acquiring initial video image data and video resolution thereof;
the read-write controller is used for identifying the video resolution and acquiring an identification result, if the identification result is that the video resolution is the first resolution, the initial video image data is rearranged, the rearranged video image data is converted into a second segmentation state from the first segmentation state, the first video image data is acquired, and if the identification result is that the video resolution is the second resolution, the initial video image data is duplicated and processed, and the second video image data is acquired;
the algorithm processing unit is used for carrying out algorithm processing on the first video image data or the second video image data according to a preset algorithm to obtain first output data; the method comprises the steps of,
the frequency multiplication controller is used for carrying out frequency multiplication processing on the first output data to obtain second output data and outputting the second output data, wherein the frequency of the second output data is equal to the frequency of the initial video image data;
the read-write controller is used for processing the segmented initial video image data according to a preset mode, so that the frequency of the first video image data is smaller than that of the initial video image data;
the read-write controller is used for processing the second video image data according to a preset mode, so that the frequency of the second video image data is smaller than that of the initial video image data.
7. The algorithm verification system of claim 6, wherein the algorithm verification system further comprises: a PC end and a timing controller;
the PC end is connected with the algorithm verification module through a conversion interface and is used for outputting test data to the algorithm verification module;
the data acquisition unit is further used for analyzing the test data and acquiring the initial video image data and the video resolution;
the time sequence controller is connected with the algorithm verification module and the display panel through a signal connection board, and is used for receiving the second output data and converting the second output data into corresponding driving control signals, and then outputting the driving control signals to the display panel through the signal connection board so as to control the display panel to display corresponding video images.
8. The algorithm verification system of claim 6, wherein the algorithm verification module further comprises:
the video rearrangement unit is respectively connected with the data acquisition unit and the read-write controller and is used for rearranging the initial video image data with the video resolution of a first resolution, acquiring rearranged video image data and writing the rearranged video image data into the read-write controller;
and the parameter control unit is used for respectively carrying out parameter configuration on the video rearrangement unit, the read-write controller, the algorithm processing unit and the frequency multiplication controller.
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