CN112468244B - Balanced delay method and transceiving frequency conversion channel system with balanced delay module - Google Patents
Balanced delay method and transceiving frequency conversion channel system with balanced delay module Download PDFInfo
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- CN112468244B CN112468244B CN202011195671.XA CN202011195671A CN112468244B CN 112468244 B CN112468244 B CN 112468244B CN 202011195671 A CN202011195671 A CN 202011195671A CN 112468244 B CN112468244 B CN 112468244B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/30—Monitoring; Testing of propagation channels
- H04B17/309—Measuring or estimating channel quality parameters
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/30—Monitoring; Testing of propagation channels
- H04B17/391—Modelling the propagation channel
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- H—ELECTRICITY
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- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03878—Line equalisers; line build-out devices
Abstract
The invention discloses a balanced delay module and a transceiving frequency conversion channel system with the balanced delay module, belonging to the field of transceiving frequency conversion channel systems; a transceiving frequency conversion channel system with an equalization delay module, comprising: the device comprises a transmitter, a receiver, a balanced delay module, a detection module and an amplification module; the invention establishes a channel model through channel measurement, thereby obtaining the maximum information quantity and transmission quality which can be transmitted in a transmittable channel; the path loss and shadow attenuation existing between the transmitter and the receiver are detected by transmitting a plurality of beams of detection signals, so that the transmission pass is equalized, and when the frequency response of each channel after the equalizer is added and the frequency response of an ideal channel are in a fluctuable error range, the realization of equalizing channels is completed; meanwhile, a control network is established in the channel transmission network, so that the mutual balance and stability among the channels, the loads and the system are required to be established after the channels are balanced.
Description
Technical Field
The invention discloses an equalizing delay method and a transceiving frequency conversion channel system with an equalizing delay module, and belongs to the field of transceiving frequency conversion channel systems.
Background
With the development of communication, radar and measurement and control technologies, the widespread application of the technologies and the promotion of integrated circuits and software technologies, the requirements on related software and hardware equipment indexes are higher and higher; in the field of communication, with the increasing complexity of communication modulation modes and the increasing increase of channel transmission capacity; therefore, the code rate of data transmission of a communication system is more and more separated, and the requirements on various characteristics of channel transmission are more and more separated; ensuring high-quality undistorted transmission of signals is a consistent requirement in different fields; measuring transmission performance and indexes in a communication system, and having different requirements on time domain characteristics and frequency domain characteristics of a transmission network; undistorted transmission of signals in a frequency domain is divided into an amplitude-frequency characteristic and a phase-frequency characteristic; according to the basic theory of signals and systems, an ideal signal undistorted transmission system has the requirements of all-pass characteristics on amplitude-frequency characteristics and linear relation between frequency and phase characteristics.
When a receiving-transmitting frequency conversion channel system in the prior art receives signals, the strength of signals in a channel can be changed due to path loss and shadow attenuation problems existing between a transmitter and a receiver in transmission, so that the received signals are weakened, meanwhile, the frequency is changed through transmission, so that the fluctuation of the signals in the transmission is unstable, signal disorder can be reappeared in severe cases, and when the path loss in the channel is too large, the frequency and amplitude phase errors in the channel can be increased, so that the channel is mismatched.
Disclosure of Invention
The purpose of the invention is as follows: the invention provides a balanced delay method and a transceiving frequency conversion channel system with a balanced delay module, which are used for solving the problems.
The technical scheme is as follows: a method of equalizing delay, comprising:
and 4, setting stable transmission rate delay.
Preferably, in the process of transmitting and receiving signals, a channel model is established through channel measurement, so that the maximum information quantity and transmission quality which can be transmitted in a transmittable channel can be obtained; the method comprises the following specific steps:
step 101, sending a plurality of pseudo-random codes to a channel through a transmitter to serve as detection signals S1, S2 and S3.... SN;
step 102, ensuring that the detection signal does not generate an aliasing phenomenon at a receiving end, and ensuring that the repetition period of the detection signal is less than the channel change time and must be greater than the maximum multipath of the channel; thus, it follows:
wherein Tsn represents a repetition period of each detection signal;
fmax denotes the sampling rate of each probe signal in the channel;
zmax denotes the maximum multipath of the channel;
103, when the detection signal meets the condition of the step 102, receiving the detection signal through a receiver;
104, extracting the change process of the signal detection signal in the channel;
105, extracting a pseudo-random code sequence in the detection signal by the receiving system, and sequencing the pseudo-random code sequence and a local sequence to extract a correlation value;
step 106, judging whether the extracted correlation value has a maximum value; when the maximum value exists, the received signal and the transmitted signal are the same sequence; otherwise, the result is not;
step 107, extracting channel impact response from the pseudo-random sequence code of the same sequence in the step 106;
108, extracting channel weakening characteristics according to channel impact response;
step 109, because the path loss and shadow attenuation problems existing between the transmitter and the receiver may cause the intensity change of the signal in the channel (in the actual process, shadow attenuation is a shadow effect caused by blocking of an obstacle in a transmission path, and the number of the existing obstacles cannot be accurately determined, so that only the path loss is calculated), the path loss is obtained according to the transmitter power and the receiver power, and the path loss is specifically obtained according to the following formula:
wherein P1 represents the transmitter power;
p2 denotes receiver power;
p represents a path loss;
and when the performance test of the channel is finished, calculating to obtain the path loss P, and balancing the channel frequency according to the path loss.
Preferably, when the path loss in the channel is too large, the frequency and amplitude phase errors inside the channel will become large, thereby causing channel mismatch, so that a channel frequency equalization channel needs to be established, which includes the following specific steps:
step 201, establishing an ideal channel; n transmission channels are provided, and an equalizer with frequency response B is added into each transmission channel, wherein the frequency response of each channel is K; the frequency response of the equalization channel can thus be derived as:
JN＝N*(B*K)N＝1,2,3,…,N
JN represents the frequency response of the channel after the equalizer is added;
step 202, when the frequency response of each channel after the equalizer is added and the frequency response of the ideal channel are in a fluctuable error range, the realization of the equalization channel is completed;
step 203, after the implementation of the equalization channel is completed, the module will perform equalization channel detection; namely, the mismatch ratio of the equalization channel at this time is calculated as follows:
in the formula, DN represents the mismatch rate of the equalization channel;
c represents the frequency response of the reference channel;
depending on the mismatch ratio, the amplitude and phase of the channel at that time are thus related, so that it can be further derived:
in the formula, A is amplitude mismatch rate, and E is phase mismatch rate;
therefore, the equalizer is added in the channel to realize equalization, and the mismatch rate of the channel can be greatly reduced.
Preferably, after the channel is balanced, the mutual balance and stability among the channel, the load and the system are required to be established, so that the stability of transmission is ensured; the method comprises the steps of establishing a control network in a channel transmission network, arranging a plurality of controllers in each control network, arranging a plurality of nodes in each control network, sequencing all nodes in the network, selecting the largest node, and setting a node root, so that a tree-shaped development structure is selected for sequencing to generate a node range, further the working range of the control network is determined, arranging a switch in each control network, wherein the switch is used for carrying out connection transmission with other control networks, and further determining the mapping relation between the controllers and the switches according to the detected limiting conditions in the channel performance test, thereby ensuring the normal operation of the transmission network.
Preferably, the controller in each control network correspondingly controls one area, the range of the corresponding control area of each controller is determined according to the distance between the switch and the controller, the control area of the overlapping switch is determined according to the corresponding control area of each controller, and the area controlled by the switch is further adjusted according to the control area of the overlapping switch, so that the balanced channel control network for signal transmission is determined.
Preferably, stable transmission delay and control are set according to the implementation of the determined control network and equalization channel, a time T1 for sending a detection signal from the transmitter is recorded, when the time for receiving by the receiver is T2, when the time for inputting the signal into the system is T3, the time for converting the signal into a PWM wave is T4, when the signal is transmitted each time, the system automatically delays for a period of time T5, and the time for outputting the PWM wave is T6; based on the size of the time T3 for inputting the signal into the system, the delay time T5 for signal transmission is shortened, and the time T4 for converting the signal into a PWM wave inside the system is shortened.
A transmit-receive frequency-conversion channel system, comprising: the device comprises a transmitter, a receiver, a balanced delay module, a detection module and an amplification module;
the balanced delay module is used for realizing the stability and the emission delay of a frequency conversion channel;
the amplifying module is used for amplifying the time output signal;
and the detection module is used for detecting the waveform of the output signal.
Preferably, the equalization delay module comprises a filter circuit; the filter circuit includes: the filter U4, the resistor R21, the capacitor C12, the capacitor C11, the resistor R24, the resistor R20 and the amplifier U5A; the input signal of pin 3 of the filter U4, the input voltage of pin 5 of the filter U4, pin 6 of the filter U4 is connected with one end of the resistor R21, pin 7 of the filter U4 is connected with the other end of the resistor R21 and grounded, pin 4 of the filter U4 is connected with pin 1 and simultaneously connected with one end of the capacitor C11, one end of the resistor R20 and one end of the resistor R24, the voltage is input at the other end of the resistor R24, pin 2 of the filter U4 is simultaneously connected with the other end of the capacitor C11 and the other end of the resistor R20, pin 8 of the filter U4 is connected with pin 3 of the amplifier U5A, and pin 2 of the amplifier U5A is connected with pin 1 and outputs a signal.
Preferably, the detection module includes: the amplifier U1A, the amplifier U1B, the amplifier U2A, the resistor R3, the resistor R1, the resistor R2, the resistor R4, the capacitor C4, the resistor R5, the resistor R6, the capacitor C2, the capacitor C3, the resistor R7, the resistor R8, the capacitor C1, the transistor Q1, the resistor R13, the resistor R12, the voltage-regulator tube D2, the transistor Q2, the resistor R11, the voltage-regulator tube D1, the resistor R10 and the resistor R9;
one end of the resistor R3 is connected with a pin No. 3 of the amplifier U1A and inputs a signal, the other end of the resistor R3 is grounded, a pin No. 2 of the amplifier U1A is connected with a pin No. 1 and is simultaneously connected with one end of the resistor R1 and one end of the resistor R2, a pin No. 6 of the amplifier U1B is simultaneously connected with the other end of the resistor R1, one end of the resistor R4 and one end of the capacitor C4, a pin No. 5 of the amplifier U1B is simultaneously connected with the other end of the resistor R2, one end of the capacitor C1 and one end source of the transistor Q2, a drain of the transistor Q2 is connected with the other end of the capacitor C1 and is grounded, a gate of the transistor Q2 is simultaneously connected with one end of the resistor R13 and an anode of the stabilivolt D2, the other end of the resistor R13 is grounded, a cathode of the stabilivolt D2 is simultaneously connected with one end of the resistor R12 and one end of the collector of the transistor Q1, the other end of the resistor R12 is grounded, the emitter of the transistor Q1 is simultaneously connected with one end of the resistor R10, the cathode of the regulator D1 and one end of the resistor R11, the other end of the resistor R11 inputs a voltage, the anode of the regulator D1 is grounded, the gate of the transistor Q1 is simultaneously connected with the other end of the resistor R10 and one end of the resistor R9, the other end of the resistor R9 inputs an operating voltage, the pin No. 7 of the amplifier U1B is simultaneously connected with the other end of the resistor R4, the other end of the capacitor C4 and one end of the resistor R5, the other end of the resistor R5 is simultaneously connected with one end of the resistor R6 and one end of the capacitor C2, the other end of the resistor R6 is simultaneously connected with one end of the capacitor C3 and the pin No. 3 of the amplifier U2A, the other end of the capacitor C3 is grounded, the pin No. 2 of the amplifier U2 is simultaneously connected with one end of the resistor R5475 and one end of the resistor R8, the other end of the resistor R7 is grounded, and the pin No. 1 of the amplifier U2A is connected with the other end of the resistor R8 and the other end of the capacitor C2 at the same time and outputs signals.
Preferably, the amplifying module includes: the circuit comprises an amplifier U3A, an amplifier U3B, a resistor R14, a capacitor C6, a capacitor C5, a resistor R15, a resistor R16, a polar capacitor C7, a resistor R17, a capacitor C9, a resistor R19, a polar capacitor C8, a resistor R18, a resistor R23, a resistor R22 and a capacitor C10;
pin No. 2 of the amplifier U3A is connected to one end of the resistor R15 and one end of the capacitor C5, the other end of the capacitor C5 is connected to one end of the capacitor C6 and one end of the resistor R14, and a signal is input thereto, pin No. 3 of the amplifier U3A is connected to one end of the resistor R17, one end of the capacitor C9 and one end of the resistor R15, the other end of the resistor R15 is connected to one end of the polar capacitor C7, the other end of the capacitor C6 is connected to one end of the resistor R14 and the other end of the resistor R16, and ground, pin No. 4 of the amplifier U3A is connected to the other end of the resistor R16 and the other end of the polar capacitor C7, pin No. 1 of the amplifier U3A is connected to the other end of the capacitor C9, the other end of the resistor R17 and the other end of the resistor R19, and one end of the resistor 19 is connected to one end of the capacitor C8, the No. 5 pin of the amplifier U3B is connected to the other end of the polar capacitor C8, one end of the resistor R22 and one end of the capacitor C10, the No. 6 pin of the amplifier U3B is connected to one end of the resistor R18 and one end of the resistor R23, the other end of the resistor R18 is connected to the other end of the polar capacitor C7 and the No. 4 pin of the amplifier U3B, the No. 7 pin of the amplifier U3B is connected to the other end of the capacitor C10 and the other end of the resistor R22, the other end of the resistor R23 is connected to the No. 11 pin of the amplifier U3A and the No. 11 pin of the amplifier U3B, the No. 11 pin of the amplifier U3A inputs the reference voltage, and the No. 11 pin of the amplifier U3B inputs the working voltage.
Has the advantages that: in the process of transmitting and receiving signals, the channel model is established through channel measurement, so that the maximum information quantity and transmission quality which can be transmitted in a transmittable channel can be obtained; the path loss and shadow attenuation existing between the transmitter and the receiver are detected by transmitting a plurality of beams of detection signals, so that the transmission pass is equalized, and when the frequency response of each channel after the equalizer is added and the frequency response of an ideal channel are in a fluctuable error range, the realization of equalizing channels is completed; meanwhile, a control network is established in the channel transmission network, so that the mutual balance and stability among the channels, the loads and the system are required to be established after the channels are balanced.
Drawings
FIG. 1 is a flow chart of the operation of the present invention.
FIG. 2 is a circuit diagram of a detector module according to the present invention.
Fig. 3 is a circuit diagram of an amplifying module of the present invention.
Fig. 4 is a circuit diagram of a filter module of the present invention.
Detailed Description
As shown in fig. 1, in this embodiment, an equalizing delay method and a transceiver frequency conversion channel system with an equalizing delay module include: the device comprises a transmitter, a receiver, a balanced delay module, a detection module and an amplification module.
In a further embodiment, the equalization delay module includes a filter circuit; the filter circuit includes: the filter U4, resistance R21, electric capacity C12, electric capacity C11, resistance R24, resistance R20, amplifier U5A.
In a further embodiment, the pin No. 3 of the filter U4 inputs a signal, the pin No. 5 of the filter U4 inputs a voltage, the pin No. 6 of the filter U4 is connected to one end of the resistor R21, the pin No. 7 of the filter U4 is connected to the other end of the resistor R21 and grounded, the pin No. 4 of the filter U4 is connected to the pin No. 1 and simultaneously connected to one end of the capacitor C11, one end of the resistor R20 and one end of the resistor R24, the other end of the resistor R24 inputs a voltage, the pin No. 2 of the filter U4 is simultaneously connected to the other end of the capacitor C11 and the other end of the resistor R20, the pin No. 8 of the filter U4 is connected to the pin No. 3 of the amplifier U5A, and the pin No. 2 of the amplifier U5A is connected to the pin No. 1 and outputs a signal.
In a further embodiment, the detection module comprises: the amplifier comprises an amplifier U1A, an amplifier U1B, an amplifier U2A, a resistor R3, a resistor R1, a resistor R2, a resistor R4, a capacitor C4, a resistor R5, a resistor R6, a capacitor C2, a capacitor C3, a resistor R7, a resistor R8, a capacitor C1, a transistor Q1, a resistor R13, a resistor R12, a voltage regulator tube D2, a triode Q1, a resistor R11, a voltage regulator tube D1, a resistor R10 and a resistor R9.
In a further embodiment, one end of the resistor R3 is connected to pin No. 3 of the amplifier U1A and inputs a signal, the other end of the resistor R3 is grounded, pin No. 2 of the amplifier U1A is connected to pin No. 1 and simultaneously connected to one end of the resistor R1 and one end of the resistor R2, pin No. 6 of the amplifier U1B is simultaneously connected to the other end of the resistor R1, one end of the resistor R4 and one end of the capacitor C4, pin No. 5 of the amplifier U1B is simultaneously connected to the other end of the resistor R2, one end of the capacitor C1 and one end of the transistor Q2, the drain of the transistor Q2 is connected to the other end of the capacitor C1 and grounded, the gate of the transistor Q2 is simultaneously connected to one end of the resistor R13 and the positive electrode of the regulator D2, the other end of the resistor R13 is grounded, the negative electrode of the regulator D2 is simultaneously connected to one end of the resistor R12 and the collector of the transistor Q1, the other end of the resistor R12 is grounded, the emitter of the transistor Q1 is simultaneously connected with one end of the resistor R10, the cathode of the regulator tube D1 and one end of the resistor R11, the other end of the resistor R11 inputs a voltage, the anode of the regulator tube D1 is grounded, the gate of the transistor Q1 is simultaneously connected with the other end of the resistor R10 and one end of the resistor R9, the other end of the resistor R9 inputs an operating voltage, the pin No. 7 of the amplifier U1B is simultaneously connected with the other end of the resistor R4, the other end of the capacitor C4 and one end of the resistor R5, the other end of the resistor R5 is simultaneously connected with one end of the resistor R6 and one end of the capacitor C2, the other end of the resistor R6 is simultaneously connected with one end of the capacitor C3 and the pin No. 3 of the amplifier U2A, the other end of the capacitor C3 is grounded, the pin No. 2 of the amplifier U A is simultaneously connected with one end of the pin R5475 and one end of the resistor R8, the other end of the resistor R7 is grounded, and the pin No. 1 of the amplifier U2A is connected with the other end of the resistor R8 and the other end of the capacitor C2 at the same time and outputs signals.
In a further embodiment, the amplification module comprises: the circuit comprises an amplifier U3A, an amplifier U3B, a resistor R14, a capacitor C6, a capacitor C5, a resistor R15, a resistor R16, a polar capacitor C7, a resistor R17, a capacitor C9, a resistor R19, a polar capacitor C8, a resistor R18, a resistor R23, a resistor R22 and a capacitor C10.
In a further embodiment, pin No. 2 of the amplifier U3A is connected to one end of the resistor R15 and one end of the capacitor C5, the other end of the capacitor C5 is connected to one end of the capacitor C6 and one end of the resistor R14, and a signal is input thereto, pin No. 3 of the amplifier U3A is connected to one end of the resistor R17, one end of the capacitor C9 and one end of the resistor R15, the other end of the resistor R15 is connected to one end of the polar capacitor C7, the other end of the capacitor C6 is connected to one end of the resistor R14 and the other end of the resistor R16, pin No. 4 of the amplifier U3A is connected to the other end of the resistor R16 and the other end of the polar capacitor C7, pin No. 1 of the amplifier U3A is connected to the other end of the capacitor C9, the other end of the resistor R17 and the other end of the resistor R19, one end of the resistor R19 is connected to one end of the polar capacitor C8, the pin No. 5 of the amplifier U3B is connected to the other end of the polar capacitor C8, one end of the resistor R22 and one end of the capacitor C10 at the same time, the pin No. 6 of the amplifier U3B is connected to one end of the resistor R18 and one end of the resistor R23 at the same time, the other end of the resistor R18 is connected to the other end of the polar capacitor C7 and the pin No. 4 of the amplifier U3B at the same time, the pin No. 7 of the amplifier U3B is connected to the other end of the capacitor C10 and the other end of the resistor R22 at the same time and outputs a signal, the other end of the resistor R23 is connected to the pin No. 11 of the amplifier U3A and the pin No. 11 of the amplifier U3B at the same time, the pin No. 11 of the amplifier U3A inputs a reference voltage, and the pin No. 11 of the amplifier U3B inputs an operating voltage.
A method of equalizing delay, comprising:
and 4, setting stable transmission rate delay.
In a further embodiment, in the process of transmitting and receiving signals, a channel model is established through channel measurement, so that the maximum information quantity and transmission quality which can be transmitted in a transmittable channel can be obtained; the method comprises the following specific steps:
step 101, sending a plurality of pseudo-random codes to a channel through a transmitter to serve as detection signals S1, S2 and S3.. SN;
step 102, ensuring that the detection signal does not generate an aliasing phenomenon at a receiving end, and ensuring that the repetition period of the detection signal is less than the channel change time and must be greater than the maximum multipath of the channel; thus, it follows:
wherein Tsn represents a repetition period of each detection signal;
fmax denotes the sampling rate of each probe signal in the channel;
zmax represents the maximum multipath of the channel;
103, when the detection signal meets the condition of the step 102, receiving the detection signal through a receiver;
104, extracting the change process of the signal detection signal in the channel;
105, extracting a pseudo-random code sequence in the detection signal by the receiving system, and sequencing the pseudo-random code sequence and a local sequence to extract a correlation value;
step 106, judging whether the extracted correlation value has a maximum value; when the maximum value exists, the received signal and the transmitted signal are the same sequence; otherwise, the result is not;
step 107, extracting channel impact response from the pseudo-random sequence code of the same sequence in the step 106;
108, extracting channel weakening characteristics according to channel impact response;
step 109, because the path loss and shadow attenuation problems existing between the transmitter and the receiver can cause the intensity change of the signal in the channel (in the actual process, shadow attenuation is a shadow effect caused by the obstruction of obstacles in the transmission path, and the number of the obstacles cannot be accurately judged, so that only the path loss is calculated), and the path loss is obtained according to the power of the transmitter and the power of the receiver:
wherein P1 represents the transmitter power;
p2 denotes receiver power;
p represents a path loss;
and when the performance test of the channel is finished, calculating to obtain the path loss P, and balancing the channel frequency according to the path loss.
In a further embodiment, when the path loss in the channel is too large, the frequency and amplitude phase errors inside the channel become large, thereby causing channel mismatch, so that a channel frequency equalization channel needs to be established, and the specific steps are as follows:
step 201, establishing an ideal channel; n transmission channels are provided, and an equalizer with frequency response B is added into each transmission channel, wherein the frequency response of each channel is K; the frequency response of the equalization channel can thus be derived as:
JN＝N*(B*K)N＝1,2,3,…,N
JN represents the frequency response of the channel after the equalizer is added;
step 202, when the frequency response of each channel after the equalizer is added and the frequency response of the ideal channel are in a fluctuable error range, the realization of the equalization channel is completed;
step 203, after the implementation of the equalization channel is completed, the module will perform equalization channel detection; namely, the mismatch ratio of the equalization channel at this time is calculated as follows:
in the formula, DN represents the mismatch rate of the equalization channel;
c represents the frequency response of the reference channel;
depending on the mismatch ratio, the amplitude and phase of the channel at that time are thus related, so that it can be further derived:
in the formula, A is amplitude mismatch rate, and E is phase mismatch rate;
therefore, the equalizer is added in the channel to realize equalization, and the mismatch rate of the channel can be greatly reduced.
In a further embodiment, after the channel is balanced, mutual balance and stability among the channel, the load and the system are required to be established, so that the stability of transmission is ensured; the method comprises the steps of establishing a control network in a channel transmission network, arranging a plurality of controllers in each control network, arranging a plurality of nodes in each control network, sequencing all nodes in the network, selecting the largest node, and setting a node root, so that a tree-shaped development structure is selected for sequencing to generate a node range, further the working range of the control network is determined, arranging a switch in each control network, wherein the switch is used for carrying out connection transmission with other control networks, and further determining the mapping relation between the controllers and the switches according to the detected limiting conditions in the channel performance test, thereby ensuring the normal operation of the transmission network.
In a further embodiment, the controller in each control network correspondingly controls one area, the range of the corresponding control area of each controller is further determined according to the distance between the switch and the controller, the control area of the overlapping switch is determined according to the area of the corresponding control area of each controller, and the area controlled by the switch is further adjusted according to the control area of the overlapping switch, so that the balanced channel control network for signal transmission is determined.
In a further embodiment, setting stable transmission delay and control according to the implementation of the determined control network and equalization channel, firstly recording the time T1 for sending a detection signal from the transmitter, when the time for receiving by the receiver is T2, when the time for inputting the signal into the system is T3, the time for converting the signal into a PWM wave is T4, when the signal is transmitted each time, the system automatically delays for a period of time T5, and the time for outputting the PWM wave is T6; the time T3 for inputting signals into the system is based on the signals, so that the time delay T5 for signal transmission is reduced, and the time T4 for converting the signals into PWM waves inside the system is reduced, so that the time for transmitting the signals from the transmitter needs to be shortened, the conversion time T4 can be effectively shortened, the time delay is shortened, and the signals can be output more quickly through a filter circuit when the PWM signals are output.
The working principle is as follows: when a transmission signal is received and transmitted, a system sends a plurality of pseudo-random codes to a channel to serve as a detection signal, the maximum information amount and the transmission quality which can be transmitted in the channel are detected, and meanwhile, when path loss in the channel is overlarge, frequency and amplitude phase errors in the channel become large, so that channel mismatching is caused, a channel frequency balancing channel needs to be established, after the balancing channel is realized, mutual balance and stability among the channel, a load and the system need to be established, and therefore transmission stability is guaranteed; namely, a control network is established in the channel transmission network; setting stable transmission delay and control according to the realization of the determined control network and the determined equalization channel, so that a transmission signal is transmitted through a transmitter, is output through a very delay module, is received through a receiver, and is converted into a PWM wave through a system for output;
the output PWM wave signal is subjected to waveform detection through a detection mode, the signal is protected by a resistor R3 and is input to an amplifier U1A, a detection circuit consisting of an amplifier U1A, an amplifier U2B and an amplifier U2A detects the input PWM signal, meanwhile, working voltage is protected and input through a resistor R9, a collector of a triode Q1 is conducted at the moment to output voltage to a transistor Q2, the transistor Q2 is connected with the amplifier U1B to input the working voltage, the detected signal is output to an amplification module through a pin 1 of the amplifier U2A, and the signal is amplified and output through a primary amplification circuit and a secondary amplification circuit consisting of an amplifier U3A and an amplifier U3B in the amplification module.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. The invention is not described in detail in order to avoid unnecessary repetition.
Claims (9)
1. A method for equalizing delay, comprising:
step 1, carrying out a data transceiving channel performance test, and establishing a channel model through channel measurement in the process of transmitting and receiving signals; when the performance test of the channel is finished, calculating to obtain path loss P, and balancing the channel frequency according to the path loss;
step 2, establishing a channel frequency equalization channel,
step 3, establishing a control network for an equalization channel for signal transmission;
step 4, setting stable transmission rate delay; when the path loss in the channel is too large, the frequency and amplitude phase errors inside the channel become large, and the channel is mismatched, so that a channel frequency equalization channel needs to be established, and the specific steps are as follows:
step 201, establishing an ideal channel; n transmission channels are provided, an equalizer with frequency response B is added in each transmission channel, and the frequency response of each transmission channel is K; the frequency response of the added equalizer channel can thus be found to be:
JN＝N*(B*K) N＝1,2,3,…,N
JN represents the frequency response of the channel after the equalizer is added;
step 202, when the frequency response of each channel after the equalizer is added and the frequency response of the ideal channel are in a fluctuable error range, the realization of the equalization channel is completed;
step 203, after the implementation of the equalization channel is completed, the module will perform equalization channel detection; namely, the mismatch ratio of the equalization channel at this time is calculated as follows:
in the formula, DN represents the mismatch rate of the equalization channel;
c represents the frequency response of the ideal channel;
therefore, according to the relation between the mismatch ratio and the amplitude and the phase of the channel at the moment, the following can be further obtained:
in the formula, A is amplitude mismatch rate, and E is phase mismatch rate;
therefore, the equalizer is added in the channel to realize equalization, and the mismatch rate of the channel can be greatly reduced.
2. The method for equalizing delay according to claim 1, characterized in that the specific steps are as follows:
step 101, sending a plurality of pseudo random codes to a channel through a transmitter as detection signals S1, S2 and S3 … SN;
step 102, ensuring that the detection signal does not generate an aliasing phenomenon at a receiving end, and ensuring that the repetition period of the detection signal is less than the channel change time and must be greater than the maximum multipath of the channel; thus, it follows:
wherein Tsn represents a repetition period of each detection signal;
fmax denotes the sampling rate of each probe signal in the channel;
zmax represents the maximum multipath of the channel;
103, when the detection signal meets the condition of the step 102, receiving the detection signal through a receiver;
104, extracting the change process of the detection signal in the channel;
105, extracting a pseudo-random code sequence in the detection signal by the receiving system, and sequencing the pseudo-random code sequence and a local sequence to extract a correlation value;
step 106, judging whether the extracted correlation value has a maximum value; when the maximum value exists, the received signal and the transmitted signal are the same sequence; otherwise, the result is not;
step 107, extracting channel impact response from the pseudo-random sequence code of the same sequence in the step 106;
108, extracting channel weakening characteristics according to channel impact response;
in step 109, the strength of the signal in the channel may change due to the path loss and shadow attenuation between the transmitter and the receiver, where the path loss is obtained according to the transmitter power and the receiver power, and is specifically represented by the following formula:
wherein P1 represents the transmitter power;
p2 denotes receiver power;
p represents the path loss;
and when the performance test of the channel is finished, calculating to obtain the path loss P, and balancing the channel frequency according to the path loss.
3. The method according to claim 1, wherein after the equalization of the channel, the mutual balance and stability between the channel, the load and the system are required to be established, so as to ensure the stability of transmission; the method comprises the steps of establishing a control network in a channel transmission network, arranging a plurality of controllers in each control network, arranging a plurality of nodes in each control network, sequencing all nodes in the network, selecting the largest node, and setting a node root, so that a tree-shaped development structure is selected for sequencing to generate a node range, further the working range of the control network is determined, arranging a switch in each control network, wherein the switch is used for carrying out connection transmission with other control networks, and further determining the mapping relation between the controllers and the switches according to the detected limiting conditions in the channel performance test, thereby ensuring the normal operation of the transmission network.
4. The method according to claim 3, wherein the controller in each control network controls a corresponding area, and the range of the corresponding control area of each controller is determined according to the distance between the switch and the controller; and determining a control area of the overlapped switch according to the corresponding control area of each controller, and further adjusting the area controlled by the switch according to the control area of the overlapped switch, thereby determining the balanced channel control network for signal transmission.
5. The equalizing delay method according to claim 1, wherein stable transmission delay and control are set according to the implementation of the determined control network and equalizing channel, and the time T1 when a probe signal is transmitted from the transmitter is recorded, the time T2 when the receiver receives the probe signal, the time T3 when the probe signal is input to the system, the time T4 when the probe signal is converted into a PWM wave are recorded, and the system automatically delays for a period of time T5 and outputs the PWM wave for a period of time T6 when the probe signal is transmitted; based on the size of the time T3 for inputting the signal into the system, the delay time T5 for signal transmission is shortened, and the time T4 for converting the signal into a PWM wave inside the system is shortened.
6. A transceiving frequency conversion channel system for implementing the equalizing delay method according to any one of claims 2 to 5, comprising: the device comprises a transmitter, a receiver, a balanced delay module, a detection module and an amplification module;
the balanced delay module is used for realizing the stability and the emission delay of a frequency conversion channel;
the amplifying module is used for amplifying the time output signal;
and the detection module is used for detecting the waveform of the output signal.
7. The transceiving frequency conversion channel system according to claim 6, wherein the equalization delay module comprises a filter circuit; the filter circuit includes: the filter U4, the resistor R21, the capacitor C12, the capacitor C11, the resistor R24, the resistor R20 and the amplifier U5A; the input signal of pin 3 of the filter U4, the input voltage of pin 5 of the filter U4, pin 6 of the filter U4 is connected with one end of the resistor R21, pin 7 of the filter U4 is connected with the other end of the resistor R21 and grounded, pin 4 of the filter U4 is connected with pin 1 and simultaneously connected with one end of the capacitor C11, one end of the resistor R20 and one end of the resistor R24, the voltage is input at the other end of the resistor R24, pin 2 of the filter U4 is simultaneously connected with the other end of the capacitor C11 and the other end of the resistor R20, pin 8 of the filter U4 is connected with pin 3 of the amplifier U5A, and pin 2 of the amplifier U5A is connected with pin 1 and outputs a signal.
8. The transceive frequency-converted channel system of claim 6, wherein the wave detection module comprises: the amplifier U1A, the amplifier U1B, the amplifier U2A, the resistor R3, the resistor R1, the resistor R2, the resistor R4, the capacitor C4, the resistor R5, the resistor R6, the capacitor C2, the capacitor C3, the resistor R7, the resistor R8, the capacitor C1, the transistor Q1, the resistor R13, the resistor R12, the voltage regulator tube D2, the transistor Q2, the resistor R11, the voltage regulator tube D1, the resistor R10 and the resistor R9;
one end of the resistor R3 is connected with a pin No. 3 of the amplifier U1A and inputs a signal, the other end of the resistor R3 is grounded, a pin No. 2 of the amplifier U1A is connected with a pin No. 1 and is simultaneously connected with one end of the resistor R1 and one end of the resistor R2, a pin No. 6 of the amplifier U1B is simultaneously connected with the other end of the resistor R1, one end of the resistor R4 and one end of the capacitor C4, a pin No. 5 of the amplifier U1B is simultaneously connected with the other end of the resistor R2, one end of the capacitor C1 and one end of the transistor Q2, a drain of the transistor Q2 is connected with the other end of the capacitor C1 and is grounded, a gate of the transistor Q2 is simultaneously connected with one end of the resistor R13 and an anode of the stabilivolt D2, the other end of the resistor R13 is grounded, a cathode of the stabilivolt D2 is simultaneously connected with one end of the resistor R12 and a collector of the transistor Q1, the other end of the resistor R12 is grounded, the emitter of the transistor Q1 is connected with one end of the resistor R10, the cathode of the regulator tube D1 and one end of the resistor R11 at the same time, the other end of the resistor R11 is inputted with voltage, the anode of the regulator tube D1 is grounded, the gate of the transistor Q1 is connected with the other end of the resistor R10 and one end of the resistor R9 at the same time, the other end of the resistor R9 is inputted with operating voltage, the pin No. 7 of the amplifier U1B is connected with the other end of the resistor R4, the other end of the capacitor C4 and one end of the resistor R5 at the same time, the other end of the resistor R5 is connected with one end of the resistor R6 and one end of the capacitor C2 at the same time, the other end of the resistor R6 is connected with one end of the capacitor C3 and the pin No. 3 of the amplifier U2A at the same time, the other end of the capacitor C3 is grounded, the pin No. 2 of the amplifier U2A is connected with one end of the resistor R7 and one end of the resistor R8 at the same time, the other end of the resistor R7 is grounded, and the pin No. 1 of the amplifier U2A is connected with the other end of the resistor R8 and the other end of the capacitor C2 at the same time and outputs signals.
9. The system according to claim 6, wherein the amplifying module comprises: the circuit comprises an amplifier U3A, an amplifier U3B, a resistor R14, a capacitor C6, a capacitor C5, a resistor R15, a resistor R16, a polar capacitor C7, a resistor R17, a capacitor C9, a resistor R19, a polar capacitor C8, a resistor R18, a resistor R23, a resistor R22 and a capacitor C10;
pin 2 of the amplifier U3A is connected to one end of the resistor R15 and one end of the capacitor C5, the other end of the capacitor C5 is connected to one end of the capacitor C6 and one end of the resistor R14, and a signal is input, pin 3 of the amplifier U3A is connected to one end of the resistor R17, one end of the capacitor C9 and one end of the resistor R15, the other end of the resistor R15 is connected to one end of the polarity capacitor C7, the other end of the capacitor C6 is connected to one end of the resistor R14 and the other end of the resistor R16, and ground, pin 4 of the amplifier U3A is connected to the other end of the resistor R16 and the other end of the polarity capacitor C7, pin 1 of the amplifier U3A is connected to the other end of the capacitor C9, the other end of the resistor R17 and one end of the resistor R19, and the other end of the resistor R19 is connected to one end of the polarity capacitor C8, the No. 5 pin of the amplifier U3B is connected to the other end of the polar capacitor C8, one end of the resistor R22 and one end of the capacitor C10, the No. 6 pin of the amplifier U3B is connected to one end of the resistor R18 and one end of the resistor R23, the other end of the resistor R18 is connected to the other end of the polar capacitor C7 and the No. 4 pin of the amplifier U3B, the No. 7 pin of the amplifier U3B is connected to the other end of the capacitor C10 and the other end of the resistor R22, the other end of the resistor R23 is connected to the No. 11 pin of the amplifier U3A and the No. 11 pin of the amplifier U3B, the No. 11 pin of the amplifier U3A inputs the reference voltage, and the No. 11 pin of the amplifier U3B inputs the working voltage.
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| CN1553588A (en) * | 2003-06-05 | 2004-12-08 | 中兴通讯股份有限公司 | Self-adaptation balancing apparatus for SDH transmission system circuit attenuation compensation |
| CN110505020A (en) * | 2019-07-15 | 2019-11-26 | 电子科技大学 | Optical nonlinear equalization methods based on transfer learning |
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| CN1553588A (en) * | 2003-06-05 | 2004-12-08 | 中兴通讯股份有限公司 | Self-adaptation balancing apparatus for SDH transmission system circuit attenuation compensation |
| CN110505020A (en) * | 2019-07-15 | 2019-11-26 | 电子科技大学 | Optical nonlinear equalization methods based on transfer learning |
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