CN112466992A - Tellurium-cadmium-mercury infrared detector chip and preparation method thereof - Google Patents
Tellurium-cadmium-mercury infrared detector chip and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- MARUHZGHZWCEQU-UHFFFAOYSA-N 5-phenyl-2h-tetrazole Chemical compound C1=CC=CC=C1C1=NNN=N1 MARUHZGHZWCEQU-UHFFFAOYSA-N 0.000 claims abstract description 90
- 239000000758 substrate Substances 0.000 claims abstract description 70
- 229910000661 Mercury cadmium telluride Inorganic materials 0.000 claims abstract description 50
- MCMSPRNYOJJPIZ-UHFFFAOYSA-N cadmium;mercury;tellurium Chemical compound [Cd]=[Te]=[Hg] MCMSPRNYOJJPIZ-UHFFFAOYSA-N 0.000 claims abstract description 48
- 239000002131 composite material Substances 0.000 claims abstract description 36
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 33
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 33
- 239000010703 silicon Substances 0.000 claims abstract description 33
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- 238000007872 degassing Methods 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 41
- 230000008569 process Effects 0.000 claims description 24
- 238000000407 epitaxy Methods 0.000 claims description 21
- 238000011065 in-situ storage Methods 0.000 claims description 21
- 238000005516 engineering process Methods 0.000 claims description 12
- 238000002161 passivation Methods 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 6
- 230000003213 activating effect Effects 0.000 claims description 4
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 4
- 239000006096 absorbing agent Substances 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 description 28
- 230000004913 activation Effects 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
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Abstract
The invention discloses a tellurium-cadmium-mercury infrared detector chip and a preparation method thereof. The preparation method of the mercury cadmium telluride infrared detector chip comprises the following steps: sequentially performing degassing treatment and beam current correction on the silicon substrate layer; epitaxially growing a cadmium telluride composite substrate layer on the silicon substrate layer after beam current correction; epitaxially growing a p-type doped high-conductivity cadmium telluride conductive layer on the cadmium telluride composite substrate layer; and epitaxially growing a mercury cadmium telluride absorption layer on the p-type doped high-conductivity cadmium telluride conductive layer. The mercury cadmium telluride infrared detector chip comprises: a silicon substrate layer; the cadmium telluride composite substrate layer is arranged on the silicon substrate layer in a laminated mode; the p-type doped high-conductivity cadmium telluride conductive layer is arranged on the cadmium telluride composite substrate layer in a laminated mode; and the mercury cadmium telluride absorption layer is arranged on the p-type doped high-conductivity cadmium telluride conductive layer in a stacking manner. By adopting the invention, the uniformity index of the infrared focal plane detector chip can be effectively improved.
Description
Technical Field
The invention relates to the field of infrared detectors, in particular to a mercury cadmium telluride infrared detector chip and a preparation method thereof.
Background
At present, the infrared focal plane detector is developing towards the field of the third generation focal plane detector with large area array and double multi-color. The mercury cadmium telluride material occupies an absolute market share in the application of the field due to the quantum efficiency close to 100 percent and the extremely wide application range from near infrared to very long wave full wave band. With the continuous expansion of the application of the material in the fields of aerospace, meteorological observation and the like, the requirements on the performance of the material are also continuously improved.
In the preparation process of the mercury cadmium telluride infrared detector, a back-illuminated type is generally adopted, namely infrared rays radiated by a detected object enter a detector absorption layer through one side of a substrate material, and generated electron-hole pairs are captured by a p-n depletion region junction to generate electric signals and are read by a reading circuit. The p-n junction of the chip works in a reverse bias region, a positive voltage is applied to an n-type layer on the surface of the chip, and a negative voltage is annularly applied to a p-type layer through the periphery of the chip. Due to the difference in the body resistance of the center region and the edge region of the chip, the actual junction voltage of the center region is smaller than that of the edge region, which is reflected in the imaging signal. For second generation medium and short wave components, the difference is below 5%, which can be generally ignored; however, for the third generation large-area array and ultra-large-area array tellurium-cadmium-mercury infrared detector, the difference can reach 10% or even more, which causes the non-uniformity of the component to be obviously degraded; and the influence of infrared illumination is superposed, so that the inherent non-uniformity of the assembly reaches more than 18-20 percent.
Disclosure of Invention
The embodiment of the invention provides a mercury cadmium telluride infrared detector chip and a preparation method thereof, which are used for solving the problem of uneven bias voltage of a center-edge area of the chip in the prior art.
The preparation method of the mercury cadmium telluride infrared detector chip according to the embodiment of the invention comprises the following steps:
sequentially performing degassing treatment and beam current correction on the silicon substrate layer;
epitaxially growing a cadmium telluride composite substrate layer on the silicon substrate layer after beam current correction;
epitaxially growing a p-type doped high-conductivity cadmium telluride conductive layer on the cadmium telluride composite substrate layer;
and epitaxially growing a mercury cadmium telluride absorption layer on the p-type doped high-conductivity cadmium telluride conductive layer.
According to some embodiments of the invention, the silicon-based substrate layer is cleaned prior to sequentially performing the degassing treatment and the beam current correction on the silicon-based substrate layer.
According to some embodiments of the invention, the sequentially degassing the silicon substrate layer comprises:
placing the silicon-based substrate layer in molecular beam epitaxy equipment, and adjusting the temperature of a source furnace of the molecular epitaxy equipment to an estimated temperature;
after the silicon substrate layer is subjected to high-temperature degassing for a preset time period, adjusting the temperature of a source furnace of the molecular epitaxy equipment to an estimated temperature;
the estimated temperature is more than or equal to 18 ℃ and less than or equal to 25 ℃;
the preset time period is greater than or equal to 25 minutes and less than or equal to 35 minutes.
According to some embodiments of the invention, the epitaxially growing a p-type doped high conductivity cadmium telluride conductive layer on the cadmium telluride composite substrate layer comprises:
epitaxially growing a p-type doped high-conductivity cadmium telluride conductive layer on the cadmium telluride composite substrate layer by an in-situ doping technology;
the thickness of the p-type doped high-conductivity cadmium telluride conductive layer is more than or equal to 300 nanometers and less than or equal to 500 nanometers;
the effective doping concentration of the p-type doped high-conductivity cadmium telluride conductive layer is more than or equal to 1.0 multiplied by 1017。
According to some embodiments of the invention, the p-type doped high conductivity cadmium telluride conductive layer is epitaxially completed with the cadmium telluride composite substrate layer in one pass.
According to some embodiments of the invention, an annealing process is performed before the p-type doped high-conductivity cadmium telluride conductive layer is epitaxially grown on the cadmium telluride composite substrate layer and after the mercury cadmium telluride absorption layer is epitaxially grown on the p-type doped high-conductivity cadmium telluride conductive layer.
According to some embodiments of the invention, the method further comprises:
and epitaxially growing a cadmium telluride in-situ passivation layer on the mercury cadmium telluride absorption layer.
According to some embodiments of the invention, the method further comprises:
and carrying out a p-type conversion process on the tellurium-cadmium-mercury absorption layer, and activating the p-type doped high-conductivity tellurium-cadmium-telluride electric layer.
The tellurium-cadmium-mercury infrared detector chip provided by the embodiment of the invention comprises the following components:
a silicon substrate layer;
the cadmium telluride composite substrate layer is arranged on the silicon substrate layer in a laminated mode;
the p-type doped high-conductivity cadmium telluride conductive layer is arranged on the cadmium telluride composite substrate layer in a laminated mode;
and the mercury cadmium telluride absorption layer is arranged on the p-type doped high-conductivity cadmium telluride conductive layer in a laminated manner.
According to some embodiments of the invention, the mercury cadmium telluride infrared detector chip further comprises:
and the cadmium telluride in-situ passivation layer is arranged on the mercury cadmium telluride absorption layer in a stacking manner.
By adopting the embodiment of the invention, the uniformity index of the infrared focal plane detector chip can be effectively improved, the center-edge level difference of the infrared focal plane detector chip is within the range of 10-15% compared with the center-edge level difference of the infrared detector chip with the oversized area array in the prior art, the center-edge level difference of the infrared detector chip with the oversized area array is below 5%, and the yield and the material utilization rate of the infrared detector chip are greatly improved. And the cadmium telluride material epitaxy and in-situ doping technology has relatively low difficulty compared with the mercury cadmium telluride material epitaxy and in-situ doping technology, and can relatively easily realize higher-concentration doping and impurity activation, so that the process difficulty is relatively lower compared with the process difficulty of realizing a high-conductivity layer by high-doping mercury cadmium telluride.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. In the drawings:
FIG. 1 is a schematic diagram of a method for manufacturing a HgCdTe infrared detector chip in an embodiment of the invention;
FIG. 2 is a schematic structural diagram of a HgCdTe infrared detector chip in the embodiment of the invention.
Detailed Description
Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
As shown in fig. 1, the method for manufacturing a mercury cadmium telluride infrared detector chip according to an embodiment of the present invention includes:
s1, sequentially performing degassing treatment and beam current correction on the silicon substrate layer;
s2, epitaxially growing a cadmium telluride composite substrate layer on the silicon substrate layer after beam current correction;
s3, epitaxially growing a p-type doped high-conductivity cadmium telluride conductive layer on the cadmium telluride composite substrate layer; it can be understood that the p-type doped high conductivity cadmium telluride conductive layer is epitaxially grown on the side of the cadmium telluride composite substrate layer away from the silicon-based substrate layer.
S4, epitaxially growing a mercury cadmium telluride absorption layer on the p-type doped high-conductivity cadmium telluride conducting layer. It can be understood that the mercury cadmium telluride absorbing layer is epitaxially grown on the side of the p-type doped high conductivity cadmium telluride conductive layer away from the cadmium telluride composite substrate layer.
By adopting the embodiment of the invention, the uniformity index of the infrared focal plane detector chip can be effectively improved, the center-edge level difference of the infrared focal plane detector chip is within the range of 10-15% compared with the center-edge level difference of the infrared detector chip with the oversized area array in the prior art, the center-edge level difference of the infrared detector chip with the oversized area array is below 5%, and the yield and the material utilization rate of the infrared detector chip are greatly improved. And the cadmium telluride material epitaxy and in-situ doping technology has relatively low difficulty compared with the mercury cadmium telluride material epitaxy and in-situ doping technology, and can relatively easily realize higher-concentration doping and impurity activation, so that the process difficulty is relatively lower compared with the process difficulty of realizing a high-conductivity layer by high-doping mercury cadmium telluride.
On the basis of the above-described embodiment, various modified embodiments are further proposed, and it is to be noted herein that, in order to make the description brief, only the differences from the above-described embodiment are described in the various modified embodiments.
According to some embodiments of the invention, the silicon-based substrate layer is cleaned prior to sequentially performing the degassing treatment and the beam current correction on the silicon-based substrate layer.
According to some embodiments of the invention, the sequentially degassing the silicon substrate layer comprises:
placing the silicon-based substrate layer in molecular beam epitaxy equipment, and adjusting the temperature of a source furnace of the molecular epitaxy equipment to an estimated temperature;
after the silicon substrate layer is subjected to high-temperature degassing for a preset time period, adjusting the temperature of a source furnace of the molecular epitaxy equipment to an estimated temperature;
the estimated temperature is more than or equal to 18 ℃ and less than or equal to 25 ℃; for example, the estimated temperature may be set to 20 ℃.
The preset time period is greater than or equal to 25 minutes and less than or equal to 35 minutes. For example, the first preset time period may be set to 30 minutes.
According to some embodiments of the invention, the epitaxially growing a p-type doped high conductivity cadmium telluride conductive layer on the cadmium telluride composite substrate layer comprises:
epitaxially growing a p-type doped high-conductivity cadmium telluride conductive layer on the cadmium telluride composite substrate layer by an in-situ doping technology;
the thickness of the p-type doped high-conductivity cadmium telluride conductive layer is more than or equal to 300 nanometers and less than or equal to 500 nanometers;
the effective doping concentration of the p-type doped high-conductivity cadmium telluride conductive layer is more than or equal to 1.0 multiplied by 1017。
According to some embodiments of the invention, the p-type doped high conductivity cadmium telluride conductive layer is epitaxially completed with the cadmium telluride composite substrate layer in one pass. Thus, chip center-edge region bias uniformity may be achieved.
According to some embodiments of the invention, an annealing process is performed before the p-type doped high-conductivity cadmium telluride conductive layer is epitaxially grown on the cadmium telluride composite substrate layer and after the mercury cadmium telluride absorption layer is epitaxially grown on the p-type doped high-conductivity cadmium telluride conductive layer.
According to some embodiments of the invention, the method further comprises:
and epitaxially growing a cadmium telluride in-situ passivation layer on the mercury cadmium telluride absorption layer. It can be understood that a cadmium telluride in-situ passivation layer is epitaxially grown on the side of the mercury cadmium telluride absorber layer away from the high conductivity cadmium telluride conductive layer.
According to some embodiments of the invention, the method further comprises:
and carrying out a p-type conversion process on the tellurium-cadmium-mercury absorption layer, and activating the p-type doped high-conductivity tellurium-cadmium-telluride electric layer.
In some embodiments of the present invention, the composition of the p-type doped high conductivity tellurium-cadmium-telluride electrical layer is the same or substantially the same as the composition of the tellurium-cadmium-mercury absorber layer to ensure impurity doping and activation efficiency.
According to some embodiments of the invention, the manufacturing method of the mercury cadmium telluride infrared detector chip is suitable for a large-area array double-multicolor third-generation focal plane detector.
As shown in fig. 2, a mercury cadmium telluride infrared detector chip 1 according to an embodiment of the present invention includes:
a silicon-based substrate layer 11;
a cadmium telluride composite substrate layer 12 which is arranged on the silicon substrate layer 11 in a laminated mode;
a p-type doped high conductivity cadmium telluride conductive layer 20 layered on the cadmium telluride composite substrate layer 12;
and the mercury cadmium telluride absorption layer 30 is arranged on the p-type doped high-conductivity cadmium telluride conductive layer 20 in a laminated manner.
By adopting the embodiment of the invention, the uniformity index of the infrared focal plane detector chip 1 can be effectively improved, the center-edge level difference of the infrared focal plane detector chip 1 and the oversized area array infrared detector chip in the prior art is within the range of 10% -15%, the center-edge level difference of the infrared focal plane detector chip in the embodiment of the invention is below 5%, and the yield of the chip and the utilization rate of materials are greatly improved. And the cadmium telluride material epitaxy and in-situ doping technology has relatively low difficulty compared with the mercury cadmium telluride material epitaxy and in-situ doping technology, and can relatively easily realize higher-concentration doping and impurity activation, so that the process difficulty is relatively lower compared with the process difficulty of realizing a high-conductivity layer by high-doping mercury cadmium telluride.
According to some embodiments of the invention, the mercury cadmium telluride infrared detector chip further comprises:
and the cadmium telluride in-situ passivation layer is arranged on the mercury cadmium telluride absorption layer in a stacking manner.
The mercury cadmium telluride infrared detector chip and the preparation method thereof according to the embodiment of the invention are described in detail by a specific embodiment. It is to be understood that the following description is illustrative only and is not intended to be in any way limiting. All similar structures and similar variations thereof adopted by the invention are intended to fall within the scope of the invention.
The common solution is that several longitudinal and transverse deep grooves are etched on the surface of the material in the chip preparation process, and the deep grooves are led out through electrodes; by the method, the equivalent circuit divider resistance in the central area of the chip is reduced, and the reverse bias voltage uniformity of the comprehensive array diode is improved. However, for the ultra-large area array detector, along with the reduction of the center distance of the pixels, the reduction of the etching line width and the limitation of the material area, the method of etching the grid ground has the following defects: reduced duty cycle, relatively complex process, larger material area required, etc.
In order to solve the above problems, embodiments of the present invention provide a mercury cadmium telluride infrared detector chip, in which a p-type doped high conductivity cadmium telluride conductive layer is grown on a cadmium telluride composite substrate layer and under a mercury cadmium telluride absorption layer, and material preparation is completed in a material epitaxy process at one time, so that consistency of equivalent resistance of all pixels in a center-edge region is achieved, and further consistency of bias voltage is achieved.
In structural design, after the cadmium telluride composite substrate layer grows, a p-type doped high-conductivity cadmium telluride conducting layer with the thickness of 300-500 nm is subjected to epitaxy by an in-situ doping technology, and the effective doping concentration reaches 1.0 multiplied by 1017Therefore, the material body resistance is ensured to be smaller than the equivalent resistance of a subsequently prepared mercury cadmium telluride detector diode by one order of magnitude or more. And then high-temperature annealing is carried out to realize impurity activation and the improvement of the crystal quality and the surface quality of the composite substrate material. And then, carrying out tellurium-cadmium-mercury absorption layer epitaxy, wherein the process is the same as the common process.
The preparation method of the tellurium-cadmium-mercury infrared detector chip provided by the embodiment of the invention comprises the following steps:
step 1: raising the temperature of each source furnace of the molecular epitaxy equipment to about +20 ℃ of the estimated temperature, degassing for about 30 minutes, cooling to the estimated temperature, and performing beam current correction;
step 2: epitaxially growing a cadmium telluride composite substrate layer on the silicon substrate layer after beam current correction;
and step 3: after the epitaxy of the cadmium telluride composite substrate layer is finished, directly opening a doping source baffle to carry out p-type doped high-conductivity cadmium telluride conductive layer epitaxy;
and 4, step 4: after the growth is finished, annealing the material in situ according to an annealing process in the growth process of the cadmium telluride composite substrate layer, optimizing the crystal quality and the surface quality of the material, and activating doping atoms; simultaneously closing the doping source baffle;
and 5: carrying out molecular beam epitaxy process growth on the material of the mercury cadmium telluride absorption layer;
step 6: carrying out cadmium telluride in-situ passivation layer material epitaxy, and adjusting the growth time according to the required thickness of the passivation film;
and 7: the subsequent component preparation process is the same as the conventional process.
The embodiment of the invention has the beneficial effects that: 1. compared with an ultra-large area array component which is not optimized, the center-edge level difference of the chip is reduced to below 5% from 10% -15%; 2. compared with the scheme of preparing the grid ground optimization in the chip preparation process, the duty ratio is improved, the process difficulty is reduced, and the yield and the material utilization rate of the chip are improved; 3. because the difficulty of the cadmium telluride material epitaxy and the in-situ doping technology is relatively small compared with the mercury cadmium telluride material epitaxy and the in-situ doping technology, higher-concentration doping and impurity activation can be relatively easily realized, and the process difficulty is relatively lower compared with the process of realizing a high-conductivity layer by high-doping mercury cadmium telluride.
According to the preparation method of the mercury cadmium telluride super large area array focal plane component, the technical process is relatively simple, the technical steps are reduced, and the material utilization rate and the chip non-uniformity are improved.
It should be noted that the above-mentioned embodiments are only preferred embodiments of the present invention, and are not intended to limit the present invention, and those skilled in the art can make various modifications and changes. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
Claims (10)
1. A preparation method of a mercury cadmium telluride infrared detector chip is characterized by comprising the following steps:
sequentially performing degassing treatment and beam current correction on the silicon substrate layer;
epitaxially growing a cadmium telluride composite substrate layer on the silicon substrate layer after beam current correction;
epitaxially growing a p-type doped high-conductivity cadmium telluride conductive layer on the cadmium telluride composite substrate layer;
and epitaxially growing a mercury cadmium telluride absorption layer on the p-type doped high-conductivity cadmium telluride conductive layer.
2. The method of claim 1, wherein the silicon-based substrate layer is cleaned prior to the degassing and the beam current correction of the silicon-based substrate layer in sequence.
3. The method of claim 1, wherein the sequentially degassing the silicon-based substrate layer comprises:
placing the silicon-based substrate layer in molecular beam epitaxy equipment, and adjusting the temperature of a source furnace of the molecular epitaxy equipment to an estimated temperature;
after the silicon substrate layer is subjected to high-temperature degassing for a preset time period, adjusting the temperature of a source furnace of the molecular epitaxy equipment to an estimated temperature;
the estimated temperature is more than or equal to 18 ℃ and less than or equal to 25 ℃;
the preset time period is greater than or equal to 25 minutes and less than or equal to 35 minutes.
4. The method of claim 1, wherein epitaxially growing a p-type doped high conductivity cadmium telluride conductive layer on the cadmium telluride composite substrate layer comprises:
epitaxially growing a p-type doped high-conductivity cadmium telluride conductive layer on the cadmium telluride composite substrate layer by an in-situ doping technology;
the thickness of the p-type doped high-conductivity cadmium telluride conductive layer is more than or equal to 300 nanometers and less than or equal to 500 nanometers;
the effective doping concentration of the p-type doped high-conductivity cadmium telluride conductive layer is more than or equal to 1.0 multiplied by 1017。
5. The method of claim 1, wherein the p-type doped high conductivity cadmium telluride conductive layer is epitaxially grown on the cadmium telluride composite substrate layer in one pass.
6. The method of claim 1, wherein an annealing process is performed before the p-type doped high conductivity cadmium telluride conductive layer is epitaxially grown on the cadmium telluride composite substrate layer, after the mercury cadmium telluride absorber layer is epitaxially grown on the p-type doped high conductivity cadmium telluride conductive layer.
7. The method of claim 1, wherein the method further comprises:
and epitaxially growing a cadmium telluride in-situ passivation layer on the mercury cadmium telluride absorption layer.
8. The method of claim 1, wherein the method further comprises:
and carrying out a p-type conversion process on the tellurium-cadmium-mercury absorption layer, and activating the p-type doped high-conductivity tellurium-cadmium-telluride electric layer.
9. A mercury cadmium telluride infrared detector chip is characterized by comprising:
a silicon substrate layer;
the cadmium telluride composite substrate layer is arranged on the silicon substrate layer in a laminated mode;
the p-type doped high-conductivity cadmium telluride conductive layer is arranged on the cadmium telluride composite substrate layer in a laminated mode;
and the mercury cadmium telluride absorption layer is arranged on the p-type doped high-conductivity cadmium telluride conductive layer in a laminated manner.
10. The mercury cadmium telluride infrared detector chip as set forth in claim 9, further comprising:
and the cadmium telluride in-situ passivation layer is arranged on the mercury cadmium telluride absorption layer in a stacking manner.
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| US20120273838A1 (en) * | 2011-04-28 | 2012-11-01 | Kinch Michael A | MINORITY CARRIER BASED HgCdTe INFRARED DETECTORS AND ARRAYS |
| CN108998830A (en) * | 2018-08-06 | 2018-12-14 | 中国电子科技集团公司第十研究所 | A kind of passivating method of mercury cadmium telluride |
| CN110504384A (en) * | 2019-08-29 | 2019-11-26 | 京东方科技集团股份有限公司 | Organic electroluminescence device and display panel |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120273838A1 (en) * | 2011-04-28 | 2012-11-01 | Kinch Michael A | MINORITY CARRIER BASED HgCdTe INFRARED DETECTORS AND ARRAYS |
| CN108998830A (en) * | 2018-08-06 | 2018-12-14 | 中国电子科技集团公司第十研究所 | A kind of passivating method of mercury cadmium telluride |
| CN110504384A (en) * | 2019-08-29 | 2019-11-26 | 京东方科技集团股份有限公司 | Organic electroluminescence device and display panel |
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