CN112466891B

CN112466891B - Three-dimensional flash memory, control circuit and method for forming gate stack

Info

Publication number: CN112466891B
Application number: CN202010877035.9A
Authority: CN
Inventors: 吕函庭
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2019-09-09
Filing date: 2020-08-27
Publication date: 2024-08-23
Anticipated expiration: 2040-08-27
Also published as: CN112466891A

Abstract

A three-dimensional flash memory, a control circuit and a method for forming a gate stack are provided, wherein the three-dimensional flash memory comprises a gate stack structure with a plurality of gate layers electrically insulated from each other; a cylindrical channel pillar extending vertically through each gate layer of the gate stack, the cylindrical channel pillar having a cylindrical cross section; a first conductive pillar extending vertically through the gate stack, the first conductive pillar being located within and electrically connected to the cylindrical via pillar; and a second conductive pillar extending vertically through the gate stack, the second conductive pillar being located within and electrically connected to the cylindrical via pillar, the first conductive pillar and the second conductive pillar being separated from each other. The three-dimensional flash memory further comprises a ferroelectric layer arranged between the plurality of gate layers and the cylindrical channel pillars of the gate stack structure.

Description

Three-dimensional flash memory, control circuit and method for forming gate stack

Technical Field

The present invention relates to a three-dimensional flash memory, a control circuit, AND a method for forming a gate stack, AND more particularly, to a three-dimensional AND gate (AND) or three-dimensional exclusive-or gate (NOR) flash memory architecture AND control logic.

Background

Nonvolatile memory, such as flash memory, is widely used in personal computers and other electronic devices because it has the advantage that the stored data does not disappear after the computer and/or device is powered down.

As three-dimensional AND gate (AND) flash memory is increasingly used in electronic devices, smaller three-dimensional AND gate flash memory needs to be developed to achieve greater storage capacity in the electronic device, even though the electronic device itself becomes smaller. There is also a need to develop three-dimensional and gate flash memory that is more efficient and operates at higher speeds. The increased efficiency may allow battery operated electronic devices to operate longer in one charge and the increased speed may allow the electronic devices to operate faster.

It is therefore desirable to provide a smaller, more efficient and faster three-dimensional and gate flash memory architecture. The disclosed techniques achieve these features by forming cylindrical channel pillars and by implementing ferroelectric materials to form ferroelectric field effect transistors (Ferroelectric FIELD EFFECT Transistors, fefets). The cylindrical channel post may be oval, circular or some other shape.

Disclosure of Invention

The invention provides a three-dimensional flash memory. The three-dimensional flash memory comprises a gate stack structure, comprising a plurality of gate layers electrically insulated from each other; a cylindrical channel pillar extending vertically through each gate layer of the gate stack, the cylindrical channel pillar having a cylindrical cross section; a first conductive pillar extending vertically through the gate stack, the first conductive pillar being located within and electrically connected to the cylindrical via pillar; a second conductive pillar extending vertically through the gate stack, the second conductive pillar being located within and electrically connected to the cylindrical via pillar, the first conductive pillar and the second conductive pillar being separated from each other; and a ferroelectric layer disposed between the plurality of gate layers and the cylindrical channel pillars of the gate stack. The ferroelectric layer may be elliptical or circular or other types of shapes. The three-dimensional architecture structures described throughout may be implemented as three-dimensional AND gate (AND) or three-dimensional exclusive-or gate (NOR) devices. Although the present disclosure primarily describes three-dimensional AND gates (AND), the techniques of the present disclosure are not so limited AND may also be implemented as three-dimensional exclusive-or gate (NOR) devices.

According to one aspect of the disclosed technology, an insulating post is disposed within a cylindrical channel post and between a first conductive post and a second conductive post.

According to another aspect of the disclosed technology, a first embedded conductor is disposed horizontally under the gate stack and electrically connected to the first conductive pillar, and a second embedded conductor is disposed horizontally under the gate stack and electrically connected to the second conductive pillar.

Furthermore, in accordance with an aspect of the disclosed technique, the ferroelectric layer extends vertically through the gate stack structure.

In one aspect of the technology of the present disclosure, a ferroelectric layer is located on an upper surface and a lower surface of each of a plurality of gate layers.

In another aspect of the disclosed technology, the ferroelectric layer covers the outer surface of the cylindrical channel pillars.

Furthermore, in accordance with an aspect of the presently disclosed technology, the cylindrical channel column is continuous in the vertical direction.

According to one aspect of the disclosed technology, the ferroelectric layer comprises a ferroelectric HfO ₂ material.

In another aspect of the disclosed technology, a three-dimensional flash memory can include an insulator disposed between and extending along the length of a first conductive pillar and a second conductive pillar. The insulator separates the first conductive post and the second conductive post from each other.

In another aspect, a three-dimensional flash memory includes: a first embedded conductor disposed in the dielectric substrate and connected to the first conductive post; and a second embedded conductor disposed in the dielectric substrate and connected to the second conductive post. The control circuit is configured to perform a programming operation on the three-dimensional flash memory by: a voltage of approximately +5V to +8V is provided on a selected word line that is connected to a selected gate of the plurality of select gate layers. Providing a voltage of about 0V on a selected source line connected to a first embedded conductor within the cylindrical channel pillar, the first embedded conductor being connected to the first conductive pillar; and providing a voltage of about 0V on a selected bit line, the selected bit line being connected to a second buried conductor, the second buried conductor being connected to a second conductive pillar within the cylindrical via pillar.

In one aspect, a three-dimensional flash memory includes an insulator disposed between and extending along a length of a first conductive pillar and a second conductive pillar, the insulator separating the first conductive pillar and the second conductive pillar from each other.

In another aspect, a three-dimensional flash memory includes a control circuit. The control circuit is configured to perform an erase operation on the three-dimensional flash memory by: providing a voltage of about-5V to-8V on a selected word line, the selected word line being connected to a selected gate layer of the plurality of gate layers; providing a voltage of about 0V on a selected source line connected to the first conductive pillar within the cylindrical channel pillar; and providing a voltage of about 0V on a selected bit line, the selected bit line being connected to the second conductive pillar within the cylindrical channel pillar.

In another aspect, the control circuit is further configured to perform an erase operation on the three-dimensional flash memory by: providing a voltage of about 0V to a plurality of unselected word lines connected to the plurality of gate layers except the selected gate layer; providing a voltage of approximately +0.5v to an unselected source line connected to the first conductive pillar within the second cylindrical channel pillar; and providing a voltage of approximately +0.5v to an unselected bit line, the unselected bit line being connected to the second source pillar within the second cylindrical channel pillar.

In one aspect, the three-dimensional flash memory further includes a second cylindrical channel pillar having the same structure and configuration as the cylindrical channel pillar; a third conductive pillar having the same structure and configuration as the first conductive pillar; a fourth conductive pillar having the same structure and configuration as the second conductive pillar. The control circuit is configured to perform a read operation on the three-dimensional flash memory by: providing a voltage of about +2v to +4v on a selected word line, the selected word line connected to a selected gate layer of the plurality of gate layers; providing a voltage of about 0V on a plurality of selected and unselected source lines connected to a first conductive pillar within the cylindrical channel pillar and to a third conductive pillar within the second cylindrical channel pillar; and providing a voltage of about +0.5V to +1.5V on a selected bit line, the selected bit line being connected to the first conductive pillar within the cylindrical channel pillar.

According to another aspect, the control circuit is further configured to perform this read operation on the three-dimensional flash memory by: providing a voltage of about 0V to-2V to a plurality of unselected word lines connected to a plurality of gate layers other than the selected gate layer; and providing a voltage of about 0V to a plurality of unselected bit lines connected to a fourth conductive pillar within the second cylindrical channel pillar.

Further, in another aspect, a control circuit is provided that is configured to program, erase, and read a three-dimensional flash memory. The three-dimensional flash memory includes: a gate stack structure including a plurality of gate layers electrically insulated from each other; a cylindrical channel pillar extending vertically through each gate layer of the gate stack, the cylindrical channel pillar having a cylindrical cross section; a first conductive pillar extending vertically through the gate stack, the first conductive pillar being located within and electrically connected to the cylindrical via pillar; a second conductive pillar extending vertically through the gate stack, the second conductive pillar being located within and electrically connected to the cylindrical via pillar, the first conductive pillar and the second conductive pillar being separated from each other; and a ferroelectric layer disposed between the plurality of gate layers and the cylindrical channel pillars of the gate stack. Further, the control circuitry is configured to perform various program, erase, and read operations by: providing various voltages to a selected word line connected to a selected gate layer of the gate stack of the three-dimensional flash memory; providing various voltages to a selected bit line, the selected bit line being connected to a second conductive pillar within a cylindrical channel pillar of the three-dimensional flash memory; and providing various voltages to a selected source line connected to the first conductive pillar within the cylindrical channel pillar of the three-dimensional flash memory.

In addition, a method of forming a gate stack including a dielectric layer and a ferroelectric layer is provided. The method comprises the following steps: forming a gate stack structure including a plurality of gate layers electrically insulated from each other; forming a cylindrical channel column extending vertically through each gate layer of the gate stack, the cylindrical channel column having a cylindrical cross section; forming a first conductive pillar extending vertically through the gate stack, the first conductive pillar being located within and electrically connected to the cylindrical via pillar; forming a second conductive pillar extending vertically through the gate stack, the second conductive pillar being located within and electrically connected to the cylindrical via pillar; forming an insulating column which is arranged in the cylindrical channel column and between the first conductive column and the second conductive column; and forming a ferroelectric layer arranged between the plurality of gate layers of the gate stack structure and the cylindrical channel columns.

According to an aspect of this method, the ferroelectric layer may extend vertically through the gate stack.

According to another aspect of the method, the ferroelectric layer is cylindrical in cross section, wherein the ferroelectric layer surrounds an outer surface of the cylindrical channel pillar.

In one aspect, the method further includes disposing a first embedded conductor in a dielectric substrate, disposing the gate stack on the dielectric substrate, the first embedded conductor being connected to the first conductive pillar; and disposing a second embedded conductor in the dielectric substrate, the second embedded conductor being connected to the second conductive post.

In another aspect, the channel layer forms a vertically extending channel post that is continuous in a vertical direction and has a cylindrical cross section.

Other aspects and advantages of the invention will become apparent upon review of the following drawings, detailed description, and claims.

Drawings

FIG. 1 is a schematic top view of a three-dimensional and gate flash memory device having a cylindrical channel pillar structure.

Fig. 2 depicts a schematic top view of a three-dimensional and gate flash memory having an elliptical cylindrical channel pillar structure in accordance with an aspect of the disclosed technology.

Fig. 3 provides an orthogonal view of a three-dimensional and gate flash memory having an oval channel pillar structure and a corresponding cross-sectional view of the oval channel pillar and gate stack structure in accordance with an aspect of the disclosed technology.

FIG. 4 illustrates various voltages applied to a three-dimensional and gate flash memory to perform a read operation in accordance with an aspect of the disclosed technology.

FIG. 5 illustrates various voltages applied to a three-dimensional and gate flash memory to perform a programming operation in accordance with an aspect of the disclosed technology.

FIG. 6 illustrates various voltages applied to a three-dimensional and gate flash memory to perform an erase operation in accordance with an aspect of the disclosed technology.

FIG. 7 illustrates various steps performed according to a first process to fabricate a gate stack structure of a three-dimensional and gate flash memory.

Fig. 8 illustrates various steps performed according to a first process to fabricate a gate stack structure of a three-dimensional and gate flash memory.

Fig. 9 illustrates various steps performed according to a first process to fabricate a gate stack structure of a three-dimensional and gate flash memory.

FIG. 10 shows a step performed according to a first process to fabricate a gate stack structure of a three-dimensional and gate flash memory.

FIG. 11 illustrates various steps performed according to a second process to fabricate a gate stack structure of a three-dimensional and gate flash memory.

FIG. 12 illustrates various steps performed according to a second process to fabricate a gate stack structure of a three-dimensional and gate flash memory.

FIG. 13 illustrates various steps performed according to a second process to fabricate a gate stack structure of a three-dimensional and gate flash memory.

FIG. 14 shows a step performed according to a second process to fabricate a gate stack structure of a three-dimensional and gate flash memory.

FIG. 15 shows a simplified block diagram of a three-dimensional and gate flash memory, a host, and a controller configured to perform operations on the three-dimensional and gate flash memory.

[ Symbolic description ]

100: Three-dimensional and gate flash memory

102: Layer(s)

104: Storage material

106: Round channel column

108: Insulating layer

110: First conductive column

112: Second conductive column

114: Insulation body

200: Three-dimensional and gate flash memory

204: Oval memory material

206: Elliptic cylindrical channel column

208: Insulating layer

210: First conductive column

212: Second conductive column

214: Insulation body

300: Orthogonal diagram

302: Gate stack structure

304: Gate layer

306: Ferroelectric layer

308: Elliptic cylindrical channel column

310: First conductive column

312: Second conductive column

350: Sectional view of the device

700: Process flow

702: Dielectric layer (substrate)

704, 706: Embedding conductor

708: Oval passage hole

710: Channel layer

800: Process flow

802: Central space

804, 806: Hole(s)

900: Process flow

902, 904: Doped polysilicon layer

906, 908, 910, 912: An opening

914: Ferroelectric layer

916: Titanium nitride layer

1000: Process flow

1002: Gate layer

1100: Process flow

1102: Dielectric layer (substrate)

1104, 1106: Embedding conductor

1108: Oval passage hole

1110: Ferroelectric layer

1112: Channel layer

1200: Process flow

1202: Central space

1204, 1206: Hole(s)

1300: Process flow

1302, 1304: Hole(s)

1306, 1308: Doped polysilicon layer

1310, 1312, 1314, 1316: An opening

1402: Titanium nitride layer

1404: Gate layer

1500: Memory system

1502: Host machine

1508: Memory device

1514: Wire (C)

1516: Data path line

1518: Input/output circuit

1526: Data bus system

1528: Cache circuit

1534: Control circuit

1538: Page buffer circuit

1544: Wire (C)

1545, 1546: Arrows

1548: Bit line driver circuit

1564: Square frame

1565: Arrows

1566: Bit line

1576A: word line decoder

1576B: word line driver circuit

1577: Word line

1578: Memory array

A-a': sectional view of the device

B-B': top view

C-C': top view

D, D': diameter of

D2: minor axis diameter

G: gap of

L, L': length of

S, S': spacing of

BL1, BL2: bit line

SL1, SL2: source line

WL1, WL2, WL3, WL4: word line

Detailed Description

The present invention will be further described in detail below with reference to specific embodiments and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.

Detailed description of embodiments of the invention referring to fig. 1 to 15.

Specifically, fig. 1 shows a top view of a (ferroelectric) three-dimensional AND gate (AND) flash memory 100, which includes a layer 102 composed of, for example, silicon oxide. A stack (not shown) is located under layer 102. In addition, the three-dimensional and gate flash memory 100 includes memory material 104, the memory material 104 being formed on an inner surface of an opening created in a process of manufacturing the three-dimensional and gate flash memory 100. The three-dimensional and gate flash memory 100 further includes circular channel pillars 106, the circular channel pillars 106 being formed inside the memory material 104. In one embodiment, the memory material 104 may be continuous along the circular channel pillars 106, allowing the layer 102 to be an insulating layer or gate layer. In another embodiment (not shown), the memory material 104 may be located on an upper surface and a lower surface of the gate layer (e.g., the layer 102 is a gate layer in this embodiment), and the memory material 104 is located on an upper surface and a lower surface of the layer 102).

In addition, the three-dimensional and gate flash memory 100 includes an insulating layer 108 composed of, for example, silicon oxide. The three-dimensional and gate flash memory 100 further includes a first conductive pillar 110, a second conductive pillar 112, and an insulator 114, wherein the first conductive pillar 110 may be a source pillar or a drain pillar, the second conductive pillar 112 may be a source pillar or a drain pillar, and the insulator 114 is disposed between the first conductive pillar 110 and the second conductive pillar 112. The combination of memory material 104, circular via post 106, insulating layer 108, first conductive post 110, second conductive post 112, and insulator 114 may be referred to as a vertical via extending through the stacked structure.

As shown in fig. 1, the three-dimensional and gate flash memory 100 includes a plurality of vertical channels. Exemplary dimensions are depicted for the three-dimensional and gate flash memory 100 and vertical channel structures. These dimensions are for illustrative purposes only and are not drawn to scale, which are provided merely to illustrate the space and size reduction achievable with the disclosed technology (e.g., see the description of fig. 2 provided below). For example, the diameter D of the memory material 104 may be 0.28 μm, the spacing S from the leftmost side of a particular vertical channel to the leftmost side of an adjacent vertical channel may be 0.32 μm, and the length L of the three-dimensional and gate flash memory 100 may be 1.5 μm. The unit vertical channel area can be calculated as (s×l)/(the number of rows of vertical channels). Using the exemplary measurements described above, the unit vertical channel area is equal to (0.32 μm by 1.5 μm)/4, i.e., 0.12 μm ².

The three-dimensional architecture described throughout this disclosure may be implemented as a three-dimensional and gate or three-dimensional NOR device. Although three-dimensional and gate are mainly described, the disclosed technology is not limited thereto and may be implemented as a three-dimensional NOR device.

Fig. 2 depicts a schematic top view of a (ferroelectric) three-dimensional and gate flash memory with an elliptical cylindrical channel pillar structure in accordance with an aspect of the disclosed technology.

Specifically, fig. 2 shows a top view of a three-dimensional and gate flash memory 200 that is capable of reducing the size (footprint) of the vertical channel, thereby allowing more memory to be compressed into a space than the three-dimensional and gate flash memory 100 of fig. 1. The three-dimensional and gate flash memory includes an insulating layer 202 composed of, for example, silicon oxide, and a stacked structure (not shown here but shown in the following figures) is located below the insulating layer 202. In addition, the three-dimensional and gate flash memory 200 includes memory material 204, the memory material 204 being formed on an inner surface of an opening created in a process of fabricating the three-dimensional and gate flash memory 200. As discussed in more detail below, the memory material 204 may be a ferroelectric layer that improves the efficiency and performance of the three-dimensional and gate flash memory 200. The three-dimensional and gate flash memory 200 also includes oval-shaped cylindrical channel pillars 206, the oval-shaped cylindrical channel pillars 206 being formed inside the memory material 204. The storage material 204 is also oval cylindrical. In other words, the oval cylindrical channel post 206 and the oval cylindrical storage material 204 each have an oval cross-section, unlike the circular cross-section of the storage material 104 and circular channel post 106 shown in fig. 1. This oval shape allows the three-dimensional and gate flash memory 200 to have an increased storage capacity compared to the same size of the three-dimensional and gate flash memory 100. In an embodiment, the memory material 204 may be continuous along the elliptical cylindrical channel pillars 206, allowing the layer 202 to act as an insulating layer or gate layer. In another embodiment (not shown), the memory material 204 may be on an upper surface and a lower surface of the gate layer (e.g., the layer 202 is a gate layer in this embodiment), and the memory material 204 is on an upper surface and a lower surface of the layer 202).

In addition, the three-dimensional and gate flash memory 200 includes an insulating layer 208 composed of, for example, silicon oxide. The three-dimensional and gate flash memory 200 further includes a first conductive pillar 210, a second conductive pillar 212, and an insulator 214, the insulator 214 being disposed between the first conductive pillar 210 and the second conductive pillar 212. As shown in fig. 2, the first conductive post 210 and the second conductive post 212 are separated from each other by an insulator 214 and an insulating layer 208. The combination of the oval cylindrical memory material 204, the oval cylindrical channel pillars 206, the insulating layer 208, the first conductive pillars 210, the second conductive pillars 212, and the insulator 214 may be referred to as vertical channels extending through the laminate structure.

As shown in fig. 2, the three-dimensional and gate flash memory 200 includes a plurality of vertical channels. Exemplary dimensions are depicted for the three-dimensional and gate flash memory 200 and vertical channel structures. These dimensions are for illustrative purposes only and are not drawn to scale, which is provided merely to illustrate the space and size reduction achievable by the disclosed technology as compared to the three-dimensional and gate flash memory 100. For example, the diameter D ' (i.e., major axis diameter) of the oval-shaped memory material 204 may be 0.28 μm, the spacing S ' from the leftmost side of a particular vertical channel to the leftmost side of an adjacent vertical channel may be 0.32 μm, and the length L ' of the three-dimensional and gate flash memory 200 may be 0.98 μm. The unit vertical channel area can be calculated as (s×k)/(the number of rows of vertical channels). Using the exemplary measurements described above, the unit vertical channel area is equal to (0.32 μm by 0.98 μm)/4, i.e., 0.0784 μm ².

When comparing the unit vertical channel area of 0.12 μm ² of the three-dimensional and gate flash memory 100 with the unit vertical channel area of 0.0784 μm ² of the three-dimensional and gate flash memory 200, the three-dimensional and gate flash memory 200 can save 35% of space significantly compared to the three-dimensional and gate flash memory 100. This saving allows more memory to be placed into a space and/or smaller memory that is suitable for leaving more space for other components of the electronic device.

Further, the gap G between the vertical channels may be, for example, 0.04 μm, and the short axis diameter D2 of the vertical channels may be, for example, 0.15 μm.

Further, the elliptical cylindrical channel post 206 and the elliptical storage material 204 may be circular (circularly shaped) or another type of shape. This applies to all elliptical structures described throughout this disclosure.

Fig. 3 illustrates an orthogonal view of a three-dimensional and gate flash memory with an elliptical cylindrical channel pillar structure and a corresponding cross-sectional view of the elliptical cylindrical channel pillar structure and gate stack structure in accordance with an aspect of the present technique.

Specifically, fig. 3 includes an orthogonal view 300 of a three-dimensional and gate flash memory and a cross-sectional view 350 of a three-dimensional and gate flash memory. The three-dimensional and gate flash memory includes a gate stack 302, the gate stack 302 including a plurality of gate layers 304, wherein the plurality of gate layers 304 are electrically isolated from each other by an insulator. However, the insulators between each gate layer 304 are not shown in fig. 3. In this aspect of the disclosed technique, ferroelectric layers 306 are located on the upper and lower surfaces of these gate layers 304. Fig. 3 shows three gate layers 304. However, the three-dimensional and gate memory may have any number of gate layers 304.

In addition, the three-dimensional and gate flash memory includes a plurality of oval cylindrical channel pillars 308. Fig. 3 shows four oval cylindrical channel posts 308. However, the three-dimensional and gate flash memory may have any number of oval cylindrical channel pillars 308. An elliptical cylindrical via post 308 extends vertically through each gate layer 304 of the gate stack 302. As shown in fig. 3, the oval cylindrical channel post 308 is oval cylindrical in cross-section. Furthermore, in this aspect of the present technique and in the depicted cross-sectional view 350, the ferroelectric layer 306 also contacts the elliptical cylindrical channel pillars 308 (i.e., the ferroelectric layer 306 is disposed between these gate layers 304 and the elliptical cylindrical channel pillars 308). The process of this structure shown in fig. 3 is illustrated in fig. 7-10 and described below. In another aspect of the present technique, ferroelectric layer 306 covers/surrounds the outer surface of elliptical cylindrical channel pillars 308. The process of forming this alternative structure is illustrated in fig. 11-14 and described below.

Returning to fig. 3, a first conductive pillar 310 (which may be a source pillar or a drain pillar) is disposed/located within each oval cylindrical channel pillar 308, wherein each first conductive pillar 310 also extends vertically through the gate stack 302. In addition, second conductive pillars 312 (which may be source pillars or drain pillars) are disposed/located within each elliptical cylindrical channel pillar 308, wherein each second conductive pillar 312 also extends vertically through the gate stack 302. In other words, each oval cylindrical channel post 308 includes a pair of first conductive posts 310 and second conductive posts 312. As an alternative to that shown in fig. 3, the pairs of first and second conductive posts 310, 312 may be oriented such that the second conductive post 312 within the elliptical cylindrical channel post 308 is on the left and the first conductive post 310 is on the right.

In addition, the first conductive post 310 and the second conductive post 312 of each pair are separated from each other within the elliptical cylindrical channel post 308. In addition, a first conductive post 310 and a second conductive post 312 are connected to the elliptical cylindrical channel post 308. An insulating post (not shown) is disposed within each oval cylindrical channel post 308 between each pair of first conductive posts 310 and second conductive posts 312. In the same manner as the elliptical cylindrical via pillars 308, the first conductive pillars 310 and the second conductive pillars 312 penetrate the gate stack 302.

The oval cylindrical channel post 308 may be continuous in the vertical direction in which it extends, which means that the oval cylindrical channel post 308 is integral in the direction in which it extends and cannot be divided into a plurality of separate portions. The oval cylindrical channel post 308 may be discontinuous in the vertical direction in which it extends, meaning that the oval cylindrical channel post 308 is not unitary in its direction of extension and can be divided into a plurality of separate portions.

Ferroelectric layer 306 may comprise ferroelectric HfO ₂ material, hafnium oxide (including, for example, silicon-doped hafnium oxide and zirconium-doped hafnium oxide), or any other ferroelectric type material known to those skilled in the art. For example, the ferroelectric HfO ₂ material may have a thickness of about 20nm, and may have microcoulombs (μC/cm ²) of about 15-18 per square centimeter.

FIG. 4 illustrates various voltages applied to a three-dimensional and gate flash memory to perform a read operation in accordance with an aspect of the present technique.

Three-dimensional and gate flash memory is arranged to perform various operations such as reading, programming (writing) and erasing. The controller circuit is configured to provide specific electrical signals to various portions of the three-dimensional and gate flash memory to perform these various operations. An exemplary controller circuit is depicted in fig. 15 and described in more detail below.

Fig. 4 shows a source line SL1, a bit line BL1, a source line SL2, and a bit line BL2. The source line SL1 corresponds to, for example, an electrical connection of the first conductive pillar 310 of fig. 3, or corresponds to the first conductive pillar 310 itself. The bit line BL1 corresponds to, for example, the electrical connection of the second conductive pillar 312 of FIG. 3, or the second conductive pillar 312 itself. In addition, the source line SL1 and the bit line BL1 correspond to the electrical connection of the pairs of first conductive pillars 310 and second conductive pillars 312 (or to the pairs of first conductive pillars 310 and second conductive pillars 312 themselves) within the particular elliptical cylindrical channel pillar 308 of FIG. 3. In other words, the source line SL1 and the bit line BL1 are located within the same elliptical cylindrical channel pillar 308.

The source line SL2 corresponds to, for example, an electrical connection of the other first conductive pillar 310 of fig. 3, or corresponds to the other first conductive pillar 310 itself. The bit line BL2 corresponds to, for example, the electrical connection of the other second conductive pillar 312 of FIG. 3, or the other second conductive pillar itself 312. In addition, the source line SL2 and the bit line BL2 correspond to the electrical connection of another pair of first conductive pillars 310 and second conductive pillars 312 (or the other pair of first conductive pillars 310 and second conductive pillars 312 themselves) within another oval-shaped cylindrical channel pillar 308. In other words, the source line SL2 and the bit line BL2 are located within the same elliptical cylindrical channel pillar 308.

Fig. 4 also shows four word lines including WL1, WL2, WL3, and WL4, which correspond to electrical connections for various gate layers (e.g., the gate layers 304 of fig. 3), or to the gate layers themselves.

As shown in fig. 4, a memory cell (cell) is selected for a read operation. The selected memory cell of the three-dimensional and gate memory is located at the intersection of the source line SL1, the bit line BL1, and the word line WL 4. To perform a read operation on a selected memory cell, (i) a selected word line voltage V _WL of about 2V to 4V is applied to word line WL4, (ii) unselected word line voltages V _CWL of about 0V to 2V are applied to unselected word lines WL1, WL2, and WL3, (iii) a selected bit line voltage V _BL of about 0.5V to 1.5V is applied to bit line BL1, (iv) an unselected bit line voltage of 0V is applied to unselected bit line BL2, and (V) a source line voltage of 0V is applied to source lines SL1 and SL2. Using the negative voltage V _CWL on the unselected word lines WL1, WL2, and WL3, leakage current from the unselected word lines WL1, WL2, and WL3 can be avoided. With the three-dimensional and gate flash memory structures described herein, a target read speed on the order of approximately 100ns can be achieved.

FIG. 5 illustrates various voltages applied to a three-dimensional and gate flash memory to perform a program (write) operation in accordance with an aspect of the present technique.

Three-dimensional and gate flash memory is configured to perform various operations such as reading, programming (writing) and erasing. The controller circuit is configured to provide specific electrical signals to various portions of the three-dimensional and gate flash memory to perform these various operations. An exemplary controller circuit is depicted in fig. 15 and described in more detail below.

Fig. 5 shows a source line SL1, a bit line BL1, a source line SL2, and a bit line BL2. The source line SL1 corresponds to, for example, an electrical connection of the first conductive pillar 310 of fig. 3, or corresponds to the first conductive pillar 310 itself. The bit line BL1 corresponds to, for example, the electrical connection of the second conductive pillar 312 of FIG. 3, or the second conductive pillar 312 itself. In addition, the source line SL1 and the bit line BL1 correspond to the electrical connection of the pairs of first conductive pillars 310 and second conductive pillars 312 (or to the pairs of first conductive pillars 310 and second conductive pillars 312 themselves) within a particular elliptical cylindrical channel pillar 308. In other words, the source line SL1 and the bit line BL1 are located within the same elliptical cylindrical channel pillar 308.

The source line SL2 corresponds to, for example, an electrical connection of the other first conductive pillar 310 of fig. 3, or corresponds to the other first conductive pillar 310 itself. The bit line BL2 corresponds to, for example, an electrical connection of the other second conductive pillar 312 of FIG. 3, or corresponds to the other second conductive pillar 312 itself. In addition, the source line SL2 and the bit line BL2 correspond to the electrical connection of another pair of first conductive pillars 310 and second conductive pillars 312 (or the other pair of first conductive pillars 310 and second conductive pillars 312 themselves) within another oval-shaped cylindrical channel pillar 308. In other words, the source line SL2 and the bit line BL2 are located within the same elliptical cylindrical channel pillar 308.

Fig. 5 also shows four word lines including WL1, WL2, WL3, and WL4, which correspond to electrical connections for various gate layers (e.g., the gate layers 304 of fig. 3), or to the gate layers themselves.

As shown in fig. 5, the memory cell is selected for a programming (writing) operation. The selected memory cell of the three-dimensional and gate memory is located at the intersection of the source line SL1, the bit line BL1, and the word line WL 4. To perform a read operation on a selected memory cell, (i) a selected word line voltage V _PGM of about 5V to 8V is applied to word line WL4, (ii) unselected word line voltages of about 0V are applied to unselected word lines WL1, WL2, and WL3, (iii) a selected bit line voltage of about 0V is applied to bit line BL1, (iv) an unselected bit line voltage of 0V is applied to unselected source line SL1, (V) a selected bit line voltage V _{Inhibition of}＝0.5V_PGM is applied to unselected bit line BL2, and (vi) an unselected source line voltage V _{Inhibition of}＝0.5V_PGM is applied to unselected source line SL2. With the three-dimensional and gate flash memory structures described herein, a target programming (writing) speed on the order of about 1 mu architecture can be achieved.

FIG. 6 illustrates various voltages applied to a three-dimensional and gate flash memory to perform an erase operation in accordance with an aspect of the present technique.

Fig. 6 shows a source line SL1, a bit line BL1, a source line SL2, and a bit line BL2. The source line SL1 corresponds to, for example, an electrical connection of the first conductive pillar 310 of fig. 3, or corresponds to the first conductive pillar 310 itself. The bit line BL1 corresponds to, for example, the electrical connection of the second conductive pillar 312 of FIG. 3, or the second conductive pillar 312 itself. In addition, the source line SL1 and the bit line BL1 correspond to the electrical connection of the pairs of first conductive pillars 310 and second conductive pillars 312 (or to the pairs of first conductive pillars 310 and second conductive pillars 312 themselves) within a particular elliptical cylindrical channel pillar 308. In other words, the source line SL1 and the bit line BL1 are located within the same elliptical cylindrical channel pillar 308.

Fig. 6 also shows four word lines including WL1, WL2, WL3, and WL4, which correspond to electrical connections for various gate layers (e.g., the gate layers 304 of fig. 3), or to the gate layers themselves.

As shown in fig. 6, a memory cell (cell) is selected for an erase operation. The selected memory cell of the three-dimensional and gate memory is located at the intersection of the source line SL1, the bit line BL1, and the word line WL 4. To perform an erase operation on a selected memory cell, (i) a selected word line voltage V _ERS of about-5V to-8V is applied to word line WL4, (ii) unselected word line voltages of about 0V are applied to unselected word lines WL1, WL2, and WL3, (iii) a selected bit line voltage of about 0V is applied to bit line BL1, (iv) a selected source line voltage of 0V is applied to source line SL1, (V) an unselected bit line voltage V _{Inhibition of}＝0.5V_ERS is applied to unselected bit line BL2, and (vi) an unselected source line voltage V _{Inhibition of}＝0.5V_ERS is applied to unselected source line SL2. With the three-dimensional and gate flash memory structures described herein, a target erase speed on the order of about 1 μs can be achieved.

In one aspect of the present technique, undesirable high negative bias at the source line SL1 and bit line BL1 may be avoided. In this aspect of the present technology, the voltage is shifted (voltage division scheme) to avoid negative bias. For example, at V _ERS = -8V, the voltage applied to the terminal is offset by +4v. For example, +4V may be applied to the selected source line SL1 and selected bit line BL1, 0V may be applied to the unselected source line SL2 and unselected bit line BL2, 4V may be applied to the selected word line WL4, and +4V may be applied to the unselected word lines WL1, WL2, and WL3, the erase operation being bit-alterable (bit alterable).

FIG. 7 illustrates various steps in fabricating a gate stack structure of a three-dimensional and gate flash memory according to a first process. The entire first process spans fig. 7-11. This ferroelectric layer is formed with a different ferroelectric layer formation compared to the ferroelectric layer formation resulting from the structure formed by the (different) second process described in more detail below.

The process flow 700 of fig. 7 includes four steps including (1) stack formation, (2) vertical via formation, (3) via deposition, and (4) via spacer formation. Each step includes a cross-sectional view A-A ', a top view B-B ' from one location and a top view C-C ' from another location.

The stack formation step includes forming a stack including a dielectric layer (substrate) 702 having two embedded conductors 704 and 706, the dielectric layer (substrate) 702 may be, for example, a silicon oxide layer formed on a silicon substrate, or any other dielectric known to those skilled in the art. The embedded conductor 704 (e.g., conductive plug) may be a first embedded conductor (e.g., an embedded source conductor) disposed horizontally under the stack, and ultimately electrically connected to the source pillar (e.g., see first conductive pillar 210 of fig. 2). The embedded conductor 706 (e.g., a conductive plug) may be a second embedded conductor (e.g., an embedded drain conductor) disposed horizontally under the stack, and ultimately electrically connected to the drain pillar (e.g., see the second conductive pillar 212 of fig. 2). The embedded conductor 704 is connected to the first conductive post 210. The embedded conductor 706 is connected to the second conductive post 212. The embedded conductors 704 and 706 are comprised of polysilicon, metal of other conductive materials. Embedded conductors 704 and 706 may be etch stop layers.

The stacked structure formed in the stacked layer forming step further includes alternating layers of (i) an insulating layer (e.g., silicon oxide) and (ii) a sacrificial layer (e.g., silicon nitride (SiN)). The bottom silicon oxide layer may be referred to as a first layer, the adjacent SiN layer may be referred to as a second layer, the adjacent silicon oxide layer may be referred to as a third layer, the adjacent SiN layer may be referred to as a fourth layer, and the adjacent silicon oxide layer may be referred to as a fifth layer. In fig. 7, the stacked structure has three insulating layers and two sacrificial layers, but the technology of the present disclosure is not limited thereto. For example, more insulating layers and more sacrificial layers may be formed as desired. In addition, as depicted in the stack formation step, top views B-B 'provide top views of the insulating layer and top views C-C' provide top views of the sacrificial layer.

The vertical via forming step includes forming an elliptical via 708 in alternating layers, with top views B-B 'and C-C' showing elliptical cross-sections of the elliptical via 708.

The via deposition step includes applying a via layer 710 along the vertical walls of the five alternating layers and on top of the uppermost insulating layer. Specifically, the channel layer 710 may be applied by forming a channel material layer on the top surface of the uppermost insulating layer and the inner surfaces and bottoms of the elliptical channel holes 708. Channel layer 710 may be, for example, an undoped polysilicon layer, or may be doped (e.g., lightly doped) for the purpose of being a channel. Top views B-B 'and C-C' illustrate oval cross-sections of the channel layer 710 and oval channel holes 708.

The channel spacer step includes removing a portion of the channel layer 710 on top of the uppermost insulating layer and removing a portion of the channel layer 710 on the bottom of the elliptical channel hole 708. This may be accomplished, for example, by performing an anisotropic etch process anisotropic etching process to remove the channel layer 710 from the top of the uppermost insulating layer and the bottom of the elliptical channel holes 708. Top views B-B 'and C-C' depict the fact that the channel layer 710 has been removed from the bottom of the elliptical channel holes 708.

Fig. 8 illustrates various steps in a first process to fabricate a gate stack structure of a three-dimensional and gate flash memory.

Specifically, fig. 8 shows a process flow 800 that is subsequent to the process shown in fig. 7 and discussed above. The process flow 800 of fig. 8 includes four steps including (5) insulator fill and center space formation, (6) silicon nitride (SiN) fill, (7) hole etch, and (8) oxide removal. Each step includes a cross-sectional view A-A ', a top view B-B ' from one location and a top view C-C ' from another location.

The insulator filling and central space forming steps include depositing an insulator (e.g., oxide, etc.) in the elliptical channel holes 708 while also leaving central spaces 802 in the elliptical channel holes 708. The central space 802 may be, for example, an annular hole having a diameter that decreases as the central space 802 approaches the dielectric layer 702. Top views B-B 'and C-C' depict the elliptical cross-sectional shape of the oxide within the elliptical channel holes 708 and depict the circular or annular cross-sectional shape of the central space 802.

The SiN filling step includes filling the central space 802 with an insulator such as SiN. This SiN may be referred to as a center pillar. An oxide insulator surrounds the center post. Top views B-B 'and C-C' depict cross-sectional views of SiN filled into central space 802.

The hole etching step includes etching a hole 804 through the oxide layer and etching a hole 806 through the oxide layer. Top views B-B 'and C-C' depict holes 804, holes 806, and the orientation of SiN relative to the other.

The oxide removal step includes further removing a portion of the oxide. Top views B-B 'and C-C' depict other portions of the oxide removed in this step. This step essentially enlarges holes 804 and 806 so that the expanded holes reach channel layer 710.

FIG. 9 illustrates various steps in fabricating a gate stack structure of a three-dimensional and gate flash memory according to a first process.

Specifically, fig. 9 depicts a process flow 900, the process flow 900 continuing the process shown in fig. 8 and discussed above. The process flow 900 of fig. 9 includes three steps including (9) plug formation, (10) SiN removal of the stack, and (11) formation of ferroelectric and titanium nitride (TiN) layers. Each step includes a cross-sectional view A-A ', a top view B-B ' from one location, and a top view C-C ' from another location.

The plug formation step includes disposing conductors such as doped polysilicon layers 902 and 904 in the extended holes formed, for example, by the oxide removal step of fig. 8. Doped polysilicon layers 902 and 904 represent the first conductive pillars 210 and the second conductive pillars 212 of the three-dimensional and gate flash memory shown in fig. 2. Doped polysilicon layers 902 and 904 are located within oval channel layer 710 as shown in top view B-B 'and top view C-C'. In addition, doped polysilicon layers 902 and 904 are separated (insulated) from each other by oxide and SiN. The doped polysilicon layer 902 will be referred to herein as a first conductive pillar and the doped polysilicon layer 904 will be referred to herein as a second conductive pillar.

The SiN stack removal step includes removing the sacrificial layer from the stack to form openings 906, 908, 910, and 912. Top view B-B 'and top view C-C' depict the difference in cross-sections that include silicon oxide (see top view B-B ') and that include openings 910 and 912 (see top view C-C').

The formation of ferroelectric and titanium nitride layers includes adding a ferroelectric layer 914 within openings 906, 908, 910, and 912, followed by adding a titanium nitride layer 916 within openings 906, 908, 910, and 912. Ferroelectric layer 914 may comprise a ferroelectric HfO ₂ material or any other ferroelectric type material known to those of ordinary skill in the art, and titanium nitride layer 916 may comprise other metal nitride materials or other barrier materials, such as TaN. Top views B-B 'show cross-sections where ferroelectric layer 914 and titanium nitride layer 916 are not present in the silicon oxide layer, and top views C-C' show cross-sections where ferroelectric layer 914 and titanium nitride layer 916 are present in openings 910 and 912. As shown in top view C-C', one of ferroelectric layers 914 is elliptical and in contact with the channel layer and one of titanium nitride layers 916 is elliptical and in contact with ferroelectric layer 914.

FIG. 10 shows a step of fabricating a gate stack structure of a three-dimensional and gate flash memory according to a first process.

Specifically, fig. 10 illustrates a process flow 1000, with process flow 100 continuing the process illustrated in fig. 9 and discussed above. The process flow 1000 of fig. 10 includes a step that includes (12) gate formation.

The gate formation step includes adding a gate layer 1002 in the remaining spaces of openings 906, 908, 910, and 912. As shown, ferroelectric layer 914 covers the upper and lower surfaces of each gate. The gate layer 1002 may include, for example, polysilicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (A1), tungsten silicide (WSix), or cobalt silicide (CoSix). In other embodiments, a barrier layer may be formed in sequence in openings 906, 908, 910, and 912 prior to forming gate layer 1002. The barrier layer may be composed of, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof.

Top views B-B 'and C-C' depict different layers of channel layer 710 surrounding a cross section from the silicon oxide layer and a cross section of gate layer 1002.

FIG. 11 illustrates various steps in fabricating a gate stack structure of a three-dimensional and gate flash memory according to a second process.

The structure produced by the second process has a different ferroelectric layer formation than the ferroelectric layer formation produced by the structure formed by the first process.

The process flow 1100 of fig. 11 includes four steps including (1) stack formation, (2) vertical via formation, (3) ferroelectric layer formation, and (4) via deposition, each step including a cross-sectional view A-A ', a top view B-B ' from one location, and a top view C-C ' from another location.

The stack formation step includes forming a stack including a dielectric layer (substrate) 1102 having two embedded conductors 1104 and 1106. The dielectric layer (base) 1102 is, for example, a silicon oxide layer formed on a silicon substrate. The embedded conductor 1104 may be a source conductor disposed horizontally under the stack and ultimately electrically connected to a source pillar (see, e.g., first conductive pillar 210 of fig. 2). The embedded conductor 1106 may be a drain conductor disposed horizontally under the stack and ultimately electrically connected to a drain pillar (e.g., see first conductive pillar 210 of fig. 2). The embedded conductor 1104 is connected to the first conductive post 210. The embedded conductor 1106 is connected to the second conductive post 212. The embedded conductors 1104 and 1106 are comprised of polysilicon, metal of other conductive material.

The stacked structure formed in the stack formation step further includes alternating layers of (i) an insulating layer (e.g., silicon oxide) and (ii) a sacrificial layer (e.g., silicon nitride (SiN)). In fig. 11, the stacked structure has three insulating layers and two sacrificial layers, but the technology of the present disclosure is not limited thereto. For example, more insulating layers and more sacrificial layers may be formed as desired. In addition, as depicted in the stack formation step, top views B-B 'provide top views of the insulating layer and top views C-C' provide top views of the sacrificial layer.

The vertical via formation step includes forming an elliptical via 1108 in alternating layers, with top views B-B 'and top views C-C' showing elliptical cross-sections of the elliptical via 1108.

The ferroelectric layer forming step includes applying a ferroelectric layer 1110 along the vertical walls of the five alternating layers and on top of the uppermost insulating layer. Specifically, the ferroelectric layer 1110 may be applied by forming a ferroelectric material layer on the top surface of the uppermost insulating layer and the inner surfaces and bottoms of the elliptical via holes 1108. Ferroelectric layer 1110 may be, for example, a ferroelectric HfO ₂ material or any other ferroelectric type material known to those skilled in the art. Top views B-B 'and C-C' illustrate elliptical cross-sections of ferroelectric layer 1110 and elliptical via 1108.

The channel deposition step includes applying a channel layer 1112 along the ferroelectric layer 1110. Specifically, channel layer 1112 may be applied by forming channel material on ferroelectric layer 1110 such that it is on the top surface of the uppermost insulating layer and the inner surfaces and bottoms of elliptical channel holes 1108. The channel layer 1112 may be, for example, an undoped polysilicon layer, or may be doped (e.g., lightly doped) for the purpose of being a channel. Top views B-B 'and C-C' illustrate elliptical cross-sections of ferroelectric layer 1110, channel layer 1112, and elliptical channel holes 1108. As shown, ferroelectric layer 1110 covers/surrounds the outer surface of channel layer 1112.

FIG. 12 illustrates various steps in fabricating a gate stack structure of a three-dimensional and gate flash memory according to a second process.

Specifically, fig. 12 depicts a process flow 1200, the process flow 1200 continuing the process shown in fig. 12 and discussed above. The process flow 1200 of fig. 12 includes four steps including (5) spacer formation, (6) insulator fill and center space formation, (7) silicon nitride (SiN) fill, and (8) hole etching. Each step includes a cross-sectional view A-A ', a top view B-B ' from one location and a top view C-C ' from another location.

The channel spacer step includes removing a portion of the ferroelectric layer 1110 and the channel layer 1112 on top of the uppermost insulating layer and removing a portion of the ferroelectric layer 1110 and the channel layer 1112 on the bottom of the insulating layer. This may be accomplished, for example, by performing an anisotropic etch process to remove the ferroelectric layer 1110 and channel layer 1112 from the top of the uppermost insulating layer and the bottom of the elliptical channel. Top views B-B 'and C-C' depict the fact that ferroelectric layer 1110 and channel layer 1112 have been removed from the bottom of elliptical channel hole 1108. As shown, ferroelectric layer 1110 overlies the outer surface of channel layer 1112 (e.g., elliptical cylindrical channel post 206 of fig. 2).

The insulator filling and central space forming steps include depositing an insulator (e.g., oxide, etc.) in the oval-shaped via 1108 while also leaving a central space 1202 in the oval-shaped via 1108. The central space 1202 may be, for example, an annular hole having a diameter that decreases as the central space 1202 approaches the dielectric layer (substrate) 1102. Top views B-B 'and C-C' depict the elliptical cross-sectional shape of the oxide within the elliptical passage hole 1108 and depict the circular or annular cross-sectional shape of the central space 1202.

The silicon nitride (SiN) filling step in this step includes filling the central space 1202 with an insulator such as silicon nitride (SiN), and top views B-B 'and C-C' depict cross-sectional views of the silicon nitride (SiN) filled into the central space 1202.

The hole etching step includes etching a hole 1204 through the oxide layer and etching a hole 1206 through the oxide layer. Top views B-B 'and C-C' depict holes 1204, holes 1206, and SiN orientation relative to one another.

FIG. 13 illustrates various steps in fabricating a gate stack structure of a three-dimensional and gate flash memory according to a second process.

Specifically, fig. 13 depicts a process flow 1300, the process flow 1300 continuing the process shown in fig. 12 and discussed above. The process flow 1300 of fig. 13 includes three steps including (9) oxide removal, (10) plug formation, and (11) removal of a silicon nitride (SiN) stack. Each step includes a cross-sectional view A-A ', a top view B-B ' from one location and a top view C-C ' from another location.

The oxide removal step includes further removing a portion of the oxide. Top views B-B 'and C-C' depict other portions of the oxide removed in this step. This step essentially enlarges holes 1204 and 1206 to form extended holes 1302 and 1304 so that the extended holes reach channel layer 1112.

The plug formation step includes disposing conductors such as doped polysilicon layers 1306 and 1308 in the extended holes 1302 and 1304 formed, for example, by an oxide removal step. Doped polysilicon layers 1306 and 1308 represent the first conductive pillars 210 and the second conductive pillars 212 of the three-dimensional and gate flash memory device shown in fig. 2. Doped polysilicon layers 1306 and 1308 are located within elliptical channel layer 1112, as shown in top view B-B 'and top view C-C'. In addition, doped polysilicon layers 1306 and 1308 are separated (insulated) from each other by oxide and silicon nitride (SiN). The doped polysilicon layer 1306 will be referred to herein as a first conductive pillar and the doped polysilicon layer 1308 will be referred to herein as a second conductive pillar.

The SiN stack removal step includes removing the sacrificial layer from the stack to form openings 1310, 1312, 1314, and 1316. Top view B-B 'and top view C-C' depict differences in cross-sections that include silicon oxide (see top view B-B ') and that include openings 1314 and 1316 (see top view C-C').

FIG. 14 shows a step of fabricating a gate stack structure of a three-dimensional and gate flash memory according to a second process.

Specifically, fig. 14 depicts a process flow 1400, the process flow 1400 continuing the process shown in fig. 13 and discussed above. The process flow 1400 of fig. 14 includes a step that includes (12) titanium nitride (TiN) and gate formation.

The titanium nitride layer formed includes the addition of titanium nitride layer 1402 inside openings 1310, 1312, 1314 and 1316. The titanium nitride layer 1402 may include other metal nitride materials or other barrier materials, such as tantalum nitride (TaN). Top views B-B 'show cross-sections of ferroelectric layer 110, channel layer 1112, and silicon oxide layer, and top views C-C' show cross-sections of ferroelectric layer 1110, channel layer 1112, and titanium nitride layer 1402 formed by openings 1314 and 1316. As shown in top view C-C', one of ferroelectric layers 1110 is elliptical and is in contact with channel layer 1112 and one of titanium nitride layers 1402 is elliptical and is in contact with ferroelectric layer 1110.

The gate formation step includes adding a gate layer 1404 in the remaining spaces of openings 1310, 1312, 1314 and 1316. The gate layer 1404 may include, for example, polysilicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (A1), tungsten silicide (WSix), or cobalt silicide (CoSix). Furthermore, in other embodiments, a barrier layer may be formed in the openings 1310, 1312, 1314, and 1316 sequentially before forming the gate layer 1404. The barrier layer may be composed of, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof.

Top views B-B 'and C-C' depict cross-sections around the slave silicon oxide layer and the gate layer 1404.

FIG. 15 is a simplified block diagram of a gate stack structure of a three-dimensional and gate flash memory, a host, and a controller configured to perform operations on the three-dimensional and gate flash memory.

Fig. 15 is a simplified diagram of a memory system 1500, the memory system 1500 including a three-dimensional and gate flash memory device 1508 implemented on an integrated circuit and a host 1502 configured for memory operations (including page programming, reading, erasing, or other operations). In various embodiments, the memory device 1508 may have a single-LEVEL CELLS (SLC) or a multi-layer memory cell (e.g., MLC, TLC, or XLC) that stores more than one bit per memory cell. The memory device 1508 may be implemented on a single integrated circuit chip, a multi-chip module, or on multiple chips configured to suit particular needs.

The memory device 1508 includes a memory array 1578, which may be a three-dimensional and gate flash memory implemented using three-dimensional array technology, such as the structures described above with reference to fig. 1-14. Array 1578 may be an array of vertical AND pillars in a dense three-dimensional configuration. In other embodiments, memory array 1578 may include a two-dimensional array of AND pillars.

The word line decoder 1576 is coupled to a plurality of word lines 1577 in a memory array 1578 through word line driver circuitry 1576B. Page buffer circuitry 1538 is coupled to bit lines 1566 in memory array 1578 through bit line driver circuitry 1548. In some embodiments, column decoder circuitry (column decoder circuits) may be included for routing data from the bit line drivers to the selected bit lines. The page buffer circuit 1538 may store a page of data defining a data pattern for use in a page program operation, and may include sense circuitry for read and verify operations.

Bit lines for a memory array may include Global Bit Lines (GBL) and local bit lines (local bit lines). The bit lines typically include conductors in a higher patterned layer that traverse multiple blocks of memory cells in the array and are connected to local bit lines in the blocks via block select transistors or group select transistors. The local bit lines are connected to memory cells to flow current into and out of the bit lines, which are also connected to bit line driver circuitry 1548 and page buffer circuitry 1538. Likewise, the word lines may include global word lines and local word lines, with corresponding support circuitry in word line driver circuitry 1576B.

In a sense operation, sense data from the page buffer circuit 1538 is supplied to a cache circuit 1528 via a second data line in the data bus system 1526, the cache circuit 1528 being coupled to an input/output circuit 1518 via a data path line 1516. Also, in this embodiment, input data is applied to the cache circuit 1528 on the data path line 1516 and to the page buffer circuit 1538 on the data bus system 1526 for supporting programming operations.

Input/output circuitry 1518 is connected by lines 1514 (including I/O pads) and provides a communication path for data, addresses, and commands with a destination external to the memory device 1508 (which in this embodiment includes the host 1502). The input/output circuitry 1518 provides a communication path to the cache circuitry 1528 supporting memory operations through data path lines 1516. The cache circuit 1528 is in data flow communication with the page buffer circuit 1538 (e.g., using the data bus system 1526).

Control circuitry 1534 is connected to input/output circuitry 1518 and includes command decoder logic, address counters, state machines, timing circuitry, and other logic circuitry that controls various memory operations, including programming, reading, and erasing operations on memory array 1578. For example, referring to fig. 1-14 and the description thereof, the control circuit 1534 is configured to (i) provide various voltages to selected word lines connected to selected gate layers of the gate stack structure of the three-dimensional flash memory, (ii) provide various voltages to selected bit lines connected to second conductive pillars in the elliptical cylindrical channel pillars of the three-dimensional flash memory, and (iii) provide various voltages to selected source lines connected to first conductive pillars in the elliptical cylindrical channel pillars of the three-dimensional flash memory.

As indicated by arrows 1545, 1546, the control circuit signals are distributed as needed to the circuitry in the memory device to support operation of the circuitry. The control circuitry 1534 may include address registers ADDRESS REGISTERS, etc. for delivering addresses to the components of the memory device 1508 as needed, including in this example to the cache circuit 1528 and on line 1544 to the page buffer circuit 1538 and the word line decoder 1576A.

In the embodiment shown in fig. 15, the control circuitry 1534 includes control logic circuitry including a module implementing one or more bias configuration state machines (bias ARRANGEMENT STATE MACHINE) that control the bias voltages of the present disclosure (including precharge voltage, read, erase, verify, and program voltages including pass voltages and other bias voltages as described herein) generated or provided via the voltage supply in block 1564 to the word line driver circuitry 1576B and the bit line driver circuitry 1548 for a set of selectable programming and read operations. A bias voltage is applied to the components of the memory device 1508 as indicated by arrow 1565 to support operation as needed. As described in more detail below, the control circuitry 1534 provides appropriate signals (e.g., voltages) to perform the various read, write, and erase operations described above in fig. 4-6.

As is known in the art, the control circuit 1534 may include a module implemented using dedicated logic circuitry including a state machine. In alternative embodiments, the control circuit 1534 may comprise a module implemented using a general purpose processor, which may be implemented on the same integrated circuit that executes computer programming to control the operation of the memory device 1508. Among other circuits, a combination of dedicated logic circuits and a general-purpose processor may be used for implementation of the modules in the control circuit 1534.

The three-dimensional and gate flash memory array 1578 may include floating gate memory cells (floating gate memory cells) or dielectric charge trapping memory cells (DIELECTRIC CHARGE TRAPPING memory cells) that store multiple bits per memory cell by establishing multiple programming levels (multiple program levels) corresponding to the amount of charge stored, thereby establishing a memory cell threshold voltage Vt. This technique may be used with single-bit-per-cell flash memory and with other multi-bit-per-cell and single-bit-per-cell memory techniques. In other embodiments, memory storage cells may include programmable resistance storage cells (programmable resistance memory cells), phase change storage cells (PHASE CHANGE memory cells), and other types of non-volatile and volatile storage cell technologies.

In the illustrated embodiment, the host 1502 is coupled to a line 1514 on the memory device 1508 and other control terminals (e.g., chip select terminals, etc.), not shown, and can provide commands or instructions to the memory device 1508. In some embodiments, the host 1502 may be coupled to the memory device using serial bus technology (serial bus technology), using shared address and data lines. The host 1502 may include a general purpose processor, a special purpose processor, a processor configured to act as a memory controller, or other processor using the memory device 1508. All or a portion of the host 1502 may be implemented on the same integrated circuit as the memory.

Host 1502 may include one or more file systems that store, retrieve, and update data stored in memory based on requests from application programming. In general, host 1502 may include programming to perform memory management functions and other functions to generate status information for data stored in memory, including information tag data that will be invalid due to such functions. Such functions may include, for example, wear leveling, bad block recovery, power loss recovery, garbage collection, error correction, and the like. Moreover, host 1502 may include application programming, file systems, flash translation layer programming (flash translation layer programs), and other components that may generate status data (including information tag data that would be invalid due to this function) for data stored in memory.

In high density memory, a page may include hundreds or thousands of bits, and a page buffer may be connected in parallel with corresponding hundreds or thousands of bit lines. For example, during a programming operation, one set of bit lines and word lines are selected to bias programming a particular data pattern defined by the contents of page buffer circuit 1538, and another set of bit lines are selected to bias inhibit programming according to this particular data pattern.

Other embodiments of the methods described in this section may include a non-volatile computer-readable storage medium storing instructions executable by a processor to perform any of the methods described above. The system includes a memory and one or more processors operable to execute instructions stored in the memory to perform any of the methods described above.

According to many embodiments, any of the data structures and encodings described or referenced above are stored on a computer-readable storage medium, which may be any device or medium that can store the encodings and/or data for use by a computer system. This includes, but is not limited to, volatile memory, non-volatile memory, application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs), magnetic and optical storage devices, such as disk drives, magnetic tape, CDs (compact discs), DVDs (digital versatile discs or digital video discs), or other media capable of storing computer readable media either now known or later developed.

A number of flowcharts of logic performed by a memory controller or memory device are described herein. Such logic may be implemented using a processor, where the processor is programmed using computer programming stored in a memory readable by a computer system, which may be executed by the processor, by dedicated logic hardware (including field programmable integrated circuits), or by a combination of dedicated logic hardware and a computer system. It will be appreciated from all of the flowcharts herein that many of the steps can be combined, performed in parallel, or performed in a different order without affecting the function sought to be achieved. In some cases, as the reader will appreciate, the same result may be obtained with rearrangement of steps only if certain other modifications are made. In other cases, as the reader understands, the rearrangement of steps can achieve the same results only when certain conditions are met. It should be understood that the flow charts herein show only the steps relevant to understanding the present invention, and that many additional steps for accomplishing other functions may be performed before, after and between those shown.

While the invention has been disclosed by reference to the preferred embodiments and examples above, it is understood that these embodiments are illustrative only and are not limiting. Modifications and combinations readily attainable by one skilled in the art are within the spirit of the present invention and the scope of the appended claims.

While the foregoing is directed to embodiments of the present invention, other and further details of the invention may be had by the present invention, it should be understood that the foregoing description is merely illustrative of the present invention and that no limitations are intended to the scope of the invention, except insofar as modifications, equivalents, improvements or modifications are within the spirit and principles of the invention.

Claims

1. A three-dimensional flash memory, comprising:

a gate stack structure including a plurality of gate layers electrically insulated from each other;

A cylindrical channel pillar extending vertically through each gate layer of the gate stack, the cylindrical channel pillar having a cylindrical cross section;

A first conductive pillar extending vertically through the gate stack, the first conductive pillar being located within and electrically connected to the cylindrical via pillar;

A second conductive pillar extending vertically through the gate stack, the second conductive pillar being located within and electrically connected to the cylindrical via pillar, the first conductive pillar and the second conductive pillar being separated from each other; and

And the ferroelectric layer is arranged between the plurality of gate layers of the gate laminated structure and the cylindrical channel column.

2. The three-dimensional flash memory of claim 1, wherein an insulating pillar is disposed within the cylindrical channel pillar and between the first conductive pillar and the second conductive pillar.

3. The three-dimensional flash memory of claim 1,

Wherein a first embedded conductor is horizontally arranged below the gate stack structure and is electrically connected to the first conductive column, and

One of the second embedded conductors is horizontally arranged below the gate laminated structure and is electrically connected to the second conductive column.

4. The three-dimensional flash memory of claim 1,

Wherein the ferroelectric layer extends vertically through the gate stack.

5. The three-dimensional flash memory of claim 1, wherein the ferroelectric layer is located on an upper surface and a lower surface of a gate layer of the plurality of gate layers.

6. The three-dimensional flash memory of claim 1, wherein the ferroelectric layer surrounds an outer surface of the pillar of the cylindrical channel.

7. The three-dimensional flash memory of claim 1, wherein the cylindrical channel pillars are continuous in a vertical direction.

8. The three-dimensional flash memory of claim 1, wherein the ferroelectric layer comprises a ferroelectric HfO ₂ material.

9. The three-dimensional flash memory of claim 1, further comprising:

And an insulator disposed between and extending along a length of the first and second conductive posts, the insulator separating the first and second conductive posts from each other.

10. The three-dimensional flash memory of claim 1, further comprising:

A first embedded conductor arranged in a dielectric substrate and connected to the first conductive column, wherein the gate stack structure is arranged on the dielectric substrate;

a second embedded conductor disposed in the dielectric substrate and connected to the second conductive post; and

A control circuit configured to perform a programming operation on the three-dimensional flash memory by:

Providing a programming voltage V _PGM of +5v to +8v on a selected word line connected to a selected gate layer of the plurality of gate layers;

Providing a voltage of 0V on a selected source line connected to the first buried conductor within the cylindrical channel pillar, the first buried conductor being connected to the first conductive pillar; and

A voltage of 0V is provided on a selected bit line connected to the second buried conductor connected to the second conductive pillar within the cylindrical via pillar.

11. The three-dimensional flash memory of claim 1, further comprising:

a control circuit configured to perform an erase operation on the three-dimensional flash memory by:

providing an erase voltage V _ERS V to-8V on a selected word line connected to a selected gate layer of the plurality of gate layers;

Providing a voltage of 0V on a selected source line connected to the first conductive pillar within the cylindrical channel pillar; and

A voltage of 0V is provided on a selected bit line that is connected to the second conductive pillar within the cylindrical channel pillar.

12. The three-dimensional flash memory of claim 11, wherein the control circuitry is further configured to perform the erase operation on the three-dimensional flash memory by:

Providing a voltage of 0V to a plurality of unselected word lines connected to the plurality of gate layers other than the selected gate layer;

Providing a voltage of (0.5) x (V _ERS) V to an unselected source line connected to another first conductive pillar within another cylindrical channel pillar; and

A voltage of (0.5) × (V _ERS) V is supplied to an unselected bit line that is connected to another second conductive pillar within the other cylindrical channel pillar.

13. The three-dimensional flash memory of claim 1, further comprising:

A second cylindrical passage column having the same structure and configuration as the cylindrical passage column;

a third conductive pillar having the same structure and configuration as the first conductive pillar;

a fourth conductive pillar having the same structure and configuration as the second conductive pillar;

A control circuit configured to perform a read operation on the three-dimensional flash memory by:

providing a voltage of approximately +2v to +4v on a selected word line, the selected word line connected to a selected gate layer of the plurality of gate layers;

Providing a voltage of about 0V on a plurality of selected and unselected source lines connected to the first conductive pillar within the cylindrical channel pillar and to the third conductive pillar within the second cylindrical channel pillar; and

A voltage of about +0.5V to +1.5V is provided on a selected bit line that is connected to the first conductive pillar within the cylindrical channel pillar.

14. The three-dimensional flash memory of claim 13, wherein the control circuitry is further configured to perform the read operation on the three-dimensional flash memory by:

Providing a voltage of about 0V to-2V to a plurality of unselected word lines connected to the plurality of gate layers other than the selected gate layer; and

A voltage of about 0V is provided to a plurality of unselected bit lines connected to the fourth conductive pillar within the second cylindrical channel pillar.

15. The three-dimensional flash memory of claim 1, wherein the cylindrical channel pillar is elliptical, having a cross-section of an elliptical cylinder.

16. A control circuit configured to program, erase and read a three-dimensional flash memory,

Wherein the three-dimensional flash memory comprises:

A ferroelectric layer disposed between the gate layers and the column of the gate stack, and

Wherein the control circuitry is configured to perform various program, erase, and read operations by:

providing various voltages to a selected word line connected to a selected gate layer of the gate stack of the three-dimensional flash memory;

Providing various voltages to a selected bit line, the selected bit line being connected to the second conductive pillar within the cylindrical channel pillar of the three-dimensional flash memory; and

Various voltages are provided to a selected source line that is connected to the first conductive pillar within the cylindrical channel pillar of the three-dimensional flash memory.

17. A method of forming a gate stack comprising a dielectric layer and a ferroelectric layer, the method comprising:

Forming a gate stack structure including a plurality of gate layers electrically insulated from each other;

forming a cylindrical channel pillar extending vertically through each gate layer of the gate stack, the cylindrical channel pillar having a cylindrical cross section;

Forming a first conductive pillar extending vertically through the gate stack, the first conductive pillar being located within and electrically connected to the cylindrical via pillar;

Forming a second conductive pillar extending vertically through the gate stack, the second conductive pillar being located within and electrically connected to the cylindrical via pillar;

Forming an insulating column, wherein the insulating column is arranged in the cylindrical channel column and between the first conductive column and the second conductive column; and

Forming a ferroelectric layer disposed between the plurality of gate layers and the cylindrical channel pillars of the gate stack.

18. The method of claim 17, wherein the ferroelectric layer extends vertically through the gate stack.

19. The method according to claim 17,

Wherein the ferroelectric layer has an elliptical cylinder in cross section, and

Wherein the ferroelectric layer surrounds an outer surface of the cylindrical via post.

20. The method of claim 17, further comprising:

disposing a first embedded conductor in a dielectric substrate, the gate stack being disposed on the dielectric substrate, the first embedded conductor being connected to the first conductive pillar; and

A second embedded conductor is disposed in the dielectric substrate, the second embedded conductor being connected to the second conductive post.