CN112466882A - Manufacturing method of three-dimensional memory and three-dimensional memory - Google Patents
Manufacturing method of three-dimensional memory and three-dimensional memory Download PDFInfo
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- CN112466882A CN112466882A CN202011302330.8A CN202011302330A CN112466882A CN 112466882 A CN112466882 A CN 112466882A CN 202011302330 A CN202011302330 A CN 202011302330A CN 112466882 A CN112466882 A CN 112466882A
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
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- H—ELECTRICITY
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- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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Abstract
The invention provides a manufacturing method of a three-dimensional memory and the three-dimensional memory, in the manufacturing method of the three-dimensional memory, because a part of a conventional semiconductor layer at the top of a first stacked structure on a step area is replaced by a substitute semiconductor layer, and when the conventional semiconductor layer at the top of the first stacked structure is etched, the etching rate of the substitute semiconductor layer is higher than that of the conventional semiconductor layer, so that the etching depths of a grid line separating groove formed by etching in an array area and the step area are different, on the basis, a barrier layer formed on the side wall of the grid line separating groove subsequently can shield the conventional semiconductor layer at the middle part of the first stacked structure on the step area, and when the conventional semiconductor layer at the middle part of the first stacked structure on the step area is removed by wet etching at the bottom of the grid line separating groove, the conventional semiconductor layer at the middle part of the first stacked structure on the step, the supporting requirement of the virtual channel structure on the step area is simplified, and the process difficulty of the virtual channel structure is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a three-dimensional memory and the three-dimensional memory.
Background
The three-dimensional memory is a technology for stacking data units, can realize the stacking of 32 layers or more of data units at present, overcomes the limitation of the practical expansion limit of a plane memory, further improves the storage capacity, reduces the storage cost of each data bit, and reduces the energy consumption. With the continuous development of the three-dimensional memory, higher integration level and lower cost investment become the motive power for promoting the continuous advance of the three-dimensional memory.
However, as the number of layers of the three-dimensional memory is increasing, the stability of the whole architecture becomes one of the key factors that restrict the process development: in the current production and manufacturing process, the traditional SONO channel hole etching process approaches the bottleneck along with the increase of the layer number, and in order to match related processes, a structure of 'polysilicon + silicon nitride + polysilicon' is introduced at the bottom of a stack layer in the initial stage of the manufacturing process; the weakest link of the three-dimensional memory architecture is that after the bottom silicon nitride is removed, in the current production manufacturing process, a conductive channel structure is used for supporting in an array region, a virtual channel structure is used for supporting in a step region, but after the bottom silicon nitride is removed, a large hollow part exists in the three-dimensional memory structure, and the stability of the whole architecture is not enough.
Therefore, how to realize more stable support of the three-dimensional memory architecture after introducing the "polysilicon + silicon nitride + polysilicon" structure process is a problem to be solved at present.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a method for manufacturing a three-dimensional memory with improved architecture support, which solves the above-mentioned technical problems.
To achieve the above and other related objects, the present invention provides a method for manufacturing a three-dimensional memory, including:
providing a substrate, wherein the substrate comprises an array area and a step area;
forming a first stacked structure on the substrate, wherein the first stacked structure comprises a plurality of layers of conventional semiconductor layers which are sequentially stacked along the direction from the substrate to a direction far away from the substrate;
replacing a portion of the conventional semiconductor layer on top of the first stacked structure on the step region with a first replacement semiconductor layer;
forming a second stacked structure covering the first stacked structure and the first replacement semiconductor layer;
etching to form a grid line separation groove, wherein the etching on the array region passes through the second stacked structure and then stays in the conventional semiconductor layer at the top of the first stacked structure, and the etching on the step region passes through the second stacked structure and the first substitute semiconductor layer and then stays in the conventional semiconductor layer at the bottom of the first stacked structure;
wherein, when the conventional semiconductor layer on the top of the first stacked structure is etched, the etching rate of the first substitute semiconductor layer is higher than that of the conventional semiconductor layer.
Optionally, the first stacked structure includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer stacked in sequence along a direction from the substrate to a direction away from the substrate.
Optionally, the step of replacing a portion of the conventional semiconductor layer on top of the first stacked structure on the step region with the first replacement semiconductor layer includes:
etching the third semiconductor layer, and removing at least part of the third semiconductor layer on the step region;
forming the fourth semiconductor layer at the position where the third semiconductor layer is etched and removed, and carrying out surface planarization treatment;
wherein the fourth semiconductor layer is the first alternative semiconductor layer.
Optionally, after forming the second stacked structure and before forming the gate line separation groove by etching, the method for manufacturing a three-dimensional memory further includes:
etching the second stacked structure and the first stacked structure, forming a channel hole on the array region, and forming a virtual channel hole on the step region;
filling the channel hole to form a conductive channel structure; and filling the virtual channel hole to form a virtual channel structure.
Optionally, when the gate line separation groove is formed by etching, the etching on the array region passes through the second stacked structure and the third semiconductor layer and then stays on the second semiconductor layer, and the etching on the step region passes through the second stacked structure, the fourth semiconductor layer and the second semiconductor layer and then stays in the first semiconductor layer.
Optionally, when the third semiconductor layer is etched, the etching rate of the fourth semiconductor layer and the etching rate of the second semiconductor layer are respectively higher than the etching rate of the third semiconductor layer.
Optionally, the method for manufacturing the three-dimensional memory further includes:
forming barrier layers at the bottom and on the side wall of the grid line separation groove;
and continuously etching after removing the barrier layer at the bottom of the grid line separation groove by etching, stopping etching in the first semiconductor layer and exposing the second semiconductor layer on the array region.
Optionally, the method for manufacturing the three-dimensional memory further includes:
and separating the groove along the grid line, removing the second semiconductor layer on the array region, and remaining the second semiconductor layer on the step region.
Optionally, the method for manufacturing the three-dimensional memory further includes:
and forming a fifth semiconductor layer at a position occupied by the second semiconductor layer on the array region along the gate line separation groove.
Optionally, the second stacked structure includes a plurality of alternately arranged dummy gate layers and dielectric layers, and after forming the fifth semiconductor layer, the method for manufacturing a three-dimensional memory further includes:
and separating grooves along the grid lines, and replacing the dummy grid layer with a grid layer.
Further, to achieve the above and other related objects, the present invention provides a three-dimensional memory including:
a substrate including an array region and a step region;
the first stack structure is arranged on the substrate, comprises a plurality of layers of conventional semiconductor layers which are sequentially stacked along the direction from the substrate to the direction away from the substrate on the partial area of the stepped area, comprises a plurality of layers of the conventional conductor layers and a layer of first substitute semiconductor layer which are sequentially stacked along the direction from the substrate to the direction away from the substrate on the partial area of the stepped area, and comprises a plurality of layers of the conventional semiconductor layers, a layer of second substitute semiconductor layers and a plurality of layers of the conventional semiconductor layers which are sequentially stacked along the direction from the substrate to the direction away from the substrate on the array area;
a second stack structure disposed on the first stack structure;
the conductive channel structure is arranged on the array region, vertically penetrates through the second stack structure and penetrates into the first stack structure;
the virtual channel structure is arranged on the step area, vertically penetrates through the second stack structure and penetrates into the first stack structure;
and the grid line separation structure vertically penetrates through the second stack structure and extends into the first stack structure, sequentially penetrates through the second stack structure, a plurality of layers of the conventional semiconductor layer at the top of the first stack structure and the second alternative semiconductor layer on the array region, then is in contact with the conventional conductor layer at the bottom of the first stack structure, and sequentially penetrates through the second stack structure, the first alternative semiconductor layer and the conventional semiconductor layer at the middle part of the first stack structure on the step region, and then is in contact with the conventional semiconductor layer at the bottom of the first stack structure.
Optionally, the first stack structure includes, on a partial region of the step region, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer sequentially stacked in a direction from the substrate to a direction away from the substrate, the first stack structure includes, on a partial region of the step region, a first semiconductor layer, a second semiconductor layer, and a fourth semiconductor layer sequentially stacked in a direction from the substrate to a direction away from the substrate, and the first stack structure includes, on the array region, a first semiconductor layer, a fifth semiconductor layer, and a third semiconductor layer sequentially stacked in a direction from the substrate to a direction away from the substrate; wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are the conventional semiconductor layer, the fourth semiconductor layer is the first replacement semiconductor layer, and the fifth semiconductor layer is the second replacement semiconductor layer.
Optionally, the gate line separation structure sequentially passes through the second stack structure, the third semiconductor layer and the fifth semiconductor layer on the array region and then contacts the first semiconductor layer, and the gate line separation structure sequentially passes through the second stack structure, the fourth semiconductor layer and the second semiconductor layer on the step region and then contacts the first semiconductor layer.
Optionally, the conductive channel structure and the dummy channel structure are respectively in contact with the first semiconductor layer.
Optionally, the three-dimensional memory further comprises logic circuitry.
As described above, the method for manufacturing a three-dimensional memory according to the present invention has the following advantages:
replacing part of the conventional semiconductor layer at the top of the first stacked structure on the stepped region with a substitute semiconductor layer, wherein when the conventional semiconductor layer at the top of the first stacked structure is etched, the etching rate of the substitute semiconductor layer is higher than that of the conventional semiconductor layer, so that the etching depths of the etched grid line separation grooves in the array region and the stepped region are different, the etching of the grid line separation grooves on the array region passes through the second stacked structure and then stays in the conventional semiconductor layer at the top of the first stacked structure, and the etching of the grid line separation grooves on the stepped region passes through the second stacked structure and then stays in the conventional semiconductor layer at the bottom of the first stacked structure, therefore, a barrier layer formed on the side wall of the grid line separation grooves subsequently can shield the conventional semiconductor layer at the middle of the first stacked structure on the stepped region, and when the conventional semiconductor layer at the middle of the first stacked structure exposed on the array region is removed by wet etching at the bottom of, the conventional semiconductor layer in the middle of the first stacked structure on the step area is protected by the barrier layer on the side wall of the grid line separation groove, so that the conventional semiconductor layer is not removed, the support framework at the bottom of the step area is strengthened, correspondingly, the support requirement of the virtual channel structure on the step area is simplified, and the process difficulty of the virtual channel structure is reduced.
Drawings
Fig. 1-2 are process flow diagrams illustrating a method for fabricating a three-dimensional memory.
FIG. 3 is a schematic diagram showing a method for fabricating a three-dimensional memory according to the present invention.
Fig. 4-19 are process flow diagrams illustrating a method of fabricating a three-dimensional memory according to the present invention.
Description of the reference numerals
1-substrate, 10-base substrate, 11-composite barrier layer, 2-first stacked structure, 2 '-first stacked structure, 21-first semiconductor layer, 22-second semiconductor layer, 23-third semiconductor layer, 24-fourth semiconductor layer, 25-fifth semiconductor layer, 3-second stacked structure, 3' -second stacked structure, 31-dielectric layer, 32-dummy gate layer, 33-gate layer, 40-barrier layer, 41-gate line separation structure, CH-conductive channel structure, DCH-virtual channel structure, GLS-gate line separation trench.
Detailed Description
The inventor researches and discovers that: in the current production and manufacturing process, as the number of layers increases, the traditional SONO channel hole etching process approaches the bottleneck, and the development of a three-dimensional memory with higher number of layers is restricted by the infinite process problems and reliability problems, particularly the difficulty of SONO channel hole etching is increased by stacking layers above 200 +; therefore, a related process with less SONO channel hole etching is urgently needed to break through the difficulty, and in order to match the related process, as shown in FIG. 1, a first stacked structure 2 is introduced at the bottom of a second stacked structure 3 at the initial stage of the manufacturing process, and the first stacked structure 2 is a composite layer structure of 'polysilicon + silicon nitride + polysilicon'; the weakest link of the three-dimensional memory architecture is after the silicon nitride in the first stacked structure 2 is removed, and in this stage of the current manufacturing process, as shown in fig. 2, the conductive channel structure CH is used for supporting in the array region and the dummy channel structure DCH is used for supporting in the step region.
Therefore, the present invention provides a method for manufacturing a three-dimensional memory, comprising: the top layer of the first stacked structure 2 on the step area is replaced by a material layer with a higher etching selection ratio, so that the etching depths of the etched grid line separation groove in the array area and the step area are different, and based on the etching depths, when the sacrificial layer (generally silicon nitride) in the first stacked structure 2 is removed, the barrier layer formed on the side wall of the grid line separation groove can shield the sacrificial layer in the middle of the first stacked structure 2 on the step area, so that the sacrificial layer cannot be removed, and the support framework at the bottom of the step area is strengthened.
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 3 to 19. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated. The structures, proportions, sizes, and other dimensions shown in the drawings and described in the specification are for understanding and reading the present disclosure, and are not intended to limit the scope of the present disclosure, which is defined in the claims, and are not essential to the art, and any structural modifications, changes in proportions, or adjustments in size, which do not affect the efficacy and attainment of the same are intended to fall within the scope of the present disclosure. In addition, the terms such as "upper", "lower", "middle" and "first" used in the present specification are for clarity of description only, and are not intended to limit the scope of the present invention, and the relative relationship between the terms and the terms is not to be construed as a scope of the present invention unless otherwise specified.
As shown in fig. 3, the present invention provides a method for manufacturing a three-dimensional memory, which comprises the steps of:
s1, providing a substrate 1, wherein the substrate 1 comprises an array area and a step area;
s2, forming a first stacked structure 2 on the substrate 1, the first stacked structure 2 including a plurality of layers of conventional semiconductor layers stacked in sequence along the substrate 1 to a direction away from the substrate 1;
s3, replacing part of the conventional semiconductor layer on the top of the first stacked structure on the step region with a first replacement semiconductor layer;
s4, forming a second stacked structure 3, the second stacked structure 3 covering the first stacked structure 2 and the first replacement semiconductor layer;
s5, forming a grid line separation groove GLS by etching, wherein etching on the array region passes through the second stacked structure 3 and then stays in the conventional semiconductor layer at the top of the first stacked structure 2, and etching on the step region passes through the second stacked structure 3 and the first replacement semiconductor layer and then stays in the conventional semiconductor layer at the bottom of the first stacked structure 2;
wherein, when etching the conventional semiconductor layer on top of the first stacked structure 2, the etching rate of the first replacement semiconductor layer is higher than that of the conventional semiconductor layer.
In detail, as shown in fig. 4, in step S1, the substrate 1 includes a base substrate 10 and a composite barrier layer 11, the composite barrier layer 11 being disposed on the base substrate 10; the base substrate 10 mainly plays a role of structural support, and may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, an SOI substrate, a GOI substrate, or the like, and an appropriate semiconductor material may be selected according to actual requirements of devices, which is not limited herein; the composite barrier layer 11 is a multilayer composite structure, and is mainly used for preventing diffusion between the semiconductor layer 2 and the base substrate 10.
In more detail, as shown in fig. 4, the substrate 1 includes an array region and a step region sequentially arranged in a first direction (i.e., a positive X-axis direction). It will be understood that the actual layout design of the array region and the step region may have many other situations, for example, the two sides of the array region may be respectively provided with the step regions, or the step region may be disposed in the middle of the two array regions, which is not limited herein.
Alternatively, as shown in fig. 5, in step S2, a first stacked structure 2 is formed on the substrate 1, the first stacked structure 2 including the first semiconductor layer 21, the second semiconductor layer 22, and the third semiconductor layer 23 which are sequentially stacked in a direction from the substrate 1 to a direction away from the substrate 1 (i.e., a Z-axis positive direction).
It is understood that the first stacked structure 2 is not limited to the stacked structure of three conventional semiconductor layers as shown in fig. 5, but may be a more complex stacked structure of four layers, five layers, etc., and is not limited thereto; the embodiment of the present invention is merely for convenience, and the specific embodiment will be described by taking a three-layer laminated structure as an example. Alternatively, as shown in fig. 6 to 9, the step S3 of replacing the portion of the conventional semiconductor layer on the top of the first stacked structure 2 on the step region with a first alternative semiconductor layer further includes:
s31, etching the third semiconductor layer 23, and removing at least part of the third semiconductor layer 23 on the step area;
s32, forming a fourth semiconductor layer 24 at the position where the third semiconductor layer 23 is etched and removed, and carrying out surface planarization treatment;
the fourth semiconductor layer 24 is the first alternative semiconductor layer.
In more detail, as shown in fig. 6 to 7, in step S31, the third semiconductor layer 23 is selectively etched, at least the third semiconductor layer 23 on the region where the gate line separation groove GLS is to be etched later is removed, and the third semiconductor layer 23 on a part of the region in the Y-axis direction of the step region is etched away.
In more detail, as shown in fig. 8 to 9, in step S32, the fourth semiconductor layer 24 is formed at a position where the third semiconductor layer 23 is etched away, and surface planarization processing is performed.
Specific materials of the first semiconductor layer 21, the second semiconductor layer 22, the third semiconductor layer 23, and the fourth semiconductor layer 24 are not limited; however, it is necessary to satisfy: when the third semiconductor layer 23 is etched, the etching rate of the fourth semiconductor layer 24 and the etching rate of the second semiconductor layer 22 are respectively higher than the etching rate of the third semiconductor layer 23.
Optionally, the first stacked structure 2 is a composite layer structure of "polysilicon + silicon nitride + polysilicon", that is, the first semiconductor layer 21 and the third semiconductor layer 23 are polysilicon materials, the second semiconductor layer 22 is a silicon nitride material, and the fourth semiconductor layer 24 is a silicon nitride or a silicon oxide material.
In detail, as shown in fig. 10, in step S4, a stacked structure 3 is formed on the first stacked structure 2 having the partial region replaced with the fourth semiconductor layer 24, the stacked structure 3 covering the third semiconductor layer 23 and the fourth semiconductor layer 24; the second stacked structure 3 includes a plurality of dielectric layers 31 and dummy gate layers 32 alternately stacked, one dielectric layer 31 and an adjacent dummy gate layer 32 form a composite layer, that is, the stacked structure 3 includes a plurality of composite layers, and the number of composite layers in the stacked structure 3 can be flexibly designed.
Optionally, after forming the second stacked structure 3 and before etching to form the gate line separation groove GLS, the method for manufacturing the three-dimensional memory further includes:
stp1, etching the second stacked structure 3 and the first stacked structure 2, forming a channel hole on the array region, and forming a virtual channel hole on the step region;
stp2, filling the channel hole to form a conductive channel structure CH; and filling the virtual channel hole to form a virtual channel structure DCH.
The specific layout of the conductive channel structure CH and the virtual channel structure DCH can refer to fig. 2, and the detailed process steps can refer to the prior art and are not described herein again; the conductive channel structure CH and the dummy channel structure DCH respectively vertically penetrate through the stacked structure 3 and penetrate into the semiconductor layer 2, and have a certain supporting effect on the entire three-dimensional memory architecture.
In detail, as shown in fig. 11, in step S5, the second stacked structure 3 and the first stacked structure 2 with the partial region replaced by the fourth semiconductor layer 24 are etched to form the gate line separation grooves GLS, when the third semiconductor layer 23 is etched, the etching rate of the fourth semiconductor layer 24 and the etching rate of the second semiconductor layer 22 are respectively higher than the etching rate of the third semiconductor layer 23, and the relative etching rates of the fourth semiconductor layer 24 and the second semiconductor layer 22 are faster, so that the etching depths of the gate line separation grooves GLS on the array region and the step region are different: the etching on the array region passes through the second stack structure 3 and the third semiconductor layer 23 and then stays on the second semiconductor layer 22, and the etching on the step region passes through the second stack structure 3, the fourth semiconductor layer 24 and the second semiconductor layer 22 and then stays in the first semiconductor layer 21.
In detail, as shown in fig. 12 to 13, the method of manufacturing the three-dimensional memory further includes:
s6, as shown in fig. 12, forming a barrier layer 40 on the bottom and the sidewall of the gate line separation groove GLS;
s7, as shown in fig. 13, the barrier layer 40 at the bottom of the gate line separation groove GLS is removed by etching, and then the etching is continued, and the etching is stopped in the first semiconductor layer 21 to expose the second semiconductor layer 22 on the array region.
Wherein the etch rate of the barrier layer 40 is substantially lower than the etch rate of the second semiconductor layer 22 when the second semiconductor layer 22 is etched.
In detail, as shown in fig. 14 to 15, the method of manufacturing the three-dimensional memory further includes the steps of:
s8, as shown in fig. 14, along the gate line separation groove GLS, the oxidation barrier layer 40 and the portion of the third semiconductor layer 23 near the gate line separation groove GLS;
s9, as shown in fig. 15, the grooves GLS are divided along the gate lines, and the second semiconductor layer 22 on the array region is removed, but the second semiconductor layer 22 on the step region remains.
The second semiconductor layer 22 on the array region is removed by wet etching, and because the etching rate of the barrier layer 40 is significantly lower than that of the second semiconductor layer 22 when the second semiconductor layer 22 is etched, the second semiconductor layer 22 on the step region is protected by the barrier layer 40 on the side wall of the gate line separation groove GLS, so that the second semiconductor layer is not removed by etching, and the support at the bottom of the step region is enhanced.
In addition, after the second semiconductor layer 22 on the array region is removed, the tunneling layer, the charge storage layer and the barrier layer of the conductive channel structure CH in the second semiconductor layer need to be removed to expose the channel layer thereof. In detail, as shown in fig. 16 to 17, the method of manufacturing the three-dimensional memory further includes:
s9, separating the trench GLS along the gate line, forming a fifth semiconductor layer 25 at a position occupied by the second semiconductor layer 22 on the array region by depositing, filling and then etching, forming a common source structure connected to the channel layer in the conductive channel structure CH, and forming the fifth semiconductor layer 25 at the bottom of the gate line trench GLS on the step region to obtain the first stack structure 2'.
In detail, as shown in fig. 17 to 19, the method of manufacturing the three-dimensional memory further includes:
s10, as shown in fig. 17, removing the barrier layer 40 remaining on the bottom and the sidewall of the gate line separation groove GLS, but leaving the barrier layer 40 at the bottom of the gate line separation groove GLS on the step region and covering the portion of the second semiconductor layer 22;
s11, as shown in fig. 18, separating the grooves GLS along the gate lines, and replacing the dummy gate layer 32 in the stack structure 3 with the gate layer 33 by etching and then depositing and filling, so as to obtain a second stack structure 3';
s12, the barrier layer 40 remaining in the gate line separating groove GLS is removed, and a gate line separating structure 41 is formed in the gate line separating groove GLS, as shown in fig. 19.
Based on the above series of steps, finally, a three-dimensional memory as shown in fig. 19 is obtained, which includes:
a substrate 1 including an array region and a step region;
a first stack structure 2' disposed on the substrate 1, including a plurality of layers of conventional semiconductor layers sequentially stacked in a direction from the substrate 1 to a direction away from the substrate 1 (i.e., a positive Z-axis direction) in a partial region of the stepped region, including a plurality of layers of conventional semiconductor layers and a first substitute semiconductor layer sequentially stacked in a direction from the substrate 1 to a direction away from the substrate 1 (i.e., a positive Z-axis direction) in a partial region of the stepped region, and including a plurality of layers of conventional semiconductor layers, a second substitute semiconductor layer and a plurality of layers of conventional semiconductor layers sequentially stacked in a direction from the substrate 1 to a direction away from the substrate 1 (i.e., a positive Z-axis direction) in an array region;
a second stack structure 3 'disposed on the first stack structure 2' and including dielectric layers 31 and gate layers 33 alternately stacked;
the conductive channel structure CH is arranged on the array region, vertically penetrates through the second stack structure 3 'and extends into the first stack structure 2';
the virtual channel structure DCH is arranged on the step area, vertically penetrates through the second stack structure 3 'and extends into the first stack structure 2';
the gate line separation structure 41 vertically penetrates through the second stack structure 3 'and goes deep into the first stack structure 2', sequentially penetrates through the second stack structure 3', a plurality of layers of conventional semiconductor layers and second substitute semiconductor layers at the top of the first stack structure 2' in the array region, then contacts with the conventional conductor layer at the bottom of the first stack structure 2', and sequentially penetrates through the second stack structure 3', the first substitute semiconductor layer and a part of the conventional semiconductor layers at the middle of the first stack structure 2 'in the step region, then contacts with the conventional semiconductor layer at the bottom of the first stack structure 2'.
The specific structures of the conductive channel structure CH and the dummy channel structure DCH are not shown in the figure, and referring to fig. 2, the conductive channel structure CH and the dummy channel structure DCH are respectively in contact with the first semiconductor layer 21, which has a certain supporting effect on the entire structure.
Alternatively, as shown in fig. 17 to 19, in an embodiment of the present invention, the first stack structure 2 'includes a first semiconductor layer 21, a second semiconductor layer 22, and a third semiconductor layer 23 sequentially stacked in a direction from the substrate 1 to a direction away from the substrate 1 on a partial region of the stepped region, the first stack structure 2' includes a first semiconductor layer 21, a second semiconductor layer 22, and a fourth semiconductor layer 24 sequentially stacked in a direction from the substrate 1 to a direction away from the substrate 1 on a partial region of the stepped region, and the first stack structure includes a first semiconductor layer 21, a fifth semiconductor layer 25, and a third semiconductor layer 23 sequentially stacked in a direction from the substrate 1 to a direction away from the substrate 1 on the array region; wherein the first semiconductor layer 21, the second semiconductor layer 22 and the third semiconductor layer 23 are conventional semiconductor layers, the fourth semiconductor layer 24 is a first substitute semiconductor layer, and the fifth semiconductor layer 25 is a second substitute semiconductor layer.
In detail, as shown in fig. 19, the gate line separating structure 41 sequentially passes through the second stack structure 3', the third semiconductor layer 23, and the fifth semiconductor layer 25 on the array region and then contacts the first semiconductor layer 21, and the gate line separating structure 41 sequentially passes through the second stack structure 3', the fourth semiconductor layer 24, and the second semiconductor layer 22 on the step region and then contacts the first semiconductor layer 21. In detail, the three-dimensional memory further includes a logic circuit electrically connected to the memory array structure or the external control signal through the metal interconnection structure, wherein the memory array structure is the semiconductor structure formed in steps S1 to S12, and details thereof are not repeated herein.
In summary, in the manufacturing method of the three-dimensional memory and the three-dimensional memory provided by the present invention, because a portion of the conventional semiconductor layer on the top of the first stacked structure on the step region is replaced by the substitute semiconductor layer, and when the conventional semiconductor layer on the top of the first stacked structure is etched, the etching rate of the substitute semiconductor layer is higher than that of the conventional semiconductor layer, so that the etching depths of the gate line separation grooves formed by etching are different between the array region and the step region, the etching of the gate line separation grooves on the array region passes through the second stacked structure and then stays in the conventional semiconductor layer on the top of the first stacked structure, and the etching of the gate line separation grooves on the step region passes through the second stacked structure and then stays in the conventional semiconductor layer on the bottom of the first stacked structure, based on this, the barrier layer formed on the sidewall of the gate line separation grooves subsequently can shield the conventional semiconductor layer in the middle of the first, when the conventional semiconductor layer in the middle of the first stacked structure exposed on the array region is removed through wet etching at the bottom of the grid line separation groove, the conventional semiconductor layer in the middle of the first stacked structure on the step region is protected by the barrier layer protection column on the side wall of the grid line separation groove, so that the conventional semiconductor layer is not removed, the support framework at the bottom of the step region is strengthened, the support requirement of the virtual channel structure on the step region is correspondingly simplified, and the process difficulty of the virtual channel structure is reduced.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (15)
1. A method of fabricating a three-dimensional memory, comprising:
providing a substrate, wherein the substrate comprises an array area and a step area;
forming a first stacked structure on the substrate, wherein the first stacked structure comprises a plurality of layers of conventional semiconductor layers which are sequentially stacked along the direction from the substrate to a direction far away from the substrate;
replacing a portion of the conventional semiconductor layer on top of the first stacked structure on the step region with a first replacement semiconductor layer;
forming a second stacked structure covering the first stacked structure and the first replacement semiconductor layer;
etching to form a grid line separation groove, wherein the etching on the array region passes through the second stacked structure and then stays in the conventional semiconductor layer at the top of the first stacked structure, and the etching on the step region passes through the second stacked structure and the first substitute semiconductor layer and then stays in the conventional semiconductor layer at the bottom of the first stacked structure;
wherein, when the conventional semiconductor layer on the top of the first stacked structure is etched, the etching rate of the first substitute semiconductor layer is higher than that of the conventional semiconductor layer.
2. The method according to claim 1, wherein the first stacked structure includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer which are stacked in this order in a direction from the substrate to a direction away from the substrate.
3. The method of claim 2, wherein replacing the portion of the normal semiconductor layer on top of the first stacked structure on the step region with the first replacement semiconductor layer comprises:
etching the third semiconductor layer, and removing at least part of the third semiconductor layer on the step region;
forming the fourth semiconductor layer at the position where the third semiconductor layer is etched and removed, and carrying out surface planarization treatment;
wherein the fourth semiconductor layer is the first alternative semiconductor layer.
4. The method of claim 3, wherein after the forming the second stacked structure and before the etching to form the gate line separating trench, the method further comprises:
etching the second stacked structure and the first stacked structure, forming a channel hole on the array region, and forming a virtual channel hole on the step region;
filling the channel hole to form a conductive channel structure; and filling the virtual channel hole to form a virtual channel structure.
5. The method of claim 4, wherein the etching on the array region passes through the second stacked structure and the third semiconductor layer and then stays on the second semiconductor layer, and the etching on the step region passes through the second stacked structure, the fourth semiconductor layer and the second semiconductor layer and then stays in the first semiconductor layer when the gate line separation groove is formed by etching.
6. The method according to claim 5, wherein an etching rate of the fourth semiconductor layer and an etching rate of the second semiconductor layer are respectively higher than an etching rate of the third semiconductor layer when the third semiconductor layer is etched.
7. The method of manufacturing a three-dimensional memory according to claim 6, further comprising:
forming barrier layers at the bottom and on the side wall of the grid line separation groove;
and continuously etching after removing the barrier layer at the bottom of the grid line separation groove by etching, stopping etching in the first semiconductor layer and exposing the second semiconductor layer on the array region.
8. The method of manufacturing a three-dimensional memory according to claim 7, further comprising:
and separating the groove along the grid line, removing the second semiconductor layer on the array region, and remaining the second semiconductor layer on the step region.
9. The method of manufacturing a three-dimensional memory according to claim 8, further comprising:
and forming a fifth semiconductor layer at a position occupied by the second semiconductor layer on the array region along the gate line separation groove.
10. The method of manufacturing a three-dimensional memory according to claim 9, wherein the second stacked structure comprises a plurality of alternately arranged dummy gate layers and dielectric layers, and after forming the fifth semiconductor layer, the method further comprises:
and separating grooves along the grid lines, and replacing the dummy grid layer with a grid layer.
11. A three-dimensional memory, comprising:
a substrate including an array region and a step region;
the first stack structure is arranged on the substrate, comprises a plurality of layers of conventional semiconductor layers which are sequentially stacked along the direction from the substrate to the direction away from the substrate on the partial area of the stepped area, comprises a plurality of layers of the conventional conductor layers and a layer of first substitute semiconductor layer which are sequentially stacked along the direction from the substrate to the direction away from the substrate on the partial area of the stepped area, and comprises a plurality of layers of the conventional semiconductor layers, a layer of second substitute semiconductor layers and a plurality of layers of the conventional semiconductor layers which are sequentially stacked along the direction from the substrate to the direction away from the substrate on the array area;
a second stack structure disposed on the first stack structure;
the conductive channel structure is arranged on the array region, vertically penetrates through the second stack structure and penetrates into the first stack structure;
the virtual channel structure is arranged on the step area, vertically penetrates through the second stack structure and penetrates into the first stack structure;
and the grid line separation structure vertically penetrates through the second stack structure and extends into the first stack structure, sequentially penetrates through the second stack structure, a plurality of layers of the conventional semiconductor layer at the top of the first stack structure and the second alternative semiconductor layer on the array region, then is in contact with the conventional conductor layer at the bottom of the first stack structure, and sequentially penetrates through the second stack structure, the first alternative semiconductor layer and the conventional semiconductor layer at the middle part of the first stack structure on the step region, and then is in contact with the conventional semiconductor layer at the bottom of the first stack structure.
12. The three-dimensional memory according to claim 11, wherein the first stack structure includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer which are sequentially stacked in a direction from the substrate to away from the substrate in a partial region of the stepped region, the first stack structure includes a first semiconductor layer, a second semiconductor layer, and a fourth semiconductor layer which are sequentially stacked in a direction from the substrate to away from the substrate in a partial region of the stepped region, and the first stack structure includes a first semiconductor layer, a fifth semiconductor layer, and a third semiconductor layer which are sequentially stacked in a direction from the substrate to away from the substrate in the array region; wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are the conventional semiconductor layer, the fourth semiconductor layer is the first replacement semiconductor layer, and the fifth semiconductor layer is the second replacement semiconductor layer.
13. The three-dimensional memory according to claim 12, wherein the gate line separating structure contacts the first semiconductor layer after sequentially passing through the second stack structure, the third semiconductor layer and the fifth semiconductor layer in the array region, and the gate line separating structure contacts the first semiconductor layer after sequentially passing through the second stack structure, the fourth semiconductor layer and the second semiconductor layer in the step region.
14. The three-dimensional memory according to claim 13, wherein the conductive channel structure and the dummy channel structure are respectively in contact with the first semiconductor layer.
15. The three-dimensional memory according to claim 13 or 14, wherein the three-dimensional memory further comprises logic circuitry.
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