CN112464614A - Method for optimizing integrated circuit layout heat distribution by splitting transistor - Google Patents
Method for optimizing integrated circuit layout heat distribution by splitting transistor Download PDFInfo
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- CN112464614A CN112464614A CN202110043219.XA CN202110043219A CN112464614A CN 112464614 A CN112464614 A CN 112464614A CN 202110043219 A CN202110043219 A CN 202110043219A CN 112464614 A CN112464614 A CN 112464614A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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Abstract
The invention relates to a method for optimizing integrated circuit layout heat distribution by splitting a transistor, belonging to the field of integrated circuit design. The method comprises the steps of splitting all transistors of a circuit into transistors with the same size by splitting the transistors, carrying out circuit simulation on the split transistors, and extracting current and power consumption parameters of each tube; carrying out heat distribution analysis on the models by establishing the models with the same power and the same size to obtain the self-heating value and heat diffusion relation; and comprehensively considering the thermal diffusion relation and the physical layout rule of the circuit to obtain an optimized layout placing mode.
Description
Technical Field
The invention belongs to the technical field of integrated circuit design, and further relates to a method for optimizing heat distribution of an integrated circuit layout.
Background
In integrated circuit designs, devices are sensitive to temperature, and increased temperature can degrade device performance and reliability. Therefore, it is important to improve the performance of the circuit and suppress hot spots by properly laying out the circuit. Due to the adoption of transistors with different sizes in the full-custom circuit, the overall circuit is not uniformly thermally distributed, and hot spots are easily generated at the large-size transistor (group). Meanwhile, analysis of the mutual heating effect of devices with different sizes and shapes in the circuit is limited, a universal and accurate thermal analysis model cannot be established, and therefore the thermal analysis model can be effectively and reasonably expanded to be applied to actual thermal layout optimization of the simulation IC.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention aims to provide a method for optimizing the heat distribution of an integrated circuit layout. The method comprises the steps of splitting all transistors of a circuit into transistors with the same size by splitting the transistors, carrying out circuit simulation on the split transistors, and extracting current and power consumption parameters of each tube; carrying out heat distribution analysis on the models by establishing the models with the same power and the same size to obtain the self-heating value and heat diffusion relation; and comprehensively considering the thermal diffusion relation and the physical layout rule of the circuit to obtain an optimized layout placing mode.
In order to achieve the purpose, the invention adopts the specific scheme that:
a method for optimizing integrated circuit layout thermal distribution by splitting transistors, comprising the steps of:
the method comprises the following steps: splitting all transistors of the circuit into unit transistors with the same size;
step two, performing circuit simulation on the unit transistors split in the step one, verifying whether the functions and the performances of the circuit reach the standard, and extracting the current and the power consumption parameters of each unit transistor after splitting;
establishing an equivalent model of the split unit transistor, and carrying out heat distribution analysis on the equivalent model to obtain the self-heating value and the heat diffusion relation of the unit transistor;
and fourthly, according to the thermal diffusion relation, combining with the constraint of physical design rules to be followed by layout design, carrying out size adjustment and stretching of device intervals, and finally dispersing hot spots to optimize thermal layout.
Specifically, the specific method of the step one is as follows: all transistor parameters in the circuit are obtained from the Cadence, common divisor of channel width-length ratio is taken, and then the transistors with the same size are split. Further, for the splitting of a large-sized transistor, the longitudinal or lateral splitting of the channel is performed. The longitudinal or transverse split is preferably a halved split, a quartered split, an octanted split or a sixteen split.
Specifically, the equivalent model in step three refers to a model with the same power and the same size as the split cell transistor.
Has the advantages that:
the invention optimizes the thermal layout of the simulation IC by splitting the transistor devices with full customized sizes in the simulation IC into unit devices with the same size and combining the thermal equivalent modeling and the spacing adjustment of the devices.
Drawings
FIG. 1 is a schematic diagram of a layout channel lateral split; wherein (a) is a fully-customized device; (b) splitting in two halves; (c) splitting the four parts;
FIG. 2 is a schematic diagram of longitudinal split of a layout channel; wherein (a) is a fully-customized device; (b) splitting in two halves; (c) splitting the four parts;
FIG. 3 is a graph of heat generation versus channel area;
FIG. 4 is a graph of thermal diffusion relationships;
FIG. 5 is an Ansys equivalent thermal model diagram;
FIG. 6 is a cloud chart of the heat released by the MOS tube split and the equal spacing pendulum;
FIG. 7 is a flow chart of a method for optimizing thermal distribution of an integrated circuit layout according to the present invention.
Detailed Description
A method for optimizing integrated circuit layout thermal distribution by splitting transistors:
firstly, transistors with different sizes are used in a traditional full-custom analog IC layout, and all the transistors are split into unit transistors with the same size;
then, obtaining current and power consumption parameters of each split transistor through actual circuit function simulation and performance standard analysis;
then, establishing a thermal equivalent model in ANSYS, obtaining the temperature of the individual device, and determining the temperature distribution of the whole circuit;
and finally, according to the position of the hot spot, combining with the constraint of a physical design rule to be followed by layout design, carrying out size adjustment and stretching of the device interval, and finally dispersing the hot spot to optimize the thermal layout.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention.
Example 1
The method for optimizing the heat distribution of the integrated circuit layout by splitting the transistor comprises the following specific operation steps:
all transistor parameters for designing a traditional full-custom circuit are obtained from Cadence, and are divided into transistors with the same size by taking an appropriate common divisor of a channel width-to-length ratio (for the division of the large-size transistor, the channel can be divided longitudinally or transversely, and usually 2/4/8/16 equal divisions are performed, as shown in fig. 1 and fig. 2).
And putting the split transistor into Cadence for circuit simulation, verifying whether the function and performance of the circuit reach the standard, and extracting the current and power consumption parameters of the tube.
By establishing a model with the same power and the same size as the split transistor in the circuit through Ansys, the specific temperature of the split unit transistor is obtained, and the heating relation of the unit transistor is obtained, so that the relationship between the heating value of the device and the channel area of the device is found (as shown in fig. 3).
The unit transistor model is analyzed for the transverse and longitudinal heat distribution respectively, and the result that the heat diffusion of the circuit is in a negative exponential relation with the heat along with the increase of the distance (as shown in fig. 4).
And verifying the thermal diffusion relation of the circuit, acquiring the actual heating value of the circuit by using an equidistant model (such as figure 5), and comparing the actual heating value with the calculation result of the thermal diffusion relation to correct the thermal diffusion relation.
The relative dispersion of the modules with larger heat productivity in the model is placed, the heat productivity of the circuit is measured again, the function of the circuit is verified, the sum of the displacement vectors caused by the highest temperature before splitting is obviously 0.141178, the sum of the displacement vectors caused by the highest temperature after splitting is 0.102374, the overall temperature rise of the circuit is obviously reduced, and the circuit function is normally realized (as shown in fig. 6).
It should be noted that the above-mentioned embodiments illustrate rather than limit the scope of the invention, which is defined by the appended claims. It will be apparent to those skilled in the art that certain insubstantial modifications and adaptations of the present invention can be made without departing from the spirit and scope of the invention.
Claims (5)
1. A method for optimizing integrated circuit layout heat distribution by splitting transistors is characterized in that: the method comprises the following steps:
the method comprises the following steps: splitting all transistors of the circuit into unit transistors with the same size;
step two, performing circuit simulation on the unit transistors split in the step one, verifying whether the functions and the performances of the circuit reach the standard, and extracting the current and the power consumption parameters of each unit transistor after splitting;
establishing an equivalent model of the split unit transistor, and carrying out heat distribution analysis on the equivalent model to obtain the self-heating value and the heat diffusion relation of the unit transistor;
and fourthly, according to the thermal diffusion relation, combining with the constraint of physical design rules to be followed by layout design, carrying out size adjustment and stretching of device intervals, and finally dispersing hot spots to optimize thermal layout.
2. The method of claim 1 for optimizing integrated circuit layout thermal distribution by splitting transistors, wherein: the specific method of the step one is as follows: all transistor parameters in the circuit are obtained from the Cadence, common divisor of channel width-length ratio is taken, and then the transistors with the same size are split.
3. The method of claim 2 for optimizing integrated circuit layout thermal distribution by splitting transistors, wherein: for the splitting of a large-sized transistor, the longitudinal or lateral splitting of a channel is performed.
4. The method of claim 3 for optimizing integrated circuit layout thermal distribution by splitting transistors, wherein: the longitudinal or transverse split is divided into a halving split, a quartering split, an octating split or a sixteen splitting split.
5. The method of claim 1 for optimizing integrated circuit layout thermal distribution by splitting transistors, wherein: and step three, the equivalent model refers to a model with the same power and the same size as the split unit transistor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110043219.XA CN112464614A (en) | 2021-01-13 | 2021-01-13 | Method for optimizing integrated circuit layout heat distribution by splitting transistor |
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| CN202110043219.XA CN112464614A (en) | 2021-01-13 | 2021-01-13 | Method for optimizing integrated circuit layout heat distribution by splitting transistor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115952764A (en) * | 2023-03-10 | 2023-04-11 | 成都明夷电子科技有限公司 | Transistor circuit for improving heat dissipation performance of amplifier chip and optimization method |
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2021
- 2021-01-13 CN CN202110043219.XA patent/CN112464614A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115952764A (en) * | 2023-03-10 | 2023-04-11 | 成都明夷电子科技有限公司 | Transistor circuit for improving heat dissipation performance of amplifier chip and optimization method |
| CN115952764B (en) * | 2023-03-10 | 2023-07-14 | 成都明夷电子科技有限公司 | Transistor circuit optimization method for improving heat dissipation performance of amplifier chip |
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