CN112463213A

CN112463213A - Method and device for updating and reading statistical value

Info

Publication number: CN112463213A
Application number: CN201910844090.5A
Authority: CN
Inventors: 崔秀梅
Original assignee: Beijing Jingdong Century Trading Co Ltd; Beijing Jingdong Shangke Information Technology Co Ltd
Current assignee: Beijing Jingdong Century Trading Co Ltd; Beijing Jingdong Shangke Information Technology Co Ltd
Priority date: 2019-09-06
Filing date: 2019-09-06
Publication date: 2021-03-09
Anticipated expiration: 2039-09-06
Also published as: CN112463213B

Abstract

The invention discloses a method and a device for updating and reading a statistical value, and relates to the technical field of computers. One embodiment of the method comprises: acquiring a statistic set to be updated; for each statistical element in the set of statistical values, determining a storage unit in an idle state that matches the statistical element; and writing the statistical element into a storage unit in an idle state to finish updating the statistical value. The implementation mode overcomes the technical problems of low statistical efficiency and high requirement on hardware performance caused by the fact that access to the same address needs to wait for the next updating operation after the previous operation is finished, and further achieves the technical effect that the statistical operation can be efficiently executed by adopting a relatively low-speed memory.

Description

Method and device for updating and reading statistical value

Technical Field

The invention relates to the technical field of computers, in particular to a method and a device for updating and reading statistical values.

Background

Statistical functions are functions that are very common in various devices, e.g. for billing positioning problems, etc. As device performance increases, statistical performance and capacity requirements increase, and the performance of many devices is limited by memory performance.

The prior art adopts the following two schemes:

scheme 1, adopting RAM with higher performance or using register to store statistic value;

and 2, completing low-order statistics in the high-speed RAM, and accumulating the low-order statistics in the low-speed RAM with wider bit width when carrying is available.

In the process of implementing the invention, the inventor finds that at least the following problems exist in the prior art:

for scheme 1: the requirement on hardware resources is high, the cost is high, and the capacity is not easy to be enlarged;

for scheme 2: when the capacity required by the data to be counted is large, the demand for a high-speed RAM is large, resulting in high cost.

Disclosure of Invention

In view of this, embodiments of the present invention provide a method and an apparatus for updating and reading a statistical value, which can overcome the technical problems of low statistical efficiency and high requirement on hardware performance caused by the fact that access to the same address needs to wait for the completion of a previous operation and then start a next update operation, thereby achieving the technical effect of efficiently performing a statistical operation by using a relatively low-speed memory.

To achieve the above object, according to an aspect of an embodiment of the present invention, there is provided a method of updating a statistical value, including:

acquiring a statistic set to be updated;

for each statistical element in the set of statistical values, determining a storage unit in an idle state that matches the statistical element;

and writing the statistical element into a storage unit in an idle state to finish updating the statistical value.

Optionally, for each statistic element in the set of statistic elements, determining a storage unit in an idle state matching the statistic element includes:

for each statistical element in the statistical value set, determining a storage unit set matched with the statistical element;

and determining the storage unit in the idle state matched with the statistical element according to the address of the storage unit set.

Optionally, writing the statistical element into a storage unit in an idle state, and completing updating the statistical value, including:

determining an address of a memory cell in an idle state;

and writing the statistical element into the storage unit in the idle state according to the address of the storage unit in the idle state to finish updating the statistical value.

Optionally, the base addresses of the elements in the storage unit set are different, and the offset addresses are the same.

According to another aspect of the embodiments of the present invention, there is provided a method for reading statistical values, including:

acquiring all storage units for storing statistical values to be read;

accumulating the numerical values stored in the storage unit;

and determining the accumulated numerical value as a statistical value to be read.

Optionally, acquiring all storage units storing the statistical value to be read includes:

acquiring a storage unit set matched with the statistical value to be read;

determining addresses of all storage units in the storage unit set according to the addresses of the storage unit set;

and determining the storage units with numerical values in the storage unit set according to the addresses of all the storage units.

According to another aspect of the embodiments of the present invention, there is provided an apparatus for updating statistics, including:

the set acquisition module is used for acquiring a statistic set to be updated;

a storage unit determining module, configured to determine, for each statistical element in the statistical value set, a storage unit in an idle state that matches the statistical element;

and the statistic value updating module is used for writing the statistic elements into the storage unit in an idle state to finish updating the statistic values.

According to another aspect of the embodiments of the present invention, there is provided an apparatus for reading statistical values, including:

the storage unit acquisition module is used for acquiring all storage units for storing the statistical values to be read;

the accumulation module is used for accumulating the numerical values stored in the storage unit;

and the reading module determines the accumulated numerical value as a statistical value to be read.

According to another aspect of the embodiments of the present invention, there is provided an electronic device for updating or reading statistics, including:

one or more processors;

a storage device for storing one or more programs,

when the one or more programs are executed by the one or more processors, the one or more processors implement the method for updating or reading statistics provided by the present invention.

According to yet another aspect of embodiments of the present invention, there is provided a computer readable medium, on which a computer program is stored, which when executed by a processor implements the method for updating or reading statistics provided by the present invention.

One embodiment of the above invention has the following advantages or benefits:

by adopting the technical means of storing each statistical element in the statistical value set in the storage unit in the idle state in parallel, the method and the device overcome the technical problems of low statistical efficiency and high requirement on hardware performance caused by the fact that access to the same address needs to wait for the next updating operation after the previous operation is finished, and further achieve the technical effect of efficiently executing the statistical operation by adopting a relatively low-speed memory.

Further effects of the above-mentioned non-conventional alternatives will be described below in connection with the embodiments.

Drawings

The drawings are included to provide a better understanding of the invention and are not to be construed as unduly limiting the invention. Wherein:

FIG. 1 is a schematic diagram illustrating a main flow of a method for updating a statistical value according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a main flow of a method for reading statistics according to an embodiment of the present invention;

FIG. 3 is a block diagram of the major modules of an apparatus for updating a statistical value according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating the main blocks of an apparatus for reading statistics according to an embodiment of the present invention;

FIG. 5 is an exemplary system architecture diagram in which embodiments of the present invention may be employed;

fig. 6 is a schematic block diagram of a computer system suitable for use in implementing a terminal device or server of an embodiment of the invention.

Detailed Description

Exemplary embodiments of the present invention are described below with reference to the accompanying drawings, in which various details of embodiments of the invention are included to assist understanding, and which are to be considered as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the invention. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

The prior art generally implements the statistical function in the following ways: and distributing the statistic value X to a storage unit, wherein the storage Address of the storage unit is Address _ X. And when the statistic value of X needs to be increased, reading the statistic value in the Address _ X Address, accumulating the statistic value to be increased, and writing back the statistic value to the storage unit corresponding to the storage Address _ X.

To avoid statistical errors, the update operation usually needs to be an atomic operation, i.e. an access to the same address needs to wait for the previous operation to complete before starting the next update operation.

When the statistics are stored in a DRAM (DYnamic Random Access MemorY), due to the physical characteristics of the DRAM, the interval tRC time is required to update the statistics in the same bank, which greatly limits the performance of the statistics.

Wherein, the bank is a memory structure specific to all DRAMs and is a hardware concept; the trc (dram Row CYcle time) is a Row CYcle time, which defines a minimum time between two Row activation commands of the same bank, or a time for completing one Row operation CYcle (Row CYcle) in one bank, i.e., tRP + tRAS (a whole process of precharge plus activation).

However, the solution of the present application aims at: the relatively low-speed Random Access Memory (RAM) is used for completing higher-speed statistics, and further the technical effects of reducing the requirement of hardware resources, increasing the capacity of storing statistical values and reducing the production cost are achieved.

Wherein the relatively low speed Random Access Memory (RAM) includes, but is not limited to: DDR (Double Data Rate SDRAM), RLD RAM (low latency DRAM), eDRAM (enhanced dYnamic random access memorY) and the like.

Fig. 1 is a schematic diagram illustrating a main flow of a method for updating a statistical value according to an embodiment of the present invention, as shown in fig. 1, including:

s101, acquiring a statistic set to be updated;

step S102, for each statistical element in the statistical value set, determining a storage unit which is matched with the statistical element and is in an idle state;

and step S103, writing the statistical element into a storage unit in an idle state to finish updating the statistical value.

The statistical value set refers to a data set to be updated to a statistical value storage position;

wherein the elements in the set of statistics may be of multiple types, including: one or more data stored at one memory address, a plurality of data stored at different memory addresses.

Different from the prior art, if the statistical element is written into the storage unit and is limited by the tRC, the scheme allocates the statistical value stored in the storage device to a plurality of storage units. For example, the actually allocated memory Address of the statistical value X may be any one of the Address _ X0 to Address _ Xn (n is equal to or greater than 1) that is in an idle state. When there are multiple updates to the statistical value X in the statistical value set at the same time, the elements (specifically, for example, X0 and X1) in the statistical value set to the statistical value X may be written into the memory cells in the idle state in the Address _ X0 to Address _ Xn, respectively and in parallel. Since X0 and X1 are written into different memory cells in idle state, 2 parallel atomic operations are generated, and the technical defect that the memory cell needs to wait at least one tRC for subsequent update operations is overcome. In actual production, the condition of updating the same statistical value is more frequent, and the technical defects of low efficiency of serial updating statistical value and high requirement on the performance of the memory can be reduced by the method.

By setting the base addresses of the elements to be different, the restriction of bank is broken when the memory is a DRAM, and the restriction of tRC when updating the statistical value is avoided.

Corresponding to the updated statistic value, when reading the statistic value, the data in the storage units of all storage addresses corresponding to the statistic value to be read can be read in parallel without being limited by tRC, and the statistic value is obtained by accumulation.

Because one statistical value corresponds to a plurality of storage units, and offset addresses corresponding to the storage units are the same, the statistical value can be combined with all the storage units to form a set, which is called a storage unit set.

In particular, therefore, for each statistical element of the set of statistical values, determining a memory cell in an idle state that matches the statistical element comprises:

Since it is necessary to determine the address corresponding to the sibling element when the statistical element is written into the storage unit in the idle state, specifically, writing the statistical element into the storage unit in the idle state to update the statistical value includes:

determining an address of a memory cell in an idle state;

The following two specific examples compare in detail the differences between the prior art and the solution of the present application:

TABLE 1 schematic table stored for memory used in the prior art

Bank0 Bank1 Bank2…Bankn

Address_X

Address_Y

Address_Z

TABLE 2 memory storage schematic table for this scheme

Bank0 Bank1 Bank2…Bankn

Address_X0	Address_X1	Address_X2	Address_Xn

Address_Y0	Address_Y1	Address_Y2	Address_Yn

Address_Z0	Address_Z1	Address_Z2	Address_Zn

Specific example 1:

the following first embodiment is used to compare the differences between the prior art and the solution of the present application in detail:

assuming that a memory used for statistics is a DRAM, the time consumed for completing the operations of reading, writing or modifying on a memory cell corresponding to an address in the DRAM is t;

in this embodiment, three elements exist in the obtained statistical value set to be updated, which all correspond to the statistical value X, where the three elements are: x1, X2, X3.

As shown in table 1 above, in the prior art, the statistic value X is only stored in one storage unit corresponding to Address _ X, and when the statistics of the above three elements is performed, it is necessary to consider "atomic operation", and after the X1 completes the statistics storage to the Address, the statistics and storage of X2 are performed,

and then counting and storing the X3. Therefore, the time consumed by the prior art to complete the statistics of the three elements is 3 t.

Unlike the prior art, as shown in table 2 above, the steps of this scheme are as follows:

firstly, determining that three elements in a statistical value set to be updated all correspond to a statistical value X;

then, different base addresses are selected according to the three elements to avoid the limitation of tRC, and specifically, the calculated statistical addresses corresponding to the three elements are respectively dispersed to three different addresses to operate, and specifically, the operation addresses are Address _ X0, Address _ X1 and Address _ X2. Since the addresses are different and the corresponding memory cells are different, the subsequent X1 and X2 are not limited by X0 and are not influenced by the atomic operation principle, and the addresses are distributed in different banks and are not limited by the physical characteristics (such as tRC) of accessing the same bank during access.

And finally, writing the three elements into corresponding storage units of Address _ X0, Address _ X1 and Address _ X2 respectively. The scheme reduces the performance loss caused by atomic operation, and further greatly improves the final statistical performance; where the total time consumed by the statistical operation should be t.

This embodiment may improve performance by a factor of p q times that of the prior art. Wherein p is a parameter for improving statistical performance after the bank of the same statistical value is copied, the specific data depends on the bank distribution state of the statistical value, and max (p) is n; and q is the improvement of the statistical performance after eliminating the atomic operation, and the specific numerical value depends on the continuous distribution state of the statistical value.

Specific example 2:

the following second embodiment is used to compare the differences between the prior art and the solution of the present application in detail:

still assuming that the memory used for statistics is a DRAM, the time consumed for completing the operations of reading, writing or modifying on the memory cell corresponding to an address in the DRAM is t;

in this embodiment, three elements X0, Y0, and Z0 in the obtained statistical value set to be updated respectively correspond to the statistical value X, Y, Z;

as shown in table 1 above, the statistics X, Y, Z are distributed in the same bank in the prior art. When counting each statistic, it is necessary to wait for the previous statistic to complete the read or update operation, and it is necessary to wait for tRC time to match the timing of the DRAM. In this embodiment, the processing time for DRAM bank increase limit is (3 x 2-1) tRC.

Unlike the prior art, as shown in table 2 above, the steps of the present solution are as follows:

firstly, three elements in the obtained statistic value set to be updated respectively correspond to statistic values X, Y, Z;

then, different base addresses are selected according to the three elements to avoid the limitation of tRC, and specifically, the statistical addresses corresponding to the three elements are obtained by calculation, namely Address _ X0, Address _ Y1 and Address _ Z2. Because the Address _ X0, the Address _ Y1 and the Address _ Z2 are respectively distributed on different banks, the access is not limited by the physical characteristics of the same bank, and the final statistical performance can be greatly improved.

Finally, writing an element corresponding to Address _ X0 into a storage unit of Address _ X0; writing an element corresponding to Address _ Y1 into a storage unit of Address _ Y1; an element corresponding to Address _ Z2 is written into the memory cell of Address _ Z2.

Since the statistics are stored in all banks, the three statistics can schedule read overwrite for 3 different bank addresses (Address _ X0, Address _ Y1, Address _ Z2), and the following statistics can continue without waiting for tRC, the total completion time is t.

Therefore, in the embodiment, since the influence of the statistical value distribution on the performance is also reduced on the same bank, the DRAM can fully utilize the bandwidth of all the banks, and the performance improvement amplitude of the embodiment may be p times that of the prior art. Wherein p is a promotion parameter of the statistical performance after the bank of the same statistical value is copied, the specific data depends on the bank distribution state of the statistical value, and max (p) -n.

Fig. 2 is a schematic diagram of a main flow of a method for reading statistics according to an embodiment of the present invention, as shown in fig. 2, including:

step S201, acquiring all storage units for storing statistical values to be read;

step S202, accumulating the numerical values stored in the storage unit;

and step S203, determining the accumulated numerical value as a statistical value to be read.

The number of times of reading the statistical value may be spaced for a long time, and the above steps may be adopted for reading the statistical value in a manner of updating the statistical value.

Taking the above table 1 as an example, in the prior art, when reading the value of the statistical value X, the data stored in Address _ X needs to be read.

Specifically, the value of the statistical value X is value in Address _ X;

the value of the statistical value Y is value in Address _ Y;

the value of the statistical value Z is value in Address Z.

Taking the table 2 as an example, when reading the value of the statistical value X, the present invention needs to take out and accumulate the values in all the addresses matched with the statistical value X, and the accumulated value is the value of the statistical value X.

Specifically, the value of the statistical value X is value in Address _ X0+ value in Address _ X1+ value in Address _ X2+ … + value in Address _ Xn;

the value of the statistical value Y is value in Address _ Y0+ value in Address _ Y1+ value in Address _ Y2+ … + value in Address _ Yn;

the value of the statistical value Z is value in Address _ Z0+ value in Address _ Z1+ value in Address _ Z2+ … + value in Address _ Zn.

acquiring a storage unit set matched with the statistical value to be read;

Fig. 3 is a schematic diagram of main modules of an apparatus 300 for updating a statistical value according to an embodiment of the present invention, as shown in fig. 3, including:

a set obtaining module 301, configured to obtain a statistic set to be updated;

a storage unit determining module 302, configured to determine, for each statistical element in the statistical value set, a storage unit in an idle state that matches the statistical element;

a statistic value updating module 303, configured to write the statistic element into a storage unit in an idle state, so as to complete updating of the statistic value.

Fig. 4 is a schematic diagram of main blocks of an apparatus 400 for reading statistics according to an embodiment of the present invention, as shown in fig. 4, including:

a storage unit obtaining module 401, configured to obtain all storage units storing statistics to be read;

an accumulation module 402, configured to accumulate the numerical values stored in the storage unit;

the reading module 403 determines the accumulated value as the statistic to be read.

FIG. 5 illustrates an exemplary system architecture 500 to which the update, read statistics method or update, read statistics apparatus of embodiments of the invention may be applied.

As shown in fig. 5, the system architecture 500 may include

terminal devices

501, 502, 503, a network 504, and a server 505. The network 504 serves to provide a medium for communication links between the

terminal devices

501, 502, 503 and the server 505. Network 504 may include various connection types, such as wired, wireless communication links, or fiber optic cables, to name a few.

The user may use the

terminal devices

501, 502, 503 to interact with a server 505 over a network 504 to receive or send messages or the like. The

terminal devices

501, 502, 503 may have installed thereon various communication client applications, such as shopping-like applications, web browser applications, search-like applications, instant messaging tools, mailbox clients, social platform software, etc. (by way of example only).

The

terminal devices

501, 502, 503 may be various electronic devices having a display screen and supporting web browsing, including but not limited to smart phones, tablet computers, laptop portable computers, desktop computers, and the like.

The server 505 may be a server providing various services, such as a background management server (for example only) providing support for shopping websites browsed by users using the

terminal devices

501, 502, 503. The backend management server may analyze and perform other processing on the received data such as the product information query request, and feed back a processing result (for example, target push information, product information — just an example) to the terminal device.

It should be noted that the method for updating and reading statistics provided by the embodiment of the present invention is generally executed by the server 505, and accordingly, the apparatus for updating and reading statistics is generally disposed in the server 505.

It should be understood that the number of terminal devices, networks, and servers in fig. 5 is merely illustrative. There may be any number of terminal devices, networks, and servers, as desired for implementation.

Referring now to FIG. 6, a block diagram of a computer system 600 suitable for use with a terminal device implementing an embodiment of the invention is shown. The terminal device shown in fig. 6 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present invention.

As shown in fig. 6, the computer system 600 includes a Central Processing Unit (CPU)601 that can perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM)602 or a program loaded from a storage section 608 into a Random Access Memory (RAM) 603. In the RAM 603, various programs and data necessary for the operation of the system 600 are also stored. The CPU 601, ROM 602, and RAM 603 are connected to each other via a bus 604. An input/output (I/O) interface 605 is also connected to bus 604.

The following components are connected to the I/O interface 605: an input portion 606 including a keyboard, a mouse, and the like; an output portion 607 including a display such as a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and the like, and a speaker; a storage section 608 including a hard disk and the like; and a communication section 609 including a network interface card such as a LAN card, a modem, or the like. The communication section 609 performs communication processing via a network such as the internet. The driver 610 is also connected to the I/O interface 605 as needed. A removable medium 611 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 610 as necessary, so that a computer program read out therefrom is mounted in the storage section 608 as necessary.

In particular, according to the embodiments of the present disclosure, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method illustrated in the flow chart. In such an embodiment, the computer program may be downloaded and installed from a network through the communication section 609, and/or installed from the removable medium 611. The computer program performs the above-described functions defined in the system of the present invention when executed by the Central Processing Unit (CPU) 601.

It should be noted that the computer readable medium shown in the present invention can be a computer readable signal medium or a computer readable storage medium or any combination of the two. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present invention, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present invention, however, a computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The modules described in the embodiments of the present invention may be implemented by software or hardware. The described modules may also be provided in a processor, which may be described as: a processor includes a sending module, an obtaining module, a determining module, and a first processing module. The names of these modules do not form a limitation on the modules themselves in some cases, and for example, the sending module may also be described as a "module sending a picture acquisition request to a connected server".

As another aspect, the present invention also provides a computer-readable medium that may be contained in the apparatus described in the above embodiments; or may be separate and not incorporated into the device. The computer readable medium carries one or more programs which, when executed by a device, cause the device to comprise:

acquiring a statistic set to be updated;

According to the technical scheme of the embodiment of the invention, the following beneficial effects can be achieved:

The above-described embodiments should not be construed as limiting the scope of the invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions can occur, depending on design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method of updating a statistical value, comprising:

acquiring a statistic set to be updated;

2. The method of claim 1, wherein for each statistic element in the set of statistic elements, determining a memory location in an idle state matching the statistic element comprises:

3. The method of claim 1, wherein writing the statistics element to a memory location in an idle state completes updating the statistics value, comprising:

determining an address of a memory cell in an idle state;

4. A method according to claim 2 or 3, wherein the elements in the set of memory locations have different base addresses and the same offset address.

5. A method of reading statistical values, comprising:

acquiring all storage units for storing statistical values to be read;

accumulating the numerical values stored in the storage unit;

6. The method of claim 5, wherein obtaining all memory cells storing the statistical values to be read comprises:

acquiring a storage unit set matched with the statistical value to be read;

7. An apparatus for updating a statistical value, comprising:

the set acquisition module is used for acquiring a statistic set to be updated;

8. An apparatus for reading statistical values, comprising:

9. An electronic device for updating or reading, comprising:

one or more processors;

a storage device for storing one or more programs,

when executed by the one or more processors, cause the one or more processors to implement the method of any one of claims 1-6.

10. A computer-readable medium, on which a computer program is stored, which, when being executed by a processor, carries out the method according to any one of claims 1-6.