CN112463052B - Method, system, device and medium for reducing DDR capacity requirement in solid state disk - Google Patents

Method, system, device and medium for reducing DDR capacity requirement in solid state disk Download PDF

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CN112463052B
CN112463052B CN202011351213.0A CN202011351213A CN112463052B CN 112463052 B CN112463052 B CN 112463052B CN 202011351213 A CN202011351213 A CN 202011351213A CN 112463052 B CN112463052 B CN 112463052B
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ddr
sub
address
size
logical address
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CN112463052A (en
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苗森
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Suzhou Inspur Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/062—Securing storage systems
    • G06F3/0622—Securing storage systems in relation to access
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

The invention discloses a method, a system, equipment and a storage medium for reducing DDR capacity requirement in a solid state disk, wherein the method comprises the following steps: determining a first size of an L2P table for storing hot data according to a preset ratio of hot and cold data, and creating a DDR according to the first size; storing the logical address, the physical address and the access frequency of the logical address of the hot data into the DDR, and storing the logical address and the physical address of the cold data into a designated position; dividing the DDR into a plurality of sub-DDR, and determining the counting range of each sub-DDR; responding to the occurrence of reading and writing of the logic address, determining the corresponding sub DDR according to the size of the logic address, and reading and judging whether the logic address exists in the sub DDR; responding to the logic address existing in the sub DDR, adding the accessed times of the logic address and judging whether the accessed times of the logic address is the minimum value in the sub DDR; and in response to the number of times the logical address is accessed not being the minimum value in the sub-DDR, replacing the logical address with the logical address having the smallest access value in the sub-DDR.

Description

Method, system, equipment and medium for reducing DDR capacity requirement in solid state disk
Technical Field
The present invention relates to the field of solid state drives, and in particular, to a method, a system, a computer device, and a readable medium for reducing a DDR capacity requirement in a solid state drive.
Background
A Solid State Disk (SSD) is composed of user Data and metadata, and except that the user Data being read and written is cached in a DDR (Double Data Rate) during operation, the rest of the user Data is mostly stored in a flash memory. The metadata is different from the metadata, the metadata is stored in nand (flash memory) for power failure storage when power is off, and the metadata is required to be completely restored to DDR when power is on, so that the normal operation of the SSD after the power is on is ensured. Throughout the SSD DDR design, metadata occupies the vast majority of the DDR.
At present, when the size of the DDR is considered in the design of an enterprise-level SSD, a per-thousandth ratio is generally adopted, for example, a 4G DDR needs to be configured for an enterprise-level SSD with a 4T capacity. This one thousandth ratio is derived from the definition rules of the L2P table (since L2P is the metadata occupying the most DDR), and generally one L2P table entry consists of one 32bit (4byte) which is used to identify the physical storage location of one 4K user data, so that the whole 4T disc consists of 4T/4K L2P table entries, which total 1G, and therefore the DDR of the SSD needs 4G size. At power up SSD will restore all 4G L2P tables to DDR.
Disclosure of Invention
In view of this, an object of the embodiments of the present invention is to provide a method, a system, a computer device, and a computer readable storage medium for reducing the DDR capacity requirement in a solid state disk, in which cold data and hot data are stored separately, so as to greatly reduce the DDR capacity requirement and reduce the production cost of the solid state disk.
Based on the above object, an aspect of the embodiments of the present invention provides a method for reducing the DDR capacity requirement in a solid state disk, including the following steps: determining a first size of an L2P table for storing hot data and a second size of an L2P table for storing cold data according to a preset proportion of hot and cold data, creating a DDR according to the first size, and determining a designated position of a flash according to the second size; storing the logical address, the physical address and the access frequency of the logical address of the hot data into the DDR, and storing the logical address and the physical address of the cold data into the specified position; dividing the DDR into a plurality of sub-DDR, and determining the counting range of each sub-DDR; responding to the occurrence of reading and writing of a logic address, determining a corresponding sub DDR according to the size of the logic address, and reading and judging whether the logic address exists in the sub DDR; responding to the logic address existing in the sub DDR, adding one to the number of times of access of the logic address, and judging whether the number of times of access of the logic address is the minimum value in the sub DDR; and in response to the fact that the number of times of access of the logic address is not the minimum value in the sub-DDR, replacing the logic address with the minimum access value in the sub-DDR.
In some embodiments, the method further comprises: in response to the logical address not being present in the sub-DDR, reading the logical address from the specified location.
In some embodiments, the creating a DDR according to the first size includes: three DDRs of the first size are created, two of the L2P tables storing thermal data are used, and the number of times the logical address in the L2P table is accessed is used.
In some embodiments, the determining the count range of each sub-DDR includes: and determining the counting range of each sub DDR according to the size of the sub DDR, the size of the L2P table entry in the sub DDR and the proportion of the preset cold and hot data.
In another aspect of the embodiments of the present invention, a system for reducing a DDR capacity requirement in a solid state disk is further provided, including: the device comprises a creating module, a storage module and a control module, wherein the creating module is configured to determine a first size of an L2P table for storing hot data and a second size of an L2P table for storing cold data according to a preset proportion of the hot and cold data, create a DDR according to the first size, and determine a designated position of a flash according to the second size; the storage module is configured to store the logical address, the physical address and the access frequency of the logical address of the hot data into the DDR, and store the logical address and the physical address of the cold data into the specified position; the partition module is configured to divide the DDR into a plurality of sub-DDR, and determine a counting range of each sub-DDR; the first judgment module is configured to respond to the existence of a logic address for reading and writing, determine a corresponding sub DDR according to the size of the logic address, and read and judge whether the logic address exists in the sub DDR; the second judging module is configured to respond to the logic address existing in the sub DDR, add the accessed times of the logic address together and judge whether the accessed times of the logic address is the minimum value in the sub DDR; and the updating module is configured to respond to the condition that the access frequency of the logic address is not the minimum value in the sub-DDR, and replace the logic address with the minimum access value in the sub-DDR.
In some embodiments, the system further comprises a reading module configured to: in response to the logical address not being present in the sub-DDR, reading the logical address from the specified location.
In some embodiments, the creation module is configured to: three DDRs of the first size are created, two of the L2P tables storing thermal data are used, and the number of times the logical address in the L2P table is accessed is used.
In some embodiments, the partitioning module is configured to: and determining the counting range of each sub DDR according to the size of the sub DDR, the size of the L2P table entry in the sub DDR and the proportion of the preset cold and hot data.
In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method as above.
In another aspect of the embodiments of the present invention, a computer-readable storage medium is further provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.
The invention has the following beneficial technical effects: and cold and hot data are stored separately, so that the requirement of DDR capacity is greatly reduced, and the production cost of the solid state disk is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram illustrating an embodiment of a method for reducing DDR capacity requirements in a solid state disk according to the present invention;
fig. 2 is a schematic diagram of a hardware structure of an embodiment of the computer device for reducing the DDR capacity requirement in the solid state disk according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In view of the foregoing, a first aspect of the embodiments of the present invention provides an embodiment of a method for reducing DDR capacity requirements in a solid state disk. Fig. 1 is a schematic diagram illustrating an embodiment of a method for reducing DDR capacity requirements in a solid state disk provided by the present invention. As shown in fig. 1, the embodiment of the present invention includes the following steps:
s1, determining a first size of an L2P table for storing hot data and a second size of an L2P table for storing cold data according to the proportion of preset hot and cold data, creating a DDR according to the first size, and determining the designated position of the flash according to the second size;
s2, storing the logical address, the physical address and the access frequency of the logical address of the hot data into a DDR, and storing the logical address and the physical address of the cold data into a specified position;
s3, dividing the DDR into a plurality of sub-DDR, and determining the counting range of each sub-DDR;
s4, responding to the logic address, reading and writing, determining the corresponding sub DDR according to the size of the logic address, reading and judging whether the logic address exists in the sub DDR;
s5, responding to the logic address existing in the sub DDR, adding the accessed times of the logic address together and judging whether the accessed times of the logic address is the minimum value in the sub DDR; and
and S6, in response to the access frequency of the logic address not being the minimum value in the sub DDR, replacing the logic address with the minimum access value in the sub DDR.
A first size of an L2P (Logical to physical ) table storing hot data and a second size of an L2P table storing cold data are determined according to a preset proportion of hot and cold data, a DDR is created according to the first size, and a designated position of a flash is determined according to the second size. According to different application scenes, the proportion of cold and hot data is distinguished, which can be obtained by monitoring read-write data in a specific scene, and in the embodiment of the invention, the proportion of the cold and hot data is assumed to be 8:2, and the capacity of the SSD is assumed to be 4T. The size of the hardware design DDR (only the occupation of the L2P table is considered in the embodiment of the present invention), and the size of the L2P table required by the 4T capacity is 4G. According to the cold-hot data ratio of 8:2, the DDR for storing hot data is 0.8G, and the nand size for storing cold data is 3.2G.
In some embodiments, the creating a DDR according to the first size includes: three DDRs of the first size are created, two of the L2P tables storing thermal data are used, and the number of times the logical address in the L2P table is accessed is used. DDR size is L2P of three thermal data sets indicating the size of DDR required, i.e. 4G 2/(2+8) 3 ═ 2.4G. Two of the three first size DDRs are used to hold L2P of hot data. L2P consists of LBAs (logical addresses) and PBAs (physical addresses), totaling 8 bytes. The remaining DDR identifies the number of times the LBA in L2P was accessed.
And storing the logical address, the physical address and the access times of the logical address of the hot data into the DDR, and storing the logical address and the physical address of the cold data into the specified position.
The DDR is divided into a plurality of sub-DDRs, and a count range of each sub-DDR is determined.
In some embodiments, the determining the count range of each sub-DDR comprises: and determining the counting range of each sub DDR according to the size of the sub DDR, the size of the L2P table entry in the sub DDR and the proportion of the preset cold and hot data. The entire DDR is divided in units of 3M. The whole D DR, namely the new L2P table entry, is composed of LBA, PBA and LBA access times, and the total number of the accessed LBA, PBA and LBA is 12 bytes. The number of times the LBA is accessed consists of all LBA counts in this sub-DDR range. It can be known that the actual number of LBAs in the 3M range is (3M/12bytes)/(2/(2+8)) -256K × 5, and the number of bits counted per time is 1M/256K/5-0.8 bytes-6 bits, so the count range is 0 to 63.
And responding to the occurrence of reading and writing of the logic address, determining the corresponding sub DDR according to the size of the logic address, and reading and judging whether the logic address exists in the sub DDR. When one LBA is read and written in the running process of the SSD, the range of the sub DDR where the LBA is located can be determined according to the size of the LBA, 3M data corresponding to the sub DDR is read into the DDR, and whether a logical address exists in the sub DDR or not is judged.
And responding to the logic address existing in the sub DDR, adding the accessed times of the logic address and judging whether the accessed times of the logic address is the minimum value in the sub DDR.
And in response to the number of times the logical address is accessed not being the minimum value in the sub-DDR, replacing the logical address with the logical address having the smallest access value in the sub-DDR. When the LBA exists, the number of times the LBA corresponding to the LBA is accessed is increased by one, and when the LBA is full of 63, the number of times all the LBAs in the area are accessed is decreased by 63 (minimum is 0). And then judging whether the value is the minimum value in the current area, replacing the minimum value with the value when the value is not the minimum value, finding out the LBA-PBA (table entry) corresponding to the minimum count value, and replacing the LBA-PBA.
In some embodiments, the method further comprises: in response to the logical address not being present in the sub-DDR, reading the logical address from the specified location. When the LBA does not exist, it is proved that the L2P table corresponding to the LBA is in the flash and is directly read from the designated flash location.
According to the embodiment of the invention, the L2P table is redesigned based on a cold and hot data mode, the cold and hot data are relatively fixed in a specific application scene, the L2P of the hot data is stored on the DDR, and the L2P of the cold data is directly stored on the flash at a specific position, so that the DDR is saved.
It should be noted that, the steps in the embodiments of the method for reducing the DDR capacity requirement in the solid state disk described above may be interleaved, replaced, added, or deleted, and therefore, the method for reducing the DDR capacity requirement in the solid state disk by these reasonable permutation and combination transformations shall also belong to the scope of the present invention, and shall not limit the scope of the present invention to the embodiments.
In view of the foregoing, a second aspect of the embodiments of the present invention provides a system for reducing the capacity requirement of a DDR in a solid state disk, including: the device comprises a creating module, a storage module and a control module, wherein the creating module is configured to determine a first size of an L2P table for storing hot data and a second size of an L2P table for storing cold data according to a preset proportion of the hot and cold data, create a DDR according to the first size, and determine a designated position of a flash according to the second size; the storage module is configured to store the logical address, the physical address and the access frequency of the logical address of the hot data into the DDR, and store the logical address and the physical address of the cold data into the specified position; the partition module is configured to divide the DDR into a plurality of sub-DDR, and determine a counting range of each sub-DDR; the first judgment module is configured to respond to the existence of a logic address for reading and writing, determine a corresponding sub DDR according to the size of the logic address, and read and judge whether the logic address exists in the sub DDR; the second judging module is configured to respond to the logic address existing in the sub DDR, add one to the number of times of access of the logic address, and judge whether the number of times of access of the logic address is the minimum value in the sub DDR; and the updating module is configured to respond to the condition that the access frequency of the logic address is not the minimum value in the sub-DDR, and replace the logic address with the minimum access value in the sub-DDR.
In some embodiments, the system further comprises a reading module configured to: in response to the logical address not being present in the sub-DDR, reading the logical address from the specified location.
In some embodiments, the creation module is configured to: three DDRs of the first size are created, two of the L2P tables storing thermal data are used, and the number of times the logical address in the L2P table is accessed is used.
In some embodiments, the partitioning module is configured to: and determining the counting range of each sub DDR according to the size of the sub DDR, the size of the L2P table entry in the sub DDR and the proportion of the preset cold and hot data.
In view of the above object, a third aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: s1, determining a first size of an L2P table for storing hot data and a second size of an L2P table for storing cold data according to the proportion of preset hot and cold data, creating a DDR according to the first size, and determining the designated position of the flash according to the second size; s2, storing the logical address, the physical address and the access times of the logical address of the hot data into the DDR, and storing the logical address and the physical address of the cold data into a designated position; s3, dividing the DDR into a plurality of sub-DDR, and determining the counting range of each sub-DDR; s4, responding to the logic address, reading and writing, determining the corresponding sub DDR according to the size of the logic address, reading and judging whether the logic address exists in the sub DDR; s5, responding to the logic address existing in the sub DDR, adding the accessed times of the logic address together and judging whether the accessed times of the logic address is the minimum value in the sub DDR; and S6, in response to the access frequency of the logic address not being the minimum value in the sub DDR, replacing the logic address with the access value in the sub DDR.
In some embodiments, the steps further comprise: in response to the logical address not being present in the sub-DDR, reading the logical address from the specified location.
In some embodiments, the creating a DDR according to the first size includes: three DDRs of the first size are created, two of the L2P tables storing thermal data are used, and the number of times the logical address in the L2P table is accessed is used.
In some embodiments, the determining the count range of each sub-DDR includes: and determining the counting range of each sub DDR according to the size of the sub DDR, the size of the L2P table entry in the sub DDR and the proportion of the preset cold and hot data.
Fig. 2 is a schematic diagram of a hardware structure of an embodiment of the computer device for reducing the DDR capacity requirement in the solid state disk according to the present invention.
Taking the apparatus shown in fig. 2 as an example, the apparatus includes a processor 301 and a memory 302, and may further include: an input device 303 and an output device 304.
The processor 301, the memory 302, the input device 303 and the output device 304 may be connected by a bus or other means, and fig. 2 illustrates the connection by a bus as an example.
The memory 302 is used as a non-volatile computer-readable storage medium, and can be used for storing non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions/modules corresponding to the method for reducing the DDR capacity requirement in the solid state disk in the embodiment of the present application. The processor 301 executes various functional applications of the server and data processing by running the nonvolatile software programs, instructions and modules stored in the memory 302, namely, implements the method for reducing the DDR capacity requirement in the solid state disk of the above method embodiment.
The memory 302 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the data storage area may store data created according to use of a method of reducing DDR capacity requirements in the solid state disk, and the like. Further, the memory 302 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 302 optionally includes memory located remotely from processor 301, which may be connected to a local module via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 303 may receive information such as a user name and a password that are input. The output means 304 may comprise a display device such as a display screen.
Program instructions/modules corresponding to one or more methods for reducing the DDR capacity requirement in the solid state disk are stored in the memory 302, and when executed by the processor 301, the method for reducing the DDR capacity requirement in the solid state disk in any of the above method embodiments is performed.
Any embodiment of the computer device executing the method for reducing the DDR capacity requirement in the solid state disk may achieve the same or similar effects as any corresponding embodiment of the foregoing method.
The invention also provides a computer readable storage medium storing a computer program which, when executed by a processor, performs the method as above.
Finally, it should be noted that, as those skilled in the art can understand that all or part of the processes in the methods according to the embodiments described above can be implemented by instructing relevant hardware through a computer program, and the program of the method for reducing the DDR capacity requirement in the solid state disk can be stored in a computer readable storage medium, and when executed, the program can include the processes according to the embodiments of the methods described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments corresponding thereto.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, where the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant only to be exemplary, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the idea of an embodiment of the invention, also combinations between technical features in the above embodiments or in different embodiments are possible, and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims (10)

1. A method for reducing DDR capacity requirement in a solid state disk is characterized by comprising the following steps:
determining a first size of an L2P table for storing hot data and a second size of an L2P table for storing cold data according to a preset proportion of hot and cold data, creating a DDR according to the first size, and determining a designated position of a flash according to the second size;
storing the logical address, the physical address and the access frequency of the logical address of the hot data into the DDR, and storing the logical address and the physical address of the cold data into the specified position;
dividing the DDR into a plurality of sub-DDR, and determining the counting range of each sub-DDR;
responding to the occurrence of reading and writing of a logic address, determining a corresponding sub DDR according to the size of the logic address, and reading and judging whether the logic address exists in the sub DDR;
responding to the logic address existing in the sub DDR, adding one to the number of times of access of the logic address, and judging whether the number of times of access of the logic address is the minimum value in the sub DDR;
and in response to the number of times of accessing the logical address is not the minimum value in the sub-DDR, replacing the logical address with the logical address having the minimum access value in the sub-DDR.
2. The method of claim 1, further comprising:
in response to the logical address not being present in the sub-DDR, reading the logical address from the specified location.
3. The method of claim 1, wherein creating the DDR according to the first size comprises:
three DDRs of the first size are created, two of the L2P tables storing thermal data are used, and the number of times the logical address in the L2P table is accessed is used.
4. The method of claim 1, wherein the determining the count range of each sub-DDR comprises:
and determining the counting range of each sub DDR according to the size of the sub DDR, the size of the L2P table entry in the sub DDR and the proportion of the preset cold and hot data.
5. A system for reducing DDR capacity requirements in a solid state disk, comprising:
the system comprises a creating module, a judging module and a sending module, wherein the creating module is configured to determine a first size of an L2P table for storing hot data and a second size of an L2P table for storing cold data according to a preset proportion of hot and cold data, create a DDR according to the first size, and determine a designated position of a flash according to the second size;
the storage module is configured to store the logical address, the physical address and the access frequency of the logical address of the hot data into the DDR, and store the logical address and the physical address of the cold data into the designated position;
the partition module is configured to divide the DDR into a plurality of sub-DDR, and determine a counting range of each sub-DDR;
the first judgment module is configured to respond to the existence of a logic address for reading and writing, determine a corresponding sub DDR according to the size of the logic address, and read and judge whether the logic address exists in the sub DDR;
the second judging module is configured to respond to the logic address existing in the sub DDR, add the accessed times of the logic address together and judge whether the accessed times of the logic address is the minimum value in the sub DDR;
and the updating module is configured to respond to the condition that the access frequency of the logic address is not the minimum value in the sub-DDR, and replace the logic address with the minimum access value in the sub-DDR.
6. The system of claim 5, further comprising a reading module configured to:
in response to the logical address not being present in the sub-DDR, reading the logical address from the specified location.
7. The system of claim 5, wherein the creation module is configured to:
three DDRs of the first size are created, two of the L2P tables storing thermal data are used, and the number of times the logical address in the L2P table is accessed is used.
8. The system of claim 5, wherein the partitioning module is configured to:
and determining the counting range of each sub DDR according to the size of the sub DDR, the size of the L2P table entry in the sub DDR and the proportion of the preset cold and hot data.
9. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method of any one of claims 1 to 4.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 4.
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