CN109753443B - Data processing method and device and electronic equipment - Google Patents
Data processing method and device and electronic equipment Download PDFInfo
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- CN109753443B CN109753443B CN201910028966.9A CN201910028966A CN109753443B CN 109753443 B CN109753443 B CN 109753443B CN 201910028966 A CN201910028966 A CN 201910028966A CN 109753443 B CN109753443 B CN 109753443B
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Abstract
The embodiment of the invention provides a data processing method and device and electronic equipment, and relates to the field of storage management. The device is arranged in the electronic equipment and can realize the method. The method comprises the following steps: and judging whether the erasing times of the cold data flash memory block and the idle flash memory block are balanced or not, if so, writing the input data into the flash memory block with the lower erasing times in the cold data flash memory block and the idle flash memory block, and if so, writing the input data into the idle flash memory block. Because whether the erasing times of the cold data flash memory block and the idle flash memory block are balanced or not is judged, and when the erasing times of the flash memory block are unbalanced, the input data are written into the flash memory block with less erasing times in the cold data flash memory block and the idle flash memory block, on one hand, the problem that the service life of the flash memory is shortened due to the fact that cold and hot data are not considered is solved, and on the other hand, the problem that storage performance is influenced due to the fact that data are frequently moved is solved.
Description
Technical Field
The invention relates to the field of storage management of flash memories, in particular to a data processing method and device and electronic equipment.
Background
The NAND flash memory has the characteristics of non-volatility, large storage capacity, low cost and the like, and has become a mainstream large-capacity storage medium in the market. The NAND flash memory includes a plurality of flash blocks, and the life of the flash blocks is reduced as the number of times of erasing increases during use, and eventually becomes a bad block. When the number of bad blocks reaches a certain proportion of the total flash memory blocks, the whole NAND flash memory is scrapped.
At present, wear leveling methods are generally used to level the usage of each flash block, and include dynamic methods and static methods. When writing data, the dynamic method writes input data into the flash memory blocks with less erasing times, and because the cold and hot property of the data is not considered, namely whether the data is not updated for a long time, the erasing times of the flash memory blocks are unbalanced, and the service life of the flash memory is shortened. The static method needs to frequently carry out data movement, and has the problem of influencing the storage performance.
Disclosure of Invention
Embodiments of the present invention provide a data processing method, an apparatus, and an electronic device, which are used to solve the problems that the number of times of erasing flash memory blocks is unbalanced and the storage performance is affected by frequently performing data transfer.
In order to achieve the above purpose, the embodiment of the present invention adopts the following technical solutions:
in a first aspect, an embodiment of the present invention provides a data processing method, where the method includes: and judging whether the erasing times of the cold data flash memory block and the idle flash memory block are balanced or not, if so, writing the input data into the flash memory block with the lower erasing times in the cold data flash memory block and the idle flash memory block, and if so, writing the input data into the idle flash memory block.
In a second aspect, an embodiment of the present invention further provides a data processing apparatus, which includes a determining module and a writing module. The judging module is used for judging whether the erasing times of the cold data flash memory block and the idle flash memory block are balanced or not, the writing module is used for writing the input data into the flash memory block with less erasing times in the cold data flash memory block and the idle flash memory block when the erasing times of the cold data flash memory block and the idle flash memory block are unbalanced, and the writing module is used for writing the input data into the idle flash memory block when the erasing times of the cold data flash memory block and the idle flash memory block are balanced.
In a third aspect, an embodiment of the present invention further provides an electronic device, including: control chip, memory, communication port, bus, this electronic equipment can carry out the data processing method that has just been mentioned.
The data processing method, the data processing device and the electronic equipment are provided by the embodiment of the invention, and the device is arranged in the electronic equipment and can realize the method. The method comprises the following steps: and judging whether the erasing times of the cold data flash memory block and the idle flash memory block are balanced or not, if so, writing the input data into the flash memory block with the lower erasing times in the cold data flash memory block and the idle flash memory block, and if so, writing the input data into the idle flash memory block. Because whether the erasing times of the cold data flash memory block and the idle flash memory block are balanced or not is judged, and when the erasing times of the flash memory block are unbalanced, the input data are written into the flash memory block with less erasing times in the cold data flash memory block and the idle flash memory block, on one hand, the problem that the service life of the flash memory is shortened due to the fact that cold and hot data are not considered is solved, and on the other hand, the problem that storage performance is influenced due to the fact that data are frequently moved is solved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 shows a block diagram of an electronic device according to an embodiment of the present invention.
Fig. 2 is a schematic flow chart illustrating a dynamic wear leveling method according to an embodiment of the present invention.
Fig. 3 is a schematic flow chart of a static wear leveling method according to an embodiment of the present invention.
Fig. 4 is a flowchart illustrating a data processing method according to an embodiment of the present invention.
Fig. 5 is a flow chart illustrating another data processing method according to an embodiment of the present invention.
FIG. 6 is a flow chart illustrating writing of input data into a cold data flash block corresponding to a second minimum number of erasures according to an embodiment of the present invention.
Fig. 7 is a schematic diagram illustrating the erase times of different flash blocks in the first flash memory according to an embodiment of the present invention.
FIG. 8 is a diagram illustrating the number of times different flash blocks are erased in a second flash memory according to an embodiment of the present invention.
FIG. 9 is a diagram illustrating the number of times different flash blocks are erased in a third flash memory according to an embodiment of the present invention.
Fig. 10 is a schematic diagram illustrating functional blocks of a data processing apparatus according to an embodiment of the present invention.
Icon: 100-an electronic device; 110-a memory; 120-a control chip; 130-a communication interface; 140-a bus; 200-a data processing apparatus; 201-an acquisition module; 202-a judging module; 203-write module.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
Referring to fig. 1, which is a block diagram of an electronic device 100 according to an embodiment of the present invention, the electronic device 100 may include a control chip 120, a memory 110, a communication port, and a bus 140. The components of the control chip 120, the memory 110 and the communication interface 130 are electrically connected to each other directly or indirectly to achieve data transmission or interaction, for example, the components may be electrically connected to each other through one or more buses 140 or signal lines, or the control chip 120 is directly connected to the communication interface 130 and the memory 110 through the buses 140 respectively.
The electronic device 100 may further execute a corresponding data processing method through a preset data processing apparatus, where the data processing apparatus may be directly stored in the control chip 120 in a form of firmware, for example, when the control chip 120 includes a static memory and a processor, the data processing apparatus is directly stored in the static memory in the form of firmware in advance. The data processing device may also be stored in the memory 110 in the form of a program module, and the processor of the control chip 120 may call the data processing device stored in the memory 110 through the bus 140 and execute a corresponding data processing method when running. Alternatively, the data processing apparatus provided in the embodiment of the present invention may also be respectively stored in the static memory and the storage 110, and the processor may respectively call the data processing apparatus stored in the static memory and the storage 110 and execute the corresponding data processing method when running. It should be noted that the data processing apparatus provided in the embodiment of the present invention may also be disposed in the electronic device 100 in a form of hardware, and when the electronic device 100 runs, the data processing apparatus may perform interaction between data and signaling with the communication interface 130, the control chip 120, and the memory 110 through the bus 140 to complete a corresponding data processing method.
It is understood that the electronic device 100 provided by the embodiment of the present invention may be installed in other electronic devices, so that the electronic device 100 may perform data processing in cooperation with other electronic devices, for example, the electronic device 100 may be installed in a computer, an embedded device, or an internet of things device. Taking the example that the electronic device 100 is installed in a computer, the electronic device 100 may perform interaction between data and signaling with the computer through the communication interface 130, it should be noted that the data Processing apparatus provided in the embodiment of the present invention may also be disposed in a Central Processing Unit (CPU) of the computer in the form of firmware, or executed by the CPU in the form of program modules, so as to complete the corresponding data Processing method.
The memory 110 may be, but is not limited to, a NAND flash chip (NAND flash).
The control chip 120 may be an integrated circuit chip having signal processing capabilities. The control chip 120 may be an ARM architecture Processor, or a general control chip, including a Central Processing Unit (CPU), a Network control chip (NP), and the like; but may also be a digital signal control chip (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components.
It will be appreciated that the configuration shown in FIG. 1 is merely illustrative and that electronic device 100 may include more or fewer components than shown in FIG. 1 or have a different configuration than shown in FIG. 1. The components shown in fig. 1 may be implemented in hardware, software, or a combination thereof.
Based on the electronic device shown in fig. 1, the prior art generally adopts a dynamic method and a static method to balance the usage of each memory cell in the memory. Fig. 2 is a schematic flow chart of a dynamic wear leveling method according to an embodiment of the present invention.
S10, writing the input data into the free flash memory block with the least erasing times.
And S11, marking invalid data pages corresponding to the input data.
Specifically, taking the storage management of the flash memory blocks of the NAND flash memory as an example, when input data needs to be written into the flash memory for storage, the idle flash memory block with the minimum erasing frequency is obtained, and the input data is written into the idle flash memory block with the minimum erasing frequency. When the input data has corresponding original data in the flash memory, namely the input data is written into the flash memory to update the original data, the page where the original data is located is marked as an invalid data page.
It can be understood that the dynamic wear leveling method does not consider the cold and hot property of data, if the data just written is updated again immediately, the data block of the flash memory which is just updated is marked as an invalid data page, when the data is updated frequently, the flash memory block which stores the cold data is erased less (the cold data is the data which is not updated in the preset time), and the flash memory block which stores the hot data is erased more, so that the flash memory block which stores the hot data is erased excessively, and therefore the service life of the flash memory which uses the method is generally short.
Fig. 3 is a schematic flow chart of a static wear leveling method according to an embodiment of the present invention.
S20, writing the valid data of the cold data flash memory block into the idle flash memory block with the largest erasing times.
S21, writing the input data into the cold data flash block.
And S22, marking invalid data pages corresponding to the input data.
Specifically, taking the storage management of the flash memory block of the NAND flash memory as an example, when input data needs to be written into the flash memory for storage, the cold data flash memory block and the idle flash memory block with the largest erasing frequency are obtained, all data in the cold data flash memory block are read out and written into the idle flash memory block with the largest erasing frequency, and then the cold data flash memory block is erased. The input data is written to the cold data flash block after the cold data flash block is erased. When the input data has corresponding original data in the flash memory, the page where the original data is located is marked as an invalid data page.
It will be appreciated that while the static wear leveling method allows for moving cold data to the free flash block with the most number of erasures, the free flash block with the least number of erasures is used to store the incoming data. The method solves the problem of wear leveling to a certain extent, but at the same time, because data in the flash memory needs to be frequently moved, extra reading and writing is introduced and more performance resources are occupied, so that the overall storage performance of the flash memory is influenced.
In order to solve the above technical problem, a possible implementation manner of the data processing method is given below, and specifically, refer to fig. 4, which is a schematic flow chart of the data processing method provided in the embodiment of the present invention. The execution subject of the method is the data processing device, and the method comprises the following steps:
and S30, judging whether the erasing times of the cold data flash memory block and the idle flash memory block are balanced.
S31, writing the input data into the flash memory block with less erasing times in the cold data flash memory block and the idle flash memory block.
S32, writing the input data into the free flash memory block.
Specifically, taking the storage management of each flash memory block of the NAND flash memory as an example, when input data needs to be written into the flash memory for storage, obtaining a cold data flash memory block and an idle flash memory block, and determining whether the erasing times of the cold data flash memory block and the idle flash memory block are balanced, when the erasing times of the cold data flash memory block and the idle flash memory block are unbalanced, executing S31 to write the input data into the flash memory block with the smaller erasing times in the cold data flash memory block and the idle flash memory block; when the number of times of erasing of the cold data flash block and the free flash block is equalized, S32 is executed to write the input data into the free flash block. And when the input data has corresponding original data in the flash memory, marking the page where the original data is as an invalid data page.
Further, before S30, the method may further include the steps of: acquiring an idle flash memory block; when the erasing times of the idle flash memory block are not more than a preset value, directly writing input data into the idle flash memory block; when the number of times of erasing the free flash memory block is greater than the preset value, executing S30, S31 and S32.
Based on the embodiment provided in fig. 4, it can be understood that, by determining whether the erasing times of the cold data flash memory block and the idle flash memory block are balanced, and when the erasing times of the flash memory block are unbalanced, the input data is written into the flash memory block with the smaller erasing times in the cold data flash memory block and the idle flash memory block, on one hand, the problem that the service life of the flash memory is shortened due to the fact that cold and hot data are not considered is solved, and on the other hand, the problem that the storage performance is affected due to the fact that data are frequently moved is solved.
On the basis of fig. 4, a possible implementation manner of the complete solution is given below, and specifically, referring to fig. 5, a schematic flow chart of another data processing method provided by the embodiment of the present invention is shown. It should be noted that, the data processing method provided in the embodiment of the present invention is not limited by fig. 5 and the following specific sequence, and it should be understood that, in other embodiments, the sequence of some steps in the data processing method provided in the embodiment of the present invention may be interchanged according to actual needs, or some steps in the data processing method may be omitted or deleted. The specific flow shown in fig. 5 will be described in detail below.
S301, acquiring a first minimum erasing frequency in a free pool management table and a second minimum erasing frequency in a cold data management table;
the free pool management table comprises at least one free flash memory block identifier corresponding to the erasing times, the free flash memory block identifier corresponds to the free flash memory block, the cold data management table comprises at least one cold data flash memory block identifier corresponding to the erasing times, and the cold data flash memory block identifier corresponds to the cold data flash memory block.
Specifically, taking the storage management of each flash memory block of the NAND flash memory as an example, as shown in table 1 below, the free pool management table may be a mapping table (map table), that is, free flash memory blocks of all flash memory blocks of the NAND flash memory are recorded in the form of free flash memory block identifiers, and the number of times of erasing corresponding to each free flash memory block identifier is also recorded, where one free flash memory block identifier records a mapping relationship between a logical address and a physical address of one free flash memory block. As shown in table 2 below, the cold data management table may be a mapping table (map table), that is, all cold data flash blocks of the NAND flash memory are recorded in the form of cold data flash block identifiers, and the number of times of erasing corresponding to each cold data flash block identifier is also recorded, where one cold data flash block identifier records a mapping relationship between a logical address and a physical address of one cold data flash block, and the cold data flash block stores storage data that is not updated after a preset time. When input data need to be written into the flash memory for storage, acquiring the erasing times corresponding to the idle flash memory block identification with the minimum erasing times in the idle pool management table as the first minimum erasing times, and acquiring the erasing times corresponding to the cold data flash memory block identification with the minimum erasing times in the cold data management table as the second minimum erasing times.
TABLE 1
TABLE 2
S302, obtaining a difference value between the first minimum erasing times and the second minimum erasing times.
Specifically, the difference between the first minimum erase count and the second minimum erase count is obtained by subtracting the second minimum erase count from the first minimum erase count.
And S303, judging whether the difference value is equal to a preset threshold value or not.
Specifically, taking the storage management of each flash memory block of the NAND flash memory as an example, after obtaining the difference value, determining whether the difference value is equal to the preset threshold, and when the difference value is equal to the preset threshold, determining that the erasing times of the cold data flash memory block and the idle flash memory block are balanced, and executing S305; and when the difference value is not equal to the preset threshold value, judging that the erasing times of the cold data flash memory block and the idle flash memory block are not balanced, and executing S304. Since the NAND flash memory includes a plurality of different flash memory grains, and even if the NAND flash memory grains are the same type, the flash memory grains produced in different production modes have slight differences, the preset threshold value is different in different NAND flash memories, but the preset threshold value is a preset value for a specific NAND flash memory.
S304, judging that the erasing times of the cold data flash memory block and the idle flash memory block are unbalanced.
Specifically, it is determined that the erasing times of the cold data flash memory block and the idle flash memory block are unbalanced, which indicates that the wear degrees of the flash memory block storing the cold data and the idle flash memory block are different, and at this time, the wear degrees of the entire flash memory block are equalized, and S311 is executed.
S305, judging the erasing times of the cold data flash memory block and the idle flash memory block to be balanced.
Specifically, it is determined that the number of times of erasing the cold data flash memory block and the idle flash memory block is balanced, that is, the degree of wear of the flash memory block storing the cold data is the same as the degree of wear of the idle flash memory block, and at this time, S321 may be performed to write the input data into the idle flash memory block.
And S311, judging whether the difference value is larger than or smaller than a preset threshold value.
Specifically, when the difference is greater than the preset threshold, it is determined that the number of times of erasing the idle flash memory block is greater than the number of times of erasing the cold data flash memory block, and S312 is executed to store the input data into the cold data flash memory block with the minimum number of times of erasing; when the difference is smaller than the preset threshold, judging that the erasing times of the idle flash memory block are less than the erasing times of the cold data flash memory block, executing S313 to store the input data into the idle flash memory block with the least erasing times.
S313, writing the input data into the idle flash memory block corresponding to the first minimum erasing times.
Specifically, after the input data is written into the free flash memory block corresponding to the first minimum erasing times, when the input data has corresponding original data in the flash memory, the page where the original data is located is marked as an invalid data page, and the free pool table and the cold data table are updated.
And S312, writing the input data into the cold data flash memory block corresponding to the second minimum erasing times.
Specifically, after the input data is written into the cold data flash memory block corresponding to the second minimum erasing times, when the input data has corresponding original data in the flash memory, the page where the original data is located is marked as an invalid data page, and the free pool table and the cold data table are updated.
S321, writing the input data into the idle flash memory block corresponding to the first minimum erasing times.
It will be appreciated that the input data may also be written to a cold data flash block that has a low number of erasures at this time.
Further, referring to fig. 6, for S312 in fig. 5, a possible implementation manner is given for how to write the input data into the cold data flash block corresponding to the second minimum erase count, and includes:
s312-1, obtaining the maximum erasing times in the free pool management table.
Specifically, the free flash memory block identifier with the maximum number of erasing times can be found by comparing the number of erasing times in the free pool management table, and the corresponding free flash memory block can be found according to the free flash memory block identifier.
S312-2, writing the effective data in the cold data flash memory block corresponding to the second minimum erasing times into the idle flash memory block corresponding to the maximum erasing times.
Specifically, a cold data flash memory block identifier corresponding to the second minimum erasing frequency is obtained, and a corresponding cold data flash memory block is found according to the cold data flash memory block identifier. Then, the valid data in the cold data flash memory block is obtained, wherein the valid data is screened by inquiring a valid data record table managed by a garbage collection algorithm. And then writing the valid data into a free flash memory block corresponding to the maximum erasing times.
And S312-3, erasing the cold data flash memory block corresponding to the second minimum erasing times.
Specifically, a cold data flash memory block identifier corresponding to the second minimum erasing frequency is obtained, and the cold data flash memory block corresponding to the cold data flash memory block identifier is erased.
And S312-4, writing the input data into the cold data flash memory block corresponding to the second minimum erasing times.
Specifically, a cold data flash memory block identifier corresponding to the second minimum erasing frequency is obtained, and the input data is written into the cold data flash memory block corresponding to the cold data flash memory block identifier. And when the input data has corresponding original data in the flash memory, marking the page where the original data is located as an invalid data page, and updating the free pool table and the cold data table.
Based on the embodiments provided in fig. 5 and fig. 6, by presetting a preset threshold and determining whether the erasing times of the cold data flash memory block and the idle flash memory block are balanced, it is further determined whether to write the input data into the idle flash memory block with the minimum erasing times or to write the input data into the cold data flash memory block with the minimum erasing times, so as to avoid singly writing the input data into the idle flash memory block or singly writing the input data into the cold data flash memory block, consume the performance of the control chip, not only achieve wear leveling of the flash memory block, but also improve the overall operating performance of the flash memory.
Based on the embodiments provided in fig. 4 and 5, the following explanation is made for determining whether the erase times of the cold data flash memory block and the idle flash memory block are balanced:
referring to fig. 7, P/E is the erasing times of the flash memory block, the minimum erasing times of the cold data flash memory block is 10 times, the minimum erasing times of the idle flash memory block is 3 times, since 10>3, it can be determined that the erasing times of the cold data flash memory block and the idle flash memory block are unbalanced, and the minimum erasing times of the cold data flash memory block is greater than the minimum erasing times of the idle flash memory block, when the input data needs to be written into the flash memory for storage, the input data is written into the idle flash memory block with the erasing times of 3 times.
Referring to fig. 8, P/E is the erasing frequency of the flash memory block, the minimum erasing frequency of the cold data flash memory block is 1, the minimum erasing frequency of the idle flash memory block is 10, since 1<10, it can be determined that the erasing frequencies of the cold data flash memory block and the idle flash memory block are unbalanced, and the minimum erasing frequency of the cold data flash memory block is less than the minimum erasing frequency of the idle flash memory block, when input data needs to be written into the flash memory for storage, valid data in the cold data flash memory block with the erasing frequency of 1 is written into the idle flash memory block with the maximum erasing frequency, then the cold data flash memory block with the erasing frequency of 1 is erased, and the input data is written into the cold data flash memory block with the erasing frequency of 1.
Referring to fig. 9, P/E is the number of times of erasing the flash memory block, the minimum number of times of erasing the cold data flash memory block is 3 times, and the minimum number of times of erasing the idle flash memory block is 3 times, and since 3 is 3, it can be determined that the number of times of erasing the cold data flash memory block and the idle flash memory block is balanced, and when input data needs to be written into the flash memory for storage, the input data is written into the idle flash memory block with the number of times of erasing the input data being 3 times.
It can be understood that when the data processing method is used for writing the input data into the flash memory for storage, after the input data is written for many times, the erasing times of each cold data flash memory block and each idle flash memory block can be balanced, and the occupation of the performance resources of the flash memory can be reduced.
Fig. 10 is a schematic diagram of functional modules of a data processing apparatus according to an embodiment of the present invention. It should be noted that the data processing apparatus 200 provided in this embodiment may be disposed in the electronic device shown in fig. 1, and the data processing apparatus 200 may execute the data processing method shown in fig. 4, fig. 5, and fig. 6, the basic principle and the generated technical effect are the same as those of the foregoing method embodiment, and for the sake of brief description, no part mentioned in this embodiment may refer to the corresponding content in the foregoing method embodiment. The device comprises an acquisition module 201, a judgment module 202 and a writing module 203.
The obtaining module 201 is configured to obtain the erasing times of the cold data flash memory block and the idle flash memory block.
The determining module 202 is configured to determine whether the erase times of the cold data flash memory block and the idle flash memory block are balanced.
It is understood that the determining module 202 may execute the above S30.
The write-in module 203 is configured to write the input data into the flash memory block with the smaller erase frequency in the cold data flash memory block and the idle flash memory block when the erase frequency of the cold data flash memory block and the idle flash memory block is unbalanced, and write the input data into the idle flash memory block when the erase frequency of the cold data flash memory block and the idle flash memory block is balanced.
It is understood that the write module 203 may perform the above-mentioned S31, S32.
The obtaining module 201 is configured to obtain a first minimum erasing frequency in a free pool management table and a second minimum erasing frequency in a cold data management table, where the free pool management table includes at least one free flash block identifier corresponding to the erasing frequency, the free flash block identifier corresponds to the free flash block, the cold data management table includes at least one cold data flash block identifier corresponding to the erasing frequency, the cold data flash block identifier corresponds to the cold data flash block, and the obtaining module is configured to obtain a difference between the first minimum erasing frequency and the second minimum erasing frequency.
It is understood that the obtaining module 201 may execute the above S301 and S302.
The determining module 202 is further configured to determine whether the difference is equal to a preset threshold, determine that the erasing times of the cold data flash memory block and the idle flash memory block are unbalanced when the difference is not equal to the preset threshold, and determine that the erasing times of the cold data flash memory block and the idle flash memory block are balanced when the difference is equal to the preset threshold.
It is understood that the determining module 202 may execute the above S303, S304, and S305.
The determining module 202 is further configured to determine whether the difference is greater than or less than a preset threshold when the erasing times of the cold data flash memory block and the idle flash memory block are not balanced.
It is understood that the determining module 202 may execute the above S311.
The writing module 203 is further configured to write the input data into the idle flash memory block corresponding to the first minimum erasing frequency when the difference is smaller than the preset threshold, and write the input data into the cold data flash memory block corresponding to the second minimum erasing frequency when the difference is larger than the preset threshold.
It is understood that the writing module 203 may perform the above S312, S313.
The writing module 203 is further configured to write the input data into the idle flash memory block corresponding to the first minimum erasing times when the erasing times of the cold data flash memory block and the idle flash memory block are balanced.
It is understood that the writing module 203 may perform the above S321.
Further, the above module can also produce the following technical effects on how to write the input data into the cold data flash memory block corresponding to the second minimum erasing times.
The obtaining module 201 is further configured to obtain the maximum number of erasures in the free pool management table.
It is understood that the obtaining module 201 may execute the above S321-1.
The writing module 203 is further configured to write valid data in the cold data flash memory block corresponding to the second minimum erasing times into the idle flash memory block corresponding to the maximum erasing times, erase the cold data flash memory block corresponding to the second minimum erasing times, and write input data into the cold data flash memory block corresponding to the second minimum erasing times.
It is understood that the write module 203 may perform the above-mentioned S321-2, S321-3, and S321-4.
In summary, the data processing method, the data processing apparatus, and the electronic device provided in the embodiments of the present invention are provided. The device is arranged in the electronic equipment and can realize the method. The method comprises the following steps: and judging whether the erasing times of the cold data flash memory block and the idle flash memory block are balanced or not, if so, writing the input data into the flash memory block with the lower erasing times in the cold data flash memory block and the idle flash memory block, and if so, writing the input data into the idle flash memory block. Because whether the erasing times of the cold data flash memory block and the idle flash memory block are balanced or not is judged, and when the erasing times of the flash memory block are unbalanced, the input data are written into the flash memory block with less erasing times in the cold data flash memory block and the idle flash memory block, on one hand, the problem that the service life of the flash memory is shortened due to the fact that cold and hot data are not considered is solved, and on the other hand, the problem that storage performance is influenced due to the fact that data are frequently moved is solved.
It should be apparent to those skilled in the art that the embodiments of the present invention can be provided as a method, an apparatus, and an electronic device. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus, electronic device products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus and method embodiments described above are illustrative only, as the flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, the functional modules in the embodiments of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes. It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is only an alternative embodiment of the present invention and is not intended to limit the present invention, and various modifications and variations of the present invention may occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
Claims (10)
1. A data processing method, comprising:
judging whether the erasing times of the cold data flash memory block and the idle flash memory block are balanced or not, and if not, writing input data into the flash memory block with the less erasing times in the cold data flash memory block and the idle flash memory block;
and if the input data are balanced, writing the input data into the idle flash memory block.
2. The data processing method of claim 1, wherein the step of determining whether the number of times that the cold data flash block and the free flash block are erased is balanced comprises:
acquiring a first minimum erasing frequency in a free pool management table and a second minimum erasing frequency in a cold data management table, wherein the free pool management table comprises at least one free flash block identifier corresponding to the erasing frequency, the free flash block identifier corresponds to the free flash block, the cold data management table comprises at least one cold data flash block identifier corresponding to the erasing frequency, and the cold data flash block identifier corresponds to the cold data flash block;
acquiring a difference value between the first minimum erasing times and the second minimum erasing times;
when the difference value is not equal to a preset threshold value, judging that the erasing times of the cold data flash memory block and the idle flash memory block are not balanced; the preset threshold value is 0;
and when the difference value is equal to a preset threshold value, judging that the erasing times of the cold data flash memory block and the idle flash memory block are balanced.
3. The data processing method of claim 2, wherein the difference is obtained by subtracting the second minimum number of erasures from the first minimum number of erasures;
if the data is unbalanced, the step of writing the input data into the cold data flash memory block and the flash memory block with the less erasing times in the idle flash memory block comprises the following steps:
when the difference value is smaller than the preset threshold value, writing the input data into an idle flash memory block corresponding to the first minimum erasing times;
and when the difference value is larger than the preset threshold value, writing the input data into the cold data flash memory block corresponding to the second minimum erasing times.
4. The data processing method of claim 3, wherein the step of writing the input data to the cold data flash block corresponding to the second minimum number of erasures comprises:
acquiring the maximum erasing times in the free pool management table;
writing effective data in the cold data flash memory block corresponding to the second minimum erasing times into an idle flash memory block corresponding to the maximum erasing times;
erasing the cold data flash memory block corresponding to the second minimum erasing times;
and writing the input data into the cold data flash memory block corresponding to the second minimum erasing times.
5. The data processing method of claim 2, wherein the step of writing the input data to the free flash block if balanced comprises:
and writing the input data into a free flash memory block corresponding to the first minimum erasing times.
6. A data processing device is characterized by comprising a judging module and a writing module;
the judging module is used for judging whether the erasing times of the cold data flash memory block and the idle flash memory block are balanced or not;
the writing module is used for writing input data into the flash memory blocks with the less erasing times in the cold data flash memory blocks and the idle flash memory blocks when the erasing times of the cold data flash memory blocks and the idle flash memory blocks are not balanced;
and the writing module is used for writing the input data into the idle flash memory block when the erasing times of the cold data flash memory block and the idle flash memory block are balanced.
7. The data processing apparatus of claim 6, wherein the apparatus further comprises an acquisition module;
the acquisition module is used for acquiring a first minimum erasing frequency in a free pool management table and a second minimum erasing frequency in a cold data management table, wherein the free pool management table comprises at least one free flash block identifier corresponding to the erasing frequency, the free flash block identifier corresponds to the free flash block, the cold data management table comprises at least one cold data flash block identifier corresponding to the erasing frequency, and the cold data flash block identifier corresponds to the cold data flash block;
the obtaining module is further configured to obtain a difference between the first minimum erasure number and the second minimum erasure number;
when the difference value is not equal to a preset threshold value, the judging module is used for judging that the erasing times of the cold data flash memory block and the idle flash memory block are unbalanced; the preset threshold value is 0;
and when the difference value is equal to a preset threshold value, the judging module is used for judging that the erasing times of the cold data flash memory block and the idle flash memory block are balanced.
8. The data processing apparatus of claim 7, wherein the difference is obtained by subtracting the second minimum number of erasures from the first minimum number of erasures;
the writing module is used for writing the input data into an idle flash memory block corresponding to the first minimum erasing times when the difference value is smaller than the preset threshold value;
and the writing module is used for writing the input data into the cold data flash memory block corresponding to the second minimum erasing times when the difference value is larger than the preset threshold value.
9. The data processing apparatus according to claim 8, wherein the obtaining module is configured to obtain the maximum number of erasures in the free pool management table when the writing module writes the input data into the cold data flash block corresponding to the second minimum number of erasures;
the writing module is used for writing the valid data in the cold data flash memory block corresponding to the second minimum erasing times into the idle flash memory block corresponding to the maximum erasing times, erasing the cold data flash memory block corresponding to the second minimum erasing times, and writing the input data into the cold data flash memory block corresponding to the second minimum erasing times.
10. An electronic device, comprising: the device comprises a control chip, a memory, a communication port and a bus;
the electronic device may perform the method of any of the above claims 1-5.
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| CN111651126B (en) * | 2020-06-04 | 2023-05-16 | 重庆芯讯通无线科技有限公司 | Memory writing operation method, system, electronic device and medium |
| CN112379831A (en) * | 2020-11-05 | 2021-02-19 | 京信通信系统（中国）有限公司 | Data management method and device, computer equipment and storage medium |
| CN112466371B (en) * | 2020-12-17 | 2022-09-09 | 宁波拓普集团股份有限公司 | Method for circularly utilizing analog byte erasing function of flash memory |
| CN112817532A (en) * | 2021-01-27 | 2021-05-18 | 杭州爱科科技股份有限公司 | Data processing method, device and computer storage medium |
| CN114281242B (en) * | 2021-11-15 | 2024-05-10 | 北京智芯微电子科技有限公司 | Memory load balancing method, device and equipment |
| CN114281249B (en) * | 2021-11-30 | 2023-07-25 | 长江存储科技有限责任公司 | Flash memory particle improvement method, flash memory particle, memory and electronic equipment |
| CN115437580B (en) * | 2022-11-08 | 2023-03-24 | 合肥康芯威存储技术有限公司 | Data storage device management method and system and data storage device |
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