CN112463038A - Data invalidation method, system, equipment and medium - Google Patents
Data invalidation method, system, equipment and medium Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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Abstract
The invention discloses a data invalidation method, which comprises the following steps: responding to data block triggering data invalidation, and updating the number of valid data in the block information of the data block; reading the priority and the life information of the current record of the block information; calculating a new priority by using the life information and the updated effective data number; comparing the new priority with the priority recorded in the block information; and responding to the same comparison result of the two, and performing other operations of data invalidation. The invention also discloses a system, a computer device and a readable storage medium. According to the scheme provided by the invention, through a method for rapidly processing data invalidation, the locking operation on the address where the priority is located is not required to be carried out every time the VDFC is changed, the DDR access frequency is further reduced, and the performance is improved.
Description
Technical Field
The invention relates to the field of data invalidation, in particular to a method, a system, equipment and a storage medium for data invalidation.
Background
The OBS is based on PBA, namely, one OBS action is triggered by the invalidation of each PBA, the one OBS action comprises the operation of subtracting 1 of the VDFC, the VDFC comprises the VDFC in the blockinfo, after the subtraction is finished, the blockinfo is locked and read, the priority is recalculated through the latest VDFC in the blockinfo and is stored locally, the priority is compared with the priority in the blockinfo, if the priority is not consistent, the priority in the blockinfo is updated and is unlocked, and if the priority is consistent, the priority is unlocked only.
From the above, the OBS may trigger two DDR operations of blockinfo, and lock read, unlock, or write, which may cause a large pressure on DDR in the data set invalidation process due to the frequent OBS.
Disclosure of Invention
In view of the above, in order to overcome at least one aspect of the above problems, an embodiment of the present invention provides a method for invalidating data, including the following steps:
responding to data block triggering data invalidation, and updating the number of valid data in the block information of the data block;
reading the priority and the life information of the current record of the block information;
calculating a new priority by using the life information and the updated effective data number;
comparing the new priority with the priority recorded in the block information;
and responding to the same comparison result of the two, and performing other operations of data invalidation.
In some embodiments, further comprising:
and in response to the comparison result being different, locking the address corresponding to the recorded priority and updating the new priority to a corresponding plurality of bits in the corresponding address.
In some embodiments, locking the address corresponding to the priority of the record and updating the new priority to the corresponding bit in the corresponding address further comprises:
changing a preset bit of the address into a first zone bit representing a locking state;
and changing the preset bit from the first flag bit to a second flag bit representing an unlocking state in response to the completion of the updating.
In some embodiments, updating the number of valid data in the block information of the data block further includes:
acquiring the address of the number of the effective data;
and executing a decrement operation on the number of the effective data of the address record.
In some embodiments, calculating a new priority using the lifetime information and the updated number of valid data further comprises:
and carrying out a rounding-down operation on the calculated new priority.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a system for data invalidation, including:
the updating module is configured to respond to data block triggering data invalidation and update the number of valid data in the block information of the data block;
a reading module configured to read the priority and the lifetime information currently recorded by the block information;
a calculation module configured to calculate a new priority using the lifetime information and the updated number of valid data;
a comparison module configured to compare the new priority with a priority recorded in the block information;
a first response module configured to perform other operations of data invalidation in response to the comparison result being the same.
In some embodiments, further comprising a second response module configured to:
and in response to the comparison result being different, locking the address corresponding to the recorded priority and updating the new priority to a corresponding plurality of bits in the corresponding address.
In some embodiments, the second response module is further configured to:
changing a preset bit of the address into a first zone bit representing a locking state;
and changing the preset bit from the first flag bit to a second flag bit representing an unlocking state in response to the completion of the updating.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer apparatus, including:
at least one processor; and
a memory storing a computer program operable on the processor, wherein the processor executes the program to perform any of the steps of the method of data invalidation as described above.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer-readable storage medium storing a computer program which, when executed by a processor, performs the steps of any of the above-described data invalidation methods.
The invention has one of the following beneficial technical effects: according to the scheme provided by the invention, by a method for rapidly processing data invalidation, the locking operation on the address where the priority is located is not required any more every time the VDFC is changed, so that the DDR access times are reduced, the pressure is reduced, and the performance is improved.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a flow chart illustrating a method for invalidating data according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a data invalidation system according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a computer device provided in an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In the embodiment of the present invention, VDFC is valid dataframe count, and indicates the number of valid data. The OBS refers to dataframe object, and indicates that the data set is invalid. PBA is phsystematic address, which refers to the physical address of the data.
According to an aspect of the present invention, an embodiment of the present invention provides a method for invalidating data, which may include the steps of:
s1, responding to the data block triggering data invalidation, and updating the number of valid data in the block information of the data block;
s2, reading the priority and the life information of the current record of the block information;
s3, calculating a new priority by using the life information and the updated effective data number;
s4, comparing the new priority with the priority recorded in the block information;
and S5, responding to the same comparison result, and performing other operations of data invalidation.
According to the scheme provided by the invention, by a method for rapidly processing data invalidation, the locking operation on the address where the priority is located is not required every time the VDFC is changed, so that the DDR access times are reduced, and the performance is improved.
In some embodiments, in step S1, in response to a data BLOCK triggering data invalidation, the number of valid data in the BLOCK information of the data BLOCK is updated, specifically, each BLOCK has a corresponding BLOCK information, and the BLOCK information records a key state, a priority, a VDFC, lifetime information, and the like of the BLOCK, where the VDFC is recorded in a single U32 (minimum operation unit), and the priority and the key state information are recorded in another U32 together. The address information of each U32 may be obtained by an address offset. Since VDFCs are separately recorded in one U32, when a VDFC is updated, it is sufficient to update it directly.
In some embodiments, in step S3, a new priority is calculated by using the lifetime information and the updated valid data number, and specifically, the priority may be calculated by VDFC and PE.
In some embodiments, the priority may be calculated by:
prioriy＝VDFC*A+PE*B+C
wherein, A, B and C are preset weight values, and A is a number less than 1.
In some embodiments, updating the number of valid data in the block information of the data block further includes:
acquiring the address of the number of the effective data;
and executing a decrement operation on the number of the effective data of the address record.
Specifically, OBS is in PBA units, that is, one OBS action is triggered every invalidation of PBA, one OBS action includes a subtraction of 1 of VDFC, and the address of U32 where VDFC information is recorded can be obtained by obtaining address offset information, and since only VDFC information is recorded in the U32, when invalidation of data is triggered, only one subtraction of one needs to be directly performed on VDFC recorded at the address.
In some embodiments, calculating a new priority using the lifetime information and the updated number of valid data further comprises:
and carrying out a rounding-down operation on the calculated new priority.
Specifically, since the weight of the VDFC in the calculation priority formula is a number smaller than 1, the influence of the execution of the subtraction operation on the priority by the invalidation operation every time is small, and therefore the calculated priority is rounded down, so that the operation of updating the priority is triggered only after the VDFC executes the subtraction operation for multiple times, that is, only 1 OBS needs to execute the unlocking or writing operation after locking in each a OBS, and other OBSs only read the priority and do not have the unlocking or writing operation.
In some embodiments, further comprising:
and in response to the comparison result being different, locking the address corresponding to the recorded priority and updating the new priority to a corresponding plurality of bits in the corresponding address.
In some embodiments, locking the address corresponding to the priority of the record and updating the new priority to the corresponding bit in the corresponding address further comprises:
changing a preset bit of the address into a first zone bit representing a locking state;
and changing the preset bit from the first flag bit to a second flag bit representing an unlocking state in response to the completion of the updating.
Specifically, a bit in U32 recorded with priority information may be used to indicate a lock status, which indicates a lock status when it is a first flag (e.g., 1), and an unlock status when it is a second flag (e.g., 0). The priority information may occupy 13 bits in U32, and when it needs to be updated, only the information on the corresponding bit needs to be updated.
It should be noted that, when the lifetime is updated, even if the number of times of performing the decrementing operation does not reach a times, the priority information in U32 needs to be updated.
According to the scheme provided by the invention, by a method for rapidly processing data invalidation, the locking operation on the address where the priority is located is not required every time the VDFC is changed, so that the DDR access times are reduced, and the performance is improved.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a system 400 for invalidating data, as shown in fig. 2, including:
an updating module 401, where the updating module 401 is configured to respond to a data block triggering data invalidation and update the number of valid data in the block information of the data block;
a reading module 402, wherein the reading module 402 is configured to read the priority and the lifetime information currently recorded in the block information;
a calculating module 403, where the calculating module 403 is configured to calculate a new priority by using the lifetime information and the updated number of valid data;
a comparison module 404, the comparison module 404 configured to compare the new priority with the priority recorded in the block information;
a first response module 405, the first response module 405 configured to perform other operations of data invalidation in response to the comparison result being the same.
In some embodiments, further comprising a second response module configured to:
and in response to the comparison result being different, locking the address corresponding to the recorded priority and updating the new priority to a corresponding plurality of bits in the corresponding address.
In some embodiments, the second response module is further configured to:
changing a preset bit of the address into a first zone bit representing a locking state;
and changing the preset bit from the first flag bit to a second flag bit representing an unlocking state in response to the completion of the updating.
According to the scheme provided by the invention, through a method for rapidly processing data invalidation, the locking operation on the address where the priority is located is not required to be carried out every time the VDFC is changed, the DDR access frequency is further reduced, and the performance is improved.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 3, an embodiment of the present invention further provides a computer apparatus 501, comprising:
at least one processor 520; and
a memory 510, the memory 510 storing a computer program 511 executable on the processor, the processor 520 executing the program to perform any of the above-described method steps of data invalidation.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 4, an embodiment of the present invention further provides a computer-readable storage medium 601, where the computer-readable storage medium 601 stores computer program instructions 610, and the computer program instructions 610, when executed by a processor, perform the steps of any of the above data invalidation methods.
Finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes of the methods of the above embodiments may be implemented by a computer program to instruct related hardware to implement the methods.
Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps of implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A method of data invalidation comprising the steps of:
responding to data block triggering data invalidation, and updating the number of valid data in the block information of the data block;
reading the priority and the life information of the current record of the block information;
calculating a new priority by using the life information and the updated effective data number;
comparing the new priority with the priority recorded in the block information;
and responding to the same comparison result of the two, and performing other operations of data invalidation.
2. The method of claim 1, further comprising:
and in response to the comparison result being different, locking the address corresponding to the recorded priority and updating the new priority to a corresponding plurality of bits in the corresponding address.
3. The method of claim 2, wherein locking an address corresponding to the recorded priority and updating a new priority to corresponding bits in the corresponding address, further comprising:
changing a preset bit of the address into a first zone bit representing a locking state;
and changing the preset bit from the first flag bit to a second flag bit representing an unlocking state in response to the completion of the updating.
4. The method of claim 1, wherein updating the number of valid data in the block information of the data block, further comprises:
acquiring the address of the number of the effective data;
and executing a decrement operation on the number of the effective data of the address record.
5. The method of claim 1, wherein calculating a new priority using the age information and the updated number of valid data further comprises:
and carrying out a rounding-down operation on the calculated new priority.
6. A system for data invalidation comprising:
the updating module is configured to respond to data block triggering data invalidation and update the number of valid data in the block information of the data block;
a reading module configured to read the priority and the lifetime information currently recorded by the block information;
a calculation module configured to calculate a new priority using the lifetime information and the updated number of valid data;
a comparison module configured to compare the new priority with a priority recorded in the block information;
a first response module configured to perform other operations of data invalidation in response to the comparison result being the same.
7. The system of claim 6, further comprising a second response module configured to:
and in response to the comparison result being different, locking the address corresponding to the recorded priority and updating the new priority to a corresponding plurality of bits in the corresponding address.
8. The system of claim 7, wherein the second response module is further configured to:
changing a preset bit of the address into a first zone bit representing a locking state;
and changing the preset bit from the first flag bit to a second flag bit representing an unlocking state in response to the completion of the updating.
9. A computer device, comprising:
at least one processor; and
memory storing a computer program operable on the processor, characterized in that the processor executes the program to perform the steps of the method according to any of claims 1-5.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, is adapted to carry out the steps of the method according to any one of claims 1-5.
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| CN202011270435.XA CN112463038B (en) | 2020-11-13 | 2020-11-13 | Method, system, equipment and medium for invalidating data |
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| CN202011270435.XA CN112463038B (en) | 2020-11-13 | 2020-11-13 | Method, system, equipment and medium for invalidating data |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116578246A (en) * | 2023-07-05 | 2023-08-11 | 合肥康芯威存储技术有限公司 | Storage device and control method thereof |
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| CN110780812A (en) * | 2019-09-27 | 2020-02-11 | 苏州浪潮智能科技有限公司 | Method and device for invalidating hard disk data |
| CN111090398A (en) * | 2019-12-13 | 2020-05-01 | 北京浪潮数据技术有限公司 | Garbage recycling method, device and equipment for solid state disk and readable storage medium |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110780812A (en) * | 2019-09-27 | 2020-02-11 | 苏州浪潮智能科技有限公司 | Method and device for invalidating hard disk data |
| CN111090398A (en) * | 2019-12-13 | 2020-05-01 | 北京浪潮数据技术有限公司 | Garbage recycling method, device and equipment for solid state disk and readable storage medium |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116578246A (en) * | 2023-07-05 | 2023-08-11 | 合肥康芯威存储技术有限公司 | Storage device and control method thereof |
| CN116578246B (en) * | 2023-07-05 | 2023-09-29 | 合肥康芯威存储技术有限公司 | Storage device and control method thereof |
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