CN112463650A - Method, device and medium for managing L2P table under multi-core CPU - Google Patents

Method, device and medium for managing L2P table under multi-core CPU Download PDF

Info

Publication number
CN112463650A
CN112463650A CN202011359463.9A CN202011359463A CN112463650A CN 112463650 A CN112463650 A CN 112463650A CN 202011359463 A CN202011359463 A CN 202011359463A CN 112463650 A CN112463650 A CN 112463650A
Authority
CN
China
Prior art keywords
entry
state
current cpu
read
cpus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202011359463.9A
Other languages
Chinese (zh)
Inventor
尹作刚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Inspur Intelligent Technology Co Ltd
Original Assignee
Suzhou Inspur Intelligent Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Inspur Intelligent Technology Co Ltd filed Critical Suzhou Inspur Intelligent Technology Co Ltd
Priority to CN202011359463.9A priority Critical patent/CN112463650A/en
Publication of CN112463650A publication Critical patent/CN112463650A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7201—Logical to physical mapping or translation of blocks or pages

Abstract

The invention discloses a management method of an L2P table under a multi-core CPU, which comprises the following steps: responding to a read/write IO command received by a current CPU, and judging whether an L2P entry corresponding to the read/write IO command exists in a cache of the current CPU; in response to the corresponding L2P entry being present, obtaining a status of the corresponding L2P entry; the current CPU triggers the read or write operation of the data corresponding to the corresponding L2P item according to the state of the corresponding L2P item and the read or write IO command; updating the state of the L2P entry and/or notifying other CPUs to modify the state of a corresponding L2P entry in the other CPUs' caches in accordance with the read or write operation. The invention also discloses a computer device and a readable storage medium. The scheme provided by the invention can realize the management of the L2P table under the multi-core CPU, and simultaneously solves the consistency problems of the cache of a plurality of CPUs of data corresponding to the L2P entries and the main memory.

Description

Method, device and medium for managing L2P table under multi-core CPU
Technical Field
The invention relates to the field of L2P, in particular to a management method, equipment and a storage medium of an L2P table under a multi-core CPU.
Background
With the continuous development of storage systems, the SSD solid state disk continuously replaces a conventional hard disk, an L2P (mapping from a logical address to a physical address) table in the SSD plays an important role, during the read/write process of an IO command, a host issues an LBA to the SSD, the SSD queries an L2P table from a memory to find a corresponding PBA to perform the read/write operation of data, and if an entry of L2P hits in a Cache during the read/write process, the performance of the SSD is greatly improved, but in a multi-core CPU system, if the entry of L2P and corresponding data are stored in the Cache, the consistency of data corresponding to the same LBA entry in each CPU cannot be ensured. Therefore, a solution for maintaining data consistency in a multi-core CPU system is urgently needed.
Disclosure of Invention
In view of this, in order to overcome at least one aspect of the above problem, an embodiment of the present invention provides a method for managing an L2P table under a multi-core CPU, including the following steps:
responding to a read/write IO command received by a current CPU, and judging whether an L2P entry corresponding to the read/write IO command exists in a cache of the current CPU;
in response to the corresponding L2P entry being present, obtaining a status of the corresponding L2P entry;
the current CPU triggers the read or write operation of the data corresponding to the corresponding L2P item according to the state of the corresponding L2P item and the read or write IO command;
updating the state of the L2P entry and/or notifying other CPUs to modify the state of a corresponding L2P entry in the other CPUs' caches in accordance with the read or write operation.
In some embodiments, the current CPU triggers a read or write operation on data corresponding to the corresponding L2P entry according to the state of the L2P entry and the read or write IO command, further comprising:
in response to the status of the L2P entry being exclusive and the current CPU receiving the read IO command, directly reading data corresponding to the corresponding L2P entry from the current CPU's cache;
and in response to that the state of the L2P entry is an exclusive state and the current CPU receives the write IO command, directly performing write operation on data corresponding to the corresponding L2P entry in the cache of the current CPU.
In some embodiments, updating the state of the L2P entry and/or notifying other CPUs to modify the state of a corresponding L2P entry in the other CPUs' caches in accordance with the read or write operation further comprises:
in response to directly writing data corresponding to the corresponding L2P entry in the current CPU's cache, updating the state of the corresponding L2P entry from an exclusive state to a modified state;
in response to the state of the L2P entry being an exclusive state and the current CPU monitoring the other CPUs triggering to read data corresponding to the corresponding L2P entry in the memory, updating the state of the corresponding L2P entry from an exclusive state to a shared state;
in response to the status of the L2P entry being the exclusive state and the current CPU snooping that the other CPUs triggered writing the data corresponding to the corresponding L2P entry in the memory, updating the status of the corresponding L2P entry from the exclusive state to the invalid state.
In some embodiments, the current CPU triggers a read or write operation on data corresponding to the corresponding L2P entry according to the state of the L2P entry and the read or write IO command, further comprising:
in response to the state of the L2P entry being a shared state and the current CPU receiving the read IO command, directly reading data corresponding to the corresponding L2P entry from a memory or a cache of the current CPU;
and in response to that the state of the L2P entry is a shared state and the current CPU receives the write IO command, directly performing write operation on data corresponding to the corresponding L2P entry in the cache of the current CPU.
In some embodiments, updating the state of the L2P entry and/or notifying other CPUs to modify the state of a corresponding L2P entry in the other CPUs' caches in accordance with the read or write operation further comprises:
in response to directly writing data corresponding to the corresponding L2P entry in the cache of the current CPU, updating the state of the corresponding L2P entry from a shared state to a modified state, and notifying the other CPUs to update the states of the corresponding L2P entries in the caches of the other CPUs to an invalid state;
in response to the status of the L2P entry being a shared status and the current CPU snooping that the other CPUs triggered writing of data corresponding to the corresponding L2P entry in the memory, updating the status of the corresponding L2P entry from a shared status to an invalid status.
In some embodiments, the current CPU triggers a read or write operation on data corresponding to the corresponding L2P entry according to the state of the L2P entry and the read or write IO command, further comprising:
in response to the state of the L2P entry being a modified state and the current CPU receiving the read IO command, directly reading data corresponding to the corresponding L2P entry from the current CPU's cache;
in response to that the state of the L2P entry is a modified state and the current CPU receives the write IO command, directly performing a write operation on data corresponding to the corresponding L2P entry in the cache of the current CPU;
in response to the state of the L2P entry being modified and the current CPU snooping the data corresponding to the corresponding L2P entry in the other CPU trigger read or write memory, the current CPU writes back the data corresponding to the corresponding L2P entry in the cache to memory.
In some embodiments, updating the state of the L2P entry and/or notifying other CPUs to modify the state of a corresponding L2P entry in the other CPUs' caches in accordance with the read or write operation further comprises:
in response to the current CPU monitoring the data corresponding to the corresponding L2P entry in the other CPU trigger read memory, the current CPU updating the state of the corresponding L2P entry from a modified state to a shared state;
in response to the current CPU snooping the data corresponding to the corresponding L2P entry in the other CPU trigger write memory, the current CPU updates the state of the corresponding L2P entry from a modified state to an invalid state.
In some embodiments, the current CPU triggers a read or write operation on data corresponding to the corresponding L2P entry according to the state of the L2P entry and the read or write IO command, further comprising:
in response to the state of the L2P entry being an invalid state and the current CPU receiving the read IO command, directly reading data corresponding to the corresponding L2P entry from a memory;
in response to that the status of the L2P entry is invalid and the current CPU receives the write IO command, directly performing a write operation on data corresponding to the corresponding L2P entry in the cache of the current CPU;
updating the state of the L2P entry and/or notifying other CPUs in accordance with the read or write operation to modify the state of a corresponding L2P entry in the other CPUs' caches, further comprising:
in response to the current CPU reading data corresponding to the corresponding L2P entry directly from memory and no data corresponding to the corresponding L2P entry in the other CPUs, the current CPU updating the state of the corresponding L2P entry from an invalid state to an exclusive state;
in response to the current CPU reading data corresponding to the corresponding L2P entry directly from memory and there being data corresponding to the corresponding L2P entry in the other CPUs, the current CPU updating the state of the corresponding L2P entry from an invalid state to a shared state;
in response to the current CPU directly writing data corresponding to the corresponding L2P entry in the current CPU's cache and no data corresponding to the corresponding L2P entry in the other CPUs, the current CPU updating the state of the corresponding L2P entry from an invalid state to a modified state;
in response to the current CPU directly writing data corresponding to the corresponding L2P entry in the current CPU's cache and the other CPUs having data corresponding to the corresponding L2P entry, the current CPU updates the state of the corresponding L2P entry from invalid state to modified state and notifies the other CPUs to update the state of the corresponding L2P entry in the other CPUs' caches to invalid state.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer apparatus, including:
at least one processor; and
a memory storing a computer program executable on the processor, wherein the processor executes the program to perform the steps of any of the methods for managing the L2P table under the multicore CPU as described above.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention also provides a computer-readable storage medium storing a computer program which, when executed by a processor, performs the steps of any one of the methods for managing the L2P table under the multi-core CPU as described above.
The invention has one of the following beneficial technical effects: the scheme provided by the invention can realize the management of the L2P table under the multi-core CPU, and simultaneously solves the consistency problems of the cache of a plurality of CPUs of data corresponding to the L2P entries and the main memory.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
Fig. 1 is a schematic flowchart of a method for managing an L2P table under a multi-core CPU according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for managing an L2P table under a multi-core CPU according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a computer device provided in an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In the embodiment of the present invention, L2P represents the mapping from a Logical address to a Physical address for Logical block address to Physical block address; i is Invalid, which represents Invalid state; s is Shared and represents a Shared state; e is Exclusive and represents an Exclusive state; m is Modified and represents an invalid state; LR represents the reading operation of the CPU on the data in the local cache, and LW represents the writing operation of the CPU on the data in the local cache; LR represents the read operation of the CPU to the data in the remote memory, and LW represents the write operation of the CPU to the data in the remote memory.
According to an aspect of the present invention, an embodiment of the present invention proposes a method for managing an L2P table under a multi-core CPU, as shown in fig. 1, which may include the steps of:
s1, responding to the current CPU receiving a read/write IO command, judging whether an L2P entry corresponding to the read/write IO command exists in the cache of the current CPU;
s2, in response to the corresponding L2P entry being present, obtaining a status of the corresponding L2P entry;
s3, the current CPU triggers the read or write operation of the data corresponding to the corresponding L2P item according to the state of the corresponding L2P item and the read or write IO command;
s4, according to the read or write operation, updating the state of the L2P item and/or informing other CPUs to modify the state of the corresponding L2P item in the caches of the other CPUs.
The scheme provided by the invention can realize the management of the L2P table under the multi-core CPU, and simultaneously solves the consistency problems of the cache of a plurality of CPUs of data corresponding to the L2P entries and the main memory.
In some embodiments, as shown in fig. 2, a dedicated L2P Cache management controller may be added, primarily for local L2P data access and remote L2P data snoop access.
The state of an L2P entry is divided into an Invalid state, a Modified state, an Exclusive state and a Shared state in an L2P Cache controller, and the protocol definition of each L2P entry in the Cache controller is as follows:
status of state Memory address L2P item
Each CPU under the multi-core CPU is provided with 1L 2P Cache controller for managing a plurality of Cache entries of L2P; each L2P Cache controller is used for performing data snooping and broadcasting actions of a data bus, and can know remote L2P read operations or write operations initiated by other CPUs through bus snooping, and meanwhile, the local L2P Cache controller can know read-write operations of the local CPU on local L2P Cache entries, and if data inconsistency is caused by local operations, notify the L2P Cache controllers of other CPUs of modifying the states of the L2P entries. CPU operations on L2P entries include read local L2P data (LR) and write local L2P data (LW), and CPU operations on L2P entries include read memory L2P data (RR) and write memory L2P data (RW). Thus, there are four states for the L2P entry, and 4 more operations that cause the L2P entry to change, all the Cache controller and CPU need to do is to maintain these 16 states.
In some embodiments, when the SSD is initialized, all L2P entries are pre-allocated with addresses in the memory, there is no corresponding L2P Cache entry in the caches inside all CPUs, when the host issues a read IO command or a write IO command, a CPU is triggered to initiate an RR action, the Cache controller reads data from the memory into the Cache of the current CPU, and the L2P entry is in an E state (exclusive state, where only the current CPU has data and is consistent with the memory), and at this time, if there is another CPU that also reads data, the state is modified to S (shared, where multiple CPUs have the same data and are consistent with the memory); if one CPU generates an LW (data write) action of L2P data, the data state in the CPU is modified to M (modified state, having the latest data and inconsistent with the main memory but based on the current CPU), the Cache controller informs other CPUs having the L2P Cache data of data failure and modifies the state to I (invalid state, data in the main memory is considered inconsistent, and data cannot be obtained again) in a broadcasting mode.
In some embodiments, in step S3, the current CPU triggering, according to the state of the L2P entry and the read or write IO command, a read or write operation on data corresponding to the corresponding L2P entry, further includes:
in response to the status of the L2P entry being exclusive and the current CPU receiving the read IO command, directly reading data corresponding to the corresponding L2P entry from the current CPU's cache;
and in response to that the state of the L2P entry is an exclusive state and the current CPU receives the write IO command, directly performing write operation on data corresponding to the corresponding L2P entry in the cache of the current CPU.
In some embodiments, step S4, updating the state of the L2P entry and/or notifying other CPUs to modify the state of the corresponding L2P entry in the caches of the other CPUs according to the read or write operation, further comprises:
in response to directly writing data corresponding to the corresponding L2P entry in the current CPU's cache, updating the state of the corresponding L2P entry from an exclusive state to a modified state;
in response to the state of the L2P entry being an exclusive state and the current CPU monitoring the other CPUs triggering to read data corresponding to the corresponding L2P entry in the memory, updating the state of the corresponding L2P entry from an exclusive state to a shared state;
in response to the status of the L2P entry being the exclusive state and the current CPU snooping that the other CPUs triggered writing the data corresponding to the corresponding L2P entry in the memory, updating the status of the corresponding L2P entry from the exclusive state to the invalid state.
Specifically, the Exclusive state (Exclusive) indicates that the data state in the current CPU is Exclusive, indicates that the current CPU has Exclusive data (other CPUs have no data), and is consistent with the data of the main memory.
When LR operation occurs, data is directly acquired from the local cache, and the state is unchanged; when an LW operation occurs, i.e., data in the local Cache is modified, the state is modified to M (since there is no data in other CPUs, there is no sharing problem, and there is no need to notify other CPUs to modify the state of L2P Cache to I).
Because the local Cache has the latest data, RR and RW cannot occur in the Cache operation of the current CPU, when the Cache controller monitors that RR occurs on the bus, other CPUs are bound to have read operation of the main memory, and the RR operation cannot cause data modification, so that the data in the two CPUs are consistent with the data in the main memory, and the state of the L2P Cache is modified to be S; similarly, when the cache controller monitors that the bus has RW, other CPUs write the latest data back to the main memory, and at the moment, in order to ensure cache consistency, the data state of the current CPU is modified to I.
In some embodiments, in step S3, the current CPU triggering, according to the state of the L2P entry and the read or write IO command, a read or write operation on data corresponding to the corresponding L2P entry, further includes:
in response to the state of the L2P entry being a shared state and the current CPU receiving the read IO command, directly reading data corresponding to the corresponding L2P entry from a memory or a cache of the current CPU;
and in response to that the state of the L2P entry is a shared state and the current CPU receives the write IO command, directly performing write operation on data corresponding to the corresponding L2P entry in the cache of the current CPU.
In some embodiments, step S4, updating the state of the L2P entry and/or notifying other CPUs to modify the state of the corresponding L2P entry in the caches of the other CPUs according to the read or write operation, further comprises:
in response to directly writing data corresponding to the corresponding L2P entry in the cache of the current CPU, updating the state of the corresponding L2P entry from a shared state to a modified state, and notifying the other CPUs to update the states of the corresponding L2P entries in the caches of the other CPUs to an invalid state;
in response to the status of the L2P entry being a shared status and the current CPU snooping that the other CPUs triggered writing of data corresponding to the corresponding L2P entry in the memory, updating the status of the corresponding L2P entry from a shared status to an invalid status.
Specifically, the Shared state (Shared) indicates that the data state in the current CPU is Shared, indicates that the current CPU shares data with other CPUs, and the data is consistent among multiple CPUs, and the data among the multiple CPUs is consistent with the main memory.
When LR operation occurs, data is directly acquired from the local cache, and the state is unchanged; when an LW operation occurs, that is, a local write operation occurs, the write operation is directly performed on the data corresponding to the corresponding L2P entry in the Cache of the current CPU, but the data is not immediately written back to the main memory, but is written back to the main memory at a later time, so that in order to ensure Cache consistency, the L2P Cache state of the current CPU is modified to M, and other CPUs having the data are notified that the data is invalid, and the L2P Cache states are modified to I by the other CPUs;
because the local cache has the latest data, RR and RW cannot occur in the current CPU cache operation, when the cache controller monitors RR on the bus, other CPUs are bound to have read operation of the main memory, and RR operation cannot cause data modification, so the state is unchanged, and the data in a plurality of CPUs are consistent with the main memory; similarly, when the Cache controller monitors that the bus has RW, which means that other CPUs have write operations to the main memory, the data in the local Cache is neither the latest data nor consistent with the main memory, so that the state of the L2P Cache of the current CPU is modified to I.
In some embodiments, in step S3, the current CPU triggering, according to the state of the L2P entry and the read or write IO command, a read or write operation on data corresponding to the corresponding L2P entry, further includes:
in response to the state of the L2P entry being a modified state and the current CPU receiving the read IO command, directly reading data corresponding to the corresponding L2P entry from the current CPU's cache;
in response to that the state of the L2P entry is a modified state and the current CPU receives the write IO command, directly performing a write operation on data corresponding to the corresponding L2P entry in the cache of the current CPU;
in response to the state of the L2P entry being modified and the current CPU snooping the data corresponding to the corresponding L2P entry in the other CPU trigger read or write memory, the current CPU writes back the data corresponding to the corresponding L2P entry in the cache to memory.
In some embodiments, step S4, updating the state of the L2P entry and/or notifying other CPUs to modify the state of the corresponding L2P entry in the caches of the other CPUs according to the read or write operation, further comprises:
in response to the current CPU monitoring the data corresponding to the corresponding L2P entry in the other CPU trigger read memory, the current CPU updating the state of the corresponding L2P entry from a modified state to a shared state;
in response to the current CPU snooping the data corresponding to the corresponding L2P entry in the other CPU trigger write memory, the current CPU updates the state of the corresponding L2P entry from a modified state to an invalid state.
Specifically, the Modified state (Modified) indicates that the state of the data in the current CPU is Modified, which indicates that the current CPU has the latest data, and although the data in the main memory and the data in the current CPU are not consistent, the data in the current CPU is used as the standard.
When LR operation occurs, namely data is directly acquired from the local cache, the latest data is possessed, and therefore the state is unchanged; when LW operation occurs, namely data in the local cache is directly modified, the current CPU has the latest data after modification, and therefore the state is unchanged.
Because the local cache has the latest data, the current CPU does not generate RR and RW, when the local L2P cache controller monitors that RR occurs on the bus, the operation of reading the main memory of other CPUs is inevitable, at this time, in order to ensure consistency, the current CPU should write the data back to the main memory, and the subsequent RR will make other CPUs and the current CPU have common data, so the state is modified to S; similarly, when the cache controller detects that the bus has RW, the current CPU will write the data back to the main memory, because the subsequent RW will cause the data in the main memory to be modified, and thus the state is modified to I.
In some embodiments, in step S3, the current CPU triggering, according to the state of the L2P entry and the read or write IO command, a read or write operation on data corresponding to the corresponding L2P entry, further includes:
in response to the state of the L2P entry being an invalid state and the current CPU receiving the read IO command, directly reading data corresponding to the corresponding L2P entry from a memory;
in response to that the status of the L2P entry is invalid and the current CPU receives the write IO command, directly performing a write operation on data corresponding to the corresponding L2P entry in the cache of the current CPU;
step S4, updating the status of the L2P entry according to the read or write operation and/or notifying other CPUs to modify the status of the corresponding L2P entry in the caches of the other CPUs, further comprising:
in response to the current CPU reading data corresponding to the corresponding L2P entry directly from memory and no data corresponding to the corresponding L2P entry in the other CPUs, the current CPU updating the state of the corresponding L2P entry from an invalid state to an exclusive state;
in response to the current CPU reading data corresponding to the corresponding L2P entry directly from memory and there being data corresponding to the corresponding L2P entry in the other CPUs, the current CPU updating the state of the corresponding L2P entry from an invalid state to a shared state;
in response to the current CPU directly writing data corresponding to the corresponding L2P entry in the current CPU's cache and no data corresponding to the corresponding L2P entry in the other CPUs, the current CPU updating the state of the corresponding L2P entry from an invalid state to a modified state;
in response to the current CPU directly writing data corresponding to the corresponding L2P entry in the current CPU's cache and the other CPUs having data corresponding to the corresponding L2P entry, the current CPU updates the state of the corresponding L2P entry from invalid state to modified state and notifies the other CPUs to update the state of the corresponding L2P entry in the other CPUs' caches to invalid state.
Specifically, the Invalid state (Invalid) indicates that the current CPU is Invalid and unavailable data, and other CPUs may or may not have data.
Because the current CPU's L2P Cache data is not available, LR operations will not occur, and RR operations will only occur, the situation at this time is as follows:
A. if no data exists in other CPUs, the state is modified to E;
B. if the other CPUs have data and the state is S or E, the state is modified to S;
C. if other CPUs have data and the state is M, the other CPUs firstly generate RW to write the data in the M state back to the main memory and modify the state to be S, and then the current CPU reads the data in the main memory and modifies the state to be S;
because the current CPU's L2P Cache data is invalid, it happens that LW will directly operate local L2P Cache, the situation at this time is as follows:
A. if no data exists in other CPUs, modifying the state of the current L2P Cache to M;
B. if the other CPUs have data and the state is S or E, modifying the local Cache, informing the other CPUs of modifying the data into I, and modifying the state of the L2P Cache in the current CPU into M;
C. if the other CPUs have data and the state is M, the other CPUs write the data back to the main memory firstly, the state is modified into I, and the state of the L2P Cache in the current CPU is modified into M;
when the RR operation of the bus is monitored, other CPUs read the memory and are irrelevant to the local L2P Cache, and the state is unchanged; and (3) monitoring the bus to generate RW operation, wherein the RW operation indicates that other CPUs write the main memory, and the state is unchanged, and is irrelevant to the local L2P Cache.
According to the scheme provided by the invention, an L2P Cache controller is added below each CPU and is used for specially managing Cache entries of a plurality of L2P and data monitoring and broadcasting actions of a data bus, remote L2P read operation or write operation initiated by other CPUs can be known through bus monitoring, and meanwhile, a local L2P Cache controller can know read-write operation of a local CPU on a local L2P Cache entry; the request processing of consistent access is effectively guaranteed under four states and four different actions of each L2P Cache entry, the access speed of the L2P entries is improved, and the overall performance of the SSD is effectively improved. Therefore, management of the L2P table under the multi-core CPU can be realized, and the problem of consistency on caches and main memories of a plurality of CPUs of data corresponding to the L2P entries is solved. Meanwhile, the time and efficiency of accessing the L2P table are improved, the management of the L2P table in the SSD can be effectively completed, and the performance of the SSD can be improved.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 3, an embodiment of the present invention further provides a computer apparatus 501, comprising:
at least one processor 520; and
the memory 510 and the memory 510 store a computer program 511 that can be executed on the processor, and the processor 520 executes the program to execute the steps of the method for managing the L2P table in the multi-core CPU.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 4, an embodiment of the present invention further provides a computer-readable storage medium 601, where the computer-readable storage medium 601 stores computer program instructions 610, and the computer program instructions 610, when executed by a processor, perform the steps of the method for managing the L2P table under the multi-core CPU as any one of the above.
Finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes of the methods of the above embodiments may be implemented by a computer program to instruct related hardware to implement the methods.
Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps of implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims (10)

1. A method for managing an L2P table under a multi-core CPU is characterized by comprising the following steps:
responding to a read/write IO command received by a current CPU, and judging whether an L2P entry corresponding to the read/write IO command exists in a cache of the current CPU;
in response to the corresponding L2P entry being present, obtaining a status of the corresponding L2P entry;
the current CPU triggers the read or write operation of the data corresponding to the corresponding L2P item according to the state of the corresponding L2P item and the read or write IO command;
updating the state of the L2P entry and/or notifying other CPUs to modify the state of a corresponding L2P entry in the other CPUs' caches in accordance with the read or write operation.
2. The method of claim 1, wherein the current CPU triggers a read or write operation on data corresponding to the corresponding L2P entry according to the state of the L2P entry and the read or write IO command, further comprising:
in response to the status of the L2P entry being exclusive and the current CPU receiving the read IO command, directly reading data corresponding to the corresponding L2P entry from the current CPU's cache;
and in response to that the state of the L2P entry is an exclusive state and the current CPU receives the write IO command, directly performing write operation on data corresponding to the corresponding L2P entry in the cache of the current CPU.
3. The method as in claim 2 wherein updating the state of the L2P entry and/or notifying other CPUs to modify the state of a corresponding L2P entry in the other CPUs' cache in accordance with the read or write operation further comprises:
in response to directly writing data corresponding to the corresponding L2P entry in the current CPU's cache, updating the state of the corresponding L2P entry from an exclusive state to a modified state;
in response to the state of the L2P entry being an exclusive state and the current CPU monitoring the other CPUs triggering to read data corresponding to the corresponding L2P entry in the memory, updating the state of the corresponding L2P entry from an exclusive state to a shared state;
in response to the status of the L2P entry being the exclusive state and the current CPU snooping that the other CPUs triggered writing the data corresponding to the corresponding L2P entry in the memory, updating the status of the corresponding L2P entry from the exclusive state to the invalid state.
4. The method of claim 1, wherein the current CPU triggers a read or write operation on data corresponding to the corresponding L2P entry according to the state of the L2P entry and the read or write IO command, further comprising:
in response to the state of the L2P entry being a shared state and the current CPU receiving the read IO command, directly reading data corresponding to the corresponding L2P entry from a memory or a cache of the current CPU;
and in response to that the state of the L2P entry is a shared state and the current CPU receives the write IO command, directly performing write operation on data corresponding to the corresponding L2P entry in the cache of the current CPU.
5. The method as in claim 4 wherein updating the state of the L2P entry and/or notifying other CPUs of a modification to the state of a corresponding L2P entry in the other CPUs' caches in accordance with the read or write operation further comprises:
in response to directly writing data corresponding to the corresponding L2P entry in the cache of the current CPU, updating the state of the corresponding L2P entry from a shared state to a modified state, and notifying the other CPUs to update the states of the corresponding L2P entries in the caches of the other CPUs to an invalid state;
in response to the status of the L2P entry being a shared status and the current CPU snooping that the other CPUs triggered writing of data corresponding to the corresponding L2P entry in the memory, updating the status of the corresponding L2P entry from a shared status to an invalid status.
6. The method of claim 1, wherein the current CPU triggers a read or write operation on data corresponding to the corresponding L2P entry according to the state of the L2P entry and the read or write IO command, further comprising:
in response to the state of the L2P entry being a modified state and the current CPU receiving the read IO command, directly reading data corresponding to the corresponding L2P entry from the current CPU's cache;
in response to that the state of the L2P entry is a modified state and the current CPU receives the write IO command, directly performing a write operation on data corresponding to the corresponding L2P entry in the cache of the current CPU;
in response to the state of the L2P entry being modified and the current CPU snooping the data corresponding to the corresponding L2P entry in the other CPU trigger read or write memory, the current CPU writes back the data corresponding to the corresponding L2P entry in the cache to memory.
7. The method as in claim 6 wherein updating the state of the L2P entry and/or notifying other CPUs of a modification to the state of a corresponding L2P entry in the other CPUs' caches in accordance with the read or write operation further comprises:
in response to the current CPU monitoring the data corresponding to the corresponding L2P entry in the other CPU trigger read memory, the current CPU updating the state of the corresponding L2P entry from a modified state to a shared state;
in response to the current CPU snooping the data corresponding to the corresponding L2P entry in the other CPU trigger write memory, the current CPU updates the state of the corresponding L2P entry from a modified state to an invalid state.
8. The method of claim 1, wherein the current CPU triggers a read or write operation on data corresponding to the corresponding L2P entry according to the state of the L2P entry and the read or write IO command, further comprising: in response to the state of the L2P entry being an invalid state and the current CPU receiving the read IO command, directly reading data corresponding to the corresponding L2P entry from a memory; in response to that the status of the L2P entry is invalid and the current CPU receives the write IO command, directly performing a write operation on data corresponding to the corresponding L2P entry in the cache of the current CPU;
updating the state of the L2P entry and/or notifying other CPUs in accordance with the read or write operation to modify the state of a corresponding L2P entry in the other CPUs' caches, further comprising: in response to the current CPU reading data corresponding to the corresponding L2P entry directly from memory and no data corresponding to the corresponding L2P entry in the other CPUs, the current CPU updating the state of the corresponding L2P entry from an invalid state to an exclusive state; in response to the current CPU reading data corresponding to the corresponding L2P entry directly from memory and there being data corresponding to the corresponding L2P entry in the other CPUs, the current CPU updating the state of the corresponding L2P entry from an invalid state to a shared state; in response to the current CPU directly writing data corresponding to the corresponding L2P entry in the current CPU's cache and no data corresponding to the corresponding L2P entry in the other CPUs, the current CPU updating the state of the corresponding L2P entry from an invalid state to a modified state; in response to the current CPU directly writing data corresponding to the corresponding L2P entry in the current CPU's cache and the other CPUs having data corresponding to the corresponding L2P entry, the current CPU updates the state of the corresponding L2P entry from invalid state to modified state and notifies the other CPUs to update the state of the corresponding L2P entry in the other CPUs' caches to invalid state.
9. A computer device, comprising:
at least one processor; and
memory storing a computer program operable on the processor, wherein the processor executes the program to perform the steps of the method according to any of claims 1-8.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, is adapted to carry out the steps of the method according to any one of claims 1 to 8.
CN202011359463.9A 2020-11-27 2020-11-27 Method, device and medium for managing L2P table under multi-core CPU Pending CN112463650A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011359463.9A CN112463650A (en) 2020-11-27 2020-11-27 Method, device and medium for managing L2P table under multi-core CPU

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011359463.9A CN112463650A (en) 2020-11-27 2020-11-27 Method, device and medium for managing L2P table under multi-core CPU

Publications (1)

Publication Number Publication Date
CN112463650A true CN112463650A (en) 2021-03-09

Family

ID=74809127

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011359463.9A Pending CN112463650A (en) 2020-11-27 2020-11-27 Method, device and medium for managing L2P table under multi-core CPU

Country Status (1)

Country Link
CN (1) CN112463650A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11960397B2 (en) 2022-06-16 2024-04-16 Western Digital Technologies, Inc. Data mapping comparison for improved synchronization in data storage devices

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101523361A (en) * 2006-10-17 2009-09-02 Arm有限公司 Handling of write access requests to shared memory in a data processing apparatus
US20090276578A1 (en) * 2008-04-30 2009-11-05 Moyer William C Cache coherency protocol in a data processing system
CN102929832A (en) * 2012-09-24 2013-02-13 杭州中天微系统有限公司 Cache-coherence multi-core processor data transmission system based on no-write allocation
CN110083545A (en) * 2018-01-25 2019-08-02 爱思开海力士有限公司 Data storage device and its operating method
CN110569001A (en) * 2019-09-17 2019-12-13 深圳忆联信息系统有限公司 Solid state disk-based method and device for marking dirty bit of L2P table
CN111651376A (en) * 2020-07-06 2020-09-11 Oppo广东移动通信有限公司 Data reading and writing method, processor chip and computer equipment

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101523361A (en) * 2006-10-17 2009-09-02 Arm有限公司 Handling of write access requests to shared memory in a data processing apparatus
US20090276578A1 (en) * 2008-04-30 2009-11-05 Moyer William C Cache coherency protocol in a data processing system
CN102929832A (en) * 2012-09-24 2013-02-13 杭州中天微系统有限公司 Cache-coherence multi-core processor data transmission system based on no-write allocation
CN110083545A (en) * 2018-01-25 2019-08-02 爱思开海力士有限公司 Data storage device and its operating method
CN110569001A (en) * 2019-09-17 2019-12-13 深圳忆联信息系统有限公司 Solid state disk-based method and device for marking dirty bit of L2P table
CN111651376A (en) * 2020-07-06 2020-09-11 Oppo广东移动通信有限公司 Data reading and writing method, processor chip and computer equipment

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
吴瑞阳等: "龙芯GS464E处理器核架构设计", 《中国科学:信息科学》 *
郑安兵等: "Nios II多核系统缓存一致性解决方案", 《微计算机信息》 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11960397B2 (en) 2022-06-16 2024-04-16 Western Digital Technologies, Inc. Data mapping comparison for improved synchronization in data storage devices

Similar Documents

Publication Publication Date Title
US7107411B2 (en) Apparatus method and system for fault tolerant virtual memory management
US10402327B2 (en) Network-aware cache coherence protocol enhancement
CN107329704B (en) Cache mirroring method and controller
US10176098B2 (en) Method and apparatus for data cache in converged system
CN107341114B (en) Directory management method, node controller and system
GB2539383A (en) Cache coherency
EP2972899B1 (en) Providing local cache coherency in a shared storage environment
CN106227674B (en) Cache coherence controller and method
EP2629206B1 (en) Directory replacement method and device
CN110287129B (en) L2P table updating and writing management method and device based on solid state disk
US11625326B2 (en) Management of coherency directory cache entry ejection
CN111651376A (en) Data reading and writing method, processor chip and computer equipment
EP4200708A1 (en) Scalable region-based directory
WO2016206070A1 (en) File updating method and storage device
CN106164874B (en) Method and device for accessing data visitor directory in multi-core system
CN112463650A (en) Method, device and medium for managing L2P table under multi-core CPU
CN111611223A (en) Nonvolatile data access method, system, electronic device and medium
EP3343380A1 (en) Data read method and apparatus
US11755485B2 (en) Snoop filter device
US9684598B1 (en) Method and apparatus for fast distributed cache re-sync after node disconnection
US6996675B2 (en) Retrieval of all tag entries of cache locations for memory address and determining ECC based on same
KR102570030B1 (en) Multiprocessor system and data management method thereof
US20230100746A1 (en) Multi-level partitioned snoop filter
CN117667987A (en) Storage system, data updating method and device
CN111788562A (en) Atomic operation execution method and device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20210309