CN112447629A

CN112447629A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN112447629A
Application number: CN202010856135.3A
Authority: CN
Inventors: 吴仲融; 董志航; 邵栋梁; 萧胜聪; 王仁佑
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2019-08-28
Filing date: 2020-08-24
Publication date: 2021-03-05
Also published as: KR20210028071A; TW202109787A; TWI735317B; KR102423373B1

Abstract

A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a back surface opposite the active surface. The rear surface has a cooling zone and a peripheral zone enclosing the cooling zone. The first die includes a micro-groove in the cooling region of the back surface. The cooling cap is stacked on the first die. The cooling cap includes a fluid inlet port and a fluid outlet port located above the cooling region and in communication with the microchannels.

Description

Semiconductor device and method for manufacturing the same

Technical Field

Embodiments relate to a semiconductor device and a method of manufacturing the same.

Background

With the increasing miniaturization of electronic products, heat dissipation (heat dissipation) of the packaged die has become an important issue in packaging technology. In addition, for multi-die packages, the arrangement of the dies has affected the speed of data transfer between the dies and the reliability of the packaged product.

Disclosure of Invention

According to some embodiments of the present invention, a semiconductor device is provided. The semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a back surface opposite the active surface. The rear surface has a cooling zone and a peripheral zone enclosing the cooling zone. The first die includes a plurality of microchannels in a cooling region of the back surface. The cooling cap is stacked on the first die. The cooling cap includes a fluid inlet port and a fluid outlet port located above the cooling zone and in communication with the plurality of microchannels.

According to some embodiments of the present invention, a semiconductor device is provided. The semiconductor device includes a package and a cooling cover. The package includes a substrate, an interposer, and a die. An interposer is disposed over and electrically connected to the substrate. The die is disposed over and electrically connected to the interposer. The die includes a continuous ring pattern and a plurality of discontinuous patterns enclosed by the continuous ring pattern on an upper surface of the die opposite the interposer. The cooling cap is stacked on the die. The cooling cap includes a fluid inlet port and a fluid outlet port positioned over the plurality of discontinuous patterns.

According to some embodiments of the present invention, a method of manufacturing a semiconductor device is provided. The method comprises at least the following steps. A die is provided. The die has an active surface and a back surface opposite the active surface. The rear surface has a cooling zone and a peripheral zone enclosing the cooling zone. A plurality of micro-grooves are formed in the cooling region of the rear surface. The die is placed on the interposer such that the active surface of the die faces the interposer. An interposer is placed on a substrate. A cooling cap is attached to the back surface of the die. The cooling cap includes a fluid inlet port and a fluid outlet port located above the cooling zone and in communication with the plurality of microchannels.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

Fig. 1A through 1F are schematic cross-sectional views illustrating structures formed at various stages of a method of manufacturing a package according to some embodiments of the present disclosure.

Fig. 2A and 2B are each a schematic top view of a die according to some embodiments of the present disclosure.

Fig. 3A to 3C are schematic top views of microcolumns, respectively, according to some embodiments of the present disclosure.

Fig. 4A and 4B are each a schematic cross-sectional view of a die according to some embodiments of the present disclosure.

Fig. 5A and 5B are each a schematic cross-sectional view of a die according to some embodiments of the present disclosure.

Fig. 6A and 6B are each a schematic cross-sectional view of a die according to some embodiments of the present disclosure.

Fig. 7A is a schematic top view of a die according to some embodiments of the present disclosure.

Fig. 7B through 7D are each a schematic cross-sectional view of a die according to some embodiments of the present disclosure.

Fig. 8A is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure.

Fig. 8B is a schematic cross-sectional view of a semiconductor device in use, according to some embodiments of the present disclosure.

Fig. 8C is a schematic top view of a semiconductor device in use, according to some embodiments of the present disclosure.

Fig. 9A is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

Fig. 9B is a schematic side view of a semiconductor device according to some embodiments of the present disclosure.

Fig. 9C is a schematic side view of a semiconductor device according to some embodiments of the present disclosure.

Fig. 10A through 10D are schematic perspective views of cooling caps, respectively, according to some embodiments of the present disclosure.

Description of the reference numerals

10. 12: package member

15. 25, 35, 45: semiconductor device with a plurality of transistors

100: semiconductor wafer

101. 111, 131, 210: semiconductor substrate

101 a: anterior surface

110. 110A, 110B, 130, 1101, 1102, 1103, 1104, 1105: tube core

110 s: edge of a container

111 a: active surface

111r, 131 r: rear surface

113. 133: contact pad

115. 135, and (3) adding: passivation layer

117. 1171, 1172, 1173, 1175: discontinuous pattern

117A: stripe pattern

117B, 117B1, 117B2, 117B 3: microcolumn

119: continuous ring pattern

120. 121, 122, 1201, 1202, 1203, 1204, 1205: micro-groove

120A: stripe-shaped micro-groove

120B: net-shaped micro-groove

200: interposer

220: semiconductor via

230: interconnection structure

231: dielectric layer

233: conductive trace

300. 310: conductive terminal

400: substrate

400b, 1201b, 1202b, 1203b, 1204 b: bottom surface

400 t: top surface of the container

500: connecting terminal

600A, 600B, 600C, 600D, 600E: cooling cover

610: shell body

612: floor panel/panel

614: side panel/panel

616: roof panel/panel

620. 6201, 6202, 6203, 6204: fluid port

620 in: fluid inlet port

620 out: fluid outlet port

622in, 622 out: interface pipe

624in, 624 out: connecting pipe

630. 6301, 6302, 6303: fluid channel

630 in: fluid inlet channel

630 out: fluid outlet channel

640: sealing groove

650. 660: vertical pipe

661: narrower fluid port

662: wider fluid port

700: sealing ring

810: screw nail

820: clamp apparatus

822: upper arm

824: lower arm

826: clamp main body

830: heat dissipation layer

1174: discontinuous/stripe pattern

1191. 1192, 1193, 1194: segment of

1201s, 1202s, 1203s, 1204 s: side wall

C-C: cutting wire

CL: cooling fluid

CS: circulation space

CR: cooling zone

D: depth of field

D1: first flow direction

D2: second direction

L: length of

P: pitch of

PR: peripheral region

R: tip end

T111: maximum thickness

W: width of

I-I, II-II, III-III, IV-IV: thread

α: angle of rotation

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms such as "below …", "below …", "lower", "above …", "upper" and the like may be used herein to describe the relationship of one element or feature to another element or feature for ease of description, as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Other features and processes may also be included. For example, test structures may be included to facilitate verification testing of three-dimensional (3D) packages or three-dimensional integrated circuit (3 DIC) devices. The test structures may include, for example, test pads (test pads) formed in a redistribution layer or on a substrate, which allow for testing of three-dimensional packages or three-dimensional integrated circuits, use of probes and/or probe cards (probe cards), and the like. Verification tests may be performed on the intermediate structures and the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methods that include verifying known good dies (innown good die) at an intermediate stage to improve yield and reduce cost.

Fig. 1A through 1F are schematic cross-sectional views illustrating structures formed at various stages of a method of manufacturing a package 10 according to some embodiments of the present disclosure. Referring to fig. 1A, a semiconductor wafer 100 is provided. In some embodiments, semiconductor wafer 100 may be divided into a plurality of dies 110. In some embodiments, the semiconductor wafer 100 may be a wafer made of a semiconductor material (e.g., a semiconductor material of group III-V of the periodic table). In some embodiments, the semiconductor wafer 100 may include: elemental semiconductor materials such as silicon or germanium; compound semiconductor materials such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide; or an alloy semiconductor material such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide or indium gallium phosphide. For example, the semiconductor wafer 100 may be a bulk silicon wafer. In some embodiments, die 110 are part of semiconductor wafer 100 and the sidewalls of each die 110 extend along cut line C-C. Each die 110 may include a semiconductor substrate 111, the semiconductor substrate 111 being a portion of the semiconductor substrate 101 of the semiconductor wafer 100. A plurality of contact pads 113 and a passivation layer 115 may be formed on the front side surface 101a of the semiconductor wafer 100. In fig. 1A, two dies 110 are shown to represent multiple dies 110 formed in semiconductor wafer 100, but more than two dies 110 may be formed in semiconductor wafer 100. Each of the dies 110 may include active components (e.g., transistors, etc.) formed in the semiconductor substrate 111 and, optionally, passive components (e.g., resistors, capacitors, inductors, etc.) formed in the semiconductor substrate 111. Each of the dies 110 may be a logic die, such as a Central Processing Unit (CPU) die, a Graphics Processing Unit (GPU) die, a Micro Control Unit (MCU) die, an input-output (I/O) die, a baseband (BB) die, or an Application Processor (AP) die. In some alternative embodiments, die 110 may be a memory die, such as a High Bandwidth Memory (HBM) die.

In some embodiments, contact pads 113 are formed on the active surface 111a of the semiconductor substrate 111 of each die 110. That is, each active surface 111a may correspond to a portion of the front side surface 101a of the semiconductor substrate 101 of the semiconductor wafer 100. In some embodiments, the contact pads 113 comprise aluminum pads, copper pads, or other suitable metal pads. As shown in fig. 1A, the passivation layer 115 extends over the front side surface 101A of the semiconductor wafer 100. In some embodiments, the passivation layer 115 is formed with an opening exposing the contact pad 113. In some embodiments, the passivation layer 115 may be a single layer structure or a multi-layer structure including a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a dielectric layer formed of other suitable dielectric materials, or a combination thereof. The opening of the passivation layer 115 may at least partially expose the contact pad 113.

Referring to fig. 1B, in some embodiments, the micro-trench 120 is formed on the back surface 111r of the semiconductor substrate 111 opposite to the active surface 111 a. In some embodiments, the micro-trench 120 is formed by removing a portion of the semiconductor substrate 111. In some embodiments, the micro-trenches 120 may be formed via an etching process. In some embodiments, the etching process comprises a dry etching process or a wet etching process. In some alternative embodiments, the micro-grooves 120 may be formed via a cutting process. In some embodiments, laser sawing or mechanical die sawing may be employed as the cutting process. In some embodiments, the micro-grooves 120 are formed via an etching process or a cutting process such that the micro-grooves 120 may be formed in a cost-effective manner. In some embodiments, where micro-grooves 120 are formed, multiple discontinuous patterns 117 may be formed simultaneously on the back surface 111r of die 110. For example, the discontinuous pattern 117 is located between two adjacent microchannels 120. In some embodiments, discontinuous pattern 117 is a semiconductor microstructure that remains on back surface 111r of die 110 after portions of semiconductor substrate 111 are removed to form microchannels 120. In some embodiments, the micro-trench 120 partially penetrates the semiconductor substrate 111, and portions of the semiconductor substrate 111 may be exposed at the sides and bottom of the micro-trench 120. That is, the depth D of the micro trench 120 (the distance from the level of the rear surface 111r to the bottom of the micro trench 120) may be less than the maximum thickness T111 of the semiconductor substrate 111. In some embodiments, the discontinuous pattern 117 is enclosed by a continuous loop pattern 119. In some embodiments, the discontinuous pattern 117 is located in the cooling region CR of the die 110 and the continuous ring pattern 119 is located in the peripheral region PR surrounding the cooling region CR. In some embodiments, the maximum thickness T111 may correspond to a thickness of the peripheral region PR (corresponding to the continuous ring pattern 119).

Referring to fig. 1B and 1C, a singulation process is performed on the semiconductor wafer 100 to separate the individual dies 110. For example, the semiconductor wafer 100 is cut through the entire thickness of the semiconductor wafer 100 along cutting lines C-C arranged between the individual dies 110. In some embodiments, the singulation process generally involves performing a wafer sawing process using mechanical die sawing and/or laser sawing.

Referring to fig. 1D, the die 110 is bonded to an interposer 200. In some embodiments, the interposer 200 includes a semiconductor substrate 210, through-semiconductor vias (TSVs) 220 formed in the semiconductor substrate 210, and an interconnect structure 230 formed on one side of the semiconductor substrate 210. Semiconductor substrate 210 may be made of the same material as semiconductor substrate 111 of die 110 and therefore will not be described in detail herein. In some embodiments, interposer 200 comprises a silicon wafer.

In some embodiments, an interconnect structure 230 is disposed on the semiconductor substrate 210, and the interconnect structure 230 includes a dielectric layer 231 and conductive traces 233 extending through the dielectric layer 231. For simplicity, the dielectric layer 231 is shown as a single dielectric layer and the conductive traces 233 are shown embedded in the dielectric layer 231. However, from the viewpoint of the manufacturing process, the dielectric layer 231 is composed of at least two dielectric layers. The conductive traces 233 may be sandwiched between two adjacent dielectric layers. Some of the conductive traces 233 may extend vertically through the dielectric layer 231 to establish electrical connections between different metallization levels of the interconnect structure 230. In some embodiments, the outermost dielectric layer 231 (when multiple dielectric layers are present in the dielectric layer 231) can be patterned to expose the underlying conductive traces 233. In some embodiments, the material of the dielectric layer 231 includes polyimide, epoxy, acrylic, phenolic, benzocyclobutene (BCB), Polybenzoxazole (PBO), or any other suitable polymer-based dielectric material. The dielectric layer 231 may be formed by a suitable fabrication technique, such as spin-on coating, Chemical Vapor Deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and the like. In some embodiments, the material of the conductive traces 233 includes aluminum, titanium, copper, nickel, tungsten, or alloys thereof. The conductive traces 233 can be formed by, for example, electroplating, deposition, and/or photolithography and etching. It should be noted that the number of dielectric layers 231 and the number of conductive traces 233 shown in fig. 1D are for illustration purposes only, and the present disclosure is not limited thereto. In some alternative embodiments, fewer or more layers of dielectric layers 231 or conductive traces 233 may be formed depending on the circuit design.

As illustrated in fig. 1D, semiconductor vias 220 are formed in the semiconductor substrate 210 to provide double-sided electrical connections. In some embodiments, one end of the through semiconductor via 220 is connected to the conductive trace 233 of the interconnect structure 230 and the other end is connected to the die 110 via the conductive terminal 300. In some embodiments, the material of the semiconductor via 220 includes one or more metals. For example, the metal material of the semiconductor via 220 includes copper, titanium, tungsten, aluminum, combinations thereof, and the like.

In some embodiments, the die 110 is bonded to the interposer 200 via conductive terminals 300. In some embodiments, the conductive terminal 300 is a micro bump disposed on the semiconductor via 220 and/or the contact pad 113. In some embodiments, the die 110 is provided with an active surface 111a (the surface on which the contact pads 113 are formed) that faces the interposer 200. That is, the back surface 111r on which the micro-trench 120 is formed faces away from the interposer 200. In some embodiments, the back surface 111r is referred to as an upper surface of the die 110.

Although fig. 1A-1D illustrate bonding die 110 to interposer 200 after back surface 111r has been patterned to form micro-trenches 120, the disclosure is not so limited. In some alternative embodiments, the die 110 may be placed on the interposer 200 before removing portions of the semiconductor substrate 111 to form the micro-trenches 120, as shown in fig. 1E. Subsequently, micro-grooves 120 may be formed on the back surface 111r to obtain the structure shown in fig. 1D. That is, in some embodiments, the micro-trenches 120 may be formed after the die 110 is bonded to the interposer 200.

Referring to fig. 1F, the structure shown in fig. 1D is placed on a substrate 400 to obtain a package 10. For example, the interposer 200 with the die 110 bonded on top may be connected to a substrate 400, such as a printed circuit board, motherboard, or the like. In some embodiments, interposer 200 is disposed between die 110 and substrate 400. As shown in fig. 1F, a plurality of connection terminals 500 are formed between the interposer 200 and the substrate 400 to establish electrical connections between the interposer 200 and the substrate 400. In some embodiments, the connection terminal 500 may be a controlled collapse chip connection (C4) bump. In some embodiments, the interposer 200 may be secured to the substrate 400 via a reflow process or the like. In some embodiments, package 10 may be referred to as a chip on wafer on substrate (CoWOS) package.

Fig. 2A and 2B are schematic top views of the die 110A and the die 110B, respectively. In some embodiments, die 110 of package 10 shown in fig. 1F may be replaced by die 110A or die 110B. Referring to fig. 2A, die 110A has a cooling region CR surrounded by a peripheral region PR. In some embodiments, the cooling region CR has a stripe-shaped micro-groove 120A formed therein. In some embodiments, the stripe-shaped microchannels 120A are parallel to one another. In some embodiments, the stripe-shaped micro-groove 120A is also parallel to one of the edges 110s of the die 110A. In some embodiments, the die 110A has a stripe pattern 117A between two adjacent stripe microgrooves 120A and a continuous ring pattern 119 surrounding the stripe microgrooves 120A and the stripe pattern 117A. In some embodiments, the stripe pattern 117A corresponds to the discontinuous pattern 117 shown in fig. 1F. In some embodiments, the stripe pattern 117A is located in the cooling region CR and the continuous loop pattern 119 is located in the peripheral region PR. In some embodiments, the stripe pattern 117A is connected to the continuous loop pattern 119. For example, in the top view of fig. 2A, the continuous loop pattern 119 may be divided into four

segments

1191, 1192, 1193, and 1194, which are joined together to form a square loop pattern. In some embodiments, stripe pattern 117A is connected to section 1192 and section 1194.

Referring to fig. 2B, die 110B has a cooling region CR surrounded by a peripheral region PR. In some embodiments, the mesh-like microchannels 120B are formed in the cooling region CR. In some embodiments, die 110B has micropillars 117B surrounded by a mesh microchannel 120B and a continuous ring pattern 119 surrounding mesh microchannel 120B and micropillars 117B. In some embodiments, the micropillars 117B correspond to the discontinuous pattern 117 shown in fig. 1F. In some embodiments, the micropillars 117B are located in the cooling region CR and the continuous ring pattern 119 is located in the peripheral region PR. In some embodiments, the micropillars 117B are arranged in an array and spaced apart from the continuous ring pattern 119. In some embodiments, the micropillars 117B are spaced apart from each other by a network of microchannels 120B. In some embodiments, the mesh-shaped micro-grooves 120B may be formed by micro-grooves 121 extending along a first direction and micro-grooves 122 extending along a second direction intersecting the first direction. In some embodiments, the first direction and the second direction may be perpendicular with respect to each other, but the invention is not limited thereto. In some embodiments, additional micro-trenches (not shown) extending along additional directions intersecting the first and second directions may also be included.

In some embodiments, the micropillars 117B may be formed in different shapes. Fig. 3A-3C are schematic top views of a microcolumn 117B1, a microcolumn 117B2, and a microcolumn 117B3, respectively, according to some embodiments of the present disclosure. Referring to fig. 3A, the microcolumns 117B1 may be a square pattern in a top view and may be referred to as square microcolumns. Referring to fig. 3B, the microcolumns 117B2 may be a diamond pattern when viewed from a top view, and may be referred to as diamond-shaped microcolumns. Referring to fig. 3C, the microcolumns 117B3 may be a triangular pattern in a top view and may be referred to as triangular microcolumns. It should be noted that the present invention is not limited thereto. In some alternative embodiments, the micropillars 117B of fig. 2B may be in a different form than the shape shown in fig. 3A-3C. In addition, although fig. 2B illustrates that the die 110B includes the micro-pillars 117B having the same shape, the present invention is not limited thereto. In some alternative embodiments, die 110B may include micropillars 117B having different shapes. For example, the combination of square micropillars 117B1 and triangular micropillars 117B3 may be seen simultaneously in die 110B.

Fig. 4A and 4B, fig. 5A and 5B, and fig. 6A and 6B are schematic cross-sectional views of die 1101, die 1102, and die 1103, respectively, according to some embodiments of the present disclosure. In some embodiments, die 110 of package 10 shown in fig. 1F may be replaced by die 1101, die 1102, or die 1103. The schematic cross-sectional views of fig. 4A, 5A, and 6A may be taken along one of line I-I of fig. 2A (extending across the plurality of stripe-shaped patterns 117A) or along one of line I-I and line III-III of fig. 2B (extending across the plurality of micropillars 117B). Similarly, the schematic cross-sectional views of fig. 4B, 5B, and 6B may be taken along line II-II of fig. 2A or along one of lines II-II and IV-IV of fig. 2B (along the bottom of the strip-shaped micro-groove 120A or the bottom of the mesh-shaped micro-groove 120B to avoid the discontinuous pattern 117).

Referring to fig. 4A and 4B, micro-trenches 1201 of die 1101 are formed by dry etching. In some embodiments, the micro grooves 1201 may be strip-shaped micro grooves 120A as shown in fig. 2A or mesh-shaped micro grooves 120B as shown in fig. 2B. In some embodiments, a patterned mask (not shown) is applied over the back surface 111r of the die 1101 followed by deep reactive-ion etching (DRIE) to form the micro-trenches 1201. In some embodiments, the patterned mask covers the peripheral region PR of the die 1101 and covers portions of the semiconductor substrate 111 that later form the discontinuous pattern 1171. At the same time, the patterned mask exposes portions of the cooling region CR, from which the semiconductor substrate 111 is removed to form the micro-trenches 1201. After the etching step, the patterned mask may be removed. In some embodiments, forming micro-trenches 1201 by dry etching may form micro-trenches 1201 with a substantially rectangular profile. That is, the bottom surface 1201b of the micro trench 1201 (the surface of the semiconductor substrate 111 exposed at the bottom of the micro trench 1201) and the sidewalls 1201s of the micro trench 1201 may be substantially straight. In some embodiments, sidewall 1201s may join bottom surface 1201b at a substantially right angle. In some embodiments, the sidewalls 1201s of the microchannels 1201 may be considered as the side edges of the discontinuous pattern 1171. That is, in some embodiments, the discontinuous pattern 1171 can have substantially straight side edges. In some embodiments, the depth D of the micro-groove 1201 (the distance between the level of the back surface 111r and the level of the bottom surface 1201 b) may be in the range from 5 μm to 700 μm. In some embodiments, the width W of the micro grooves 1201 (the distance between the sidewalls 1201s of one micro groove 1201 facing each other in a direction perpendicular to the extending direction of the micro groove 1201) may be in a range from 5 μm to 500 μm. In some embodiments, the pitch P of the discontinuous patterns 1171 (the distance between corresponding side edges (i.e., sidewalls 1201s) of immediately adjacent discontinuous patterns 1171) may be in the range from 6 μm to 1000 μm. In some embodiments, the length L of the micro-groove 1201 may be measured in terms of the distance between the sidewalls 1201s of the micro-groove 1201 that face each other along the direction of extension of the micro-groove 1201 (e.g., perpendicular to the direction of measurement of the width W). In some embodiments, along the same direction, the length L of micro-groove 1201 may be about 85% of the length of die 1101. For example, the length L of the micro-groove 1201 may be in the range from 5mm to 29 mm.

Referring to fig. 5A and 5B, the micro-trenches 1202 of the die 1102 are formed by a dicing process that employs mechanical die sawing. In some embodiments, the micro grooves 1202 may be strip-shaped micro grooves 120A as shown in fig. 2A or mesh-shaped micro grooves 120B as shown in fig. 2B. In some embodiments, the strip-shaped micro-trenches may be obtained by removing a portion of the semiconductor substrate 111 by mechanical die sawing. In some embodiments, the mesh-like micro-grooves may be obtained by forming micro-grooves (e.g., micro-grooves 121 of fig. 2B) along a first direction by mechanical die sawing and then forming micro-grooves (e.g., micro-grooves 122 of fig. 2B) along one or more directions that intersect the first direction. In some embodiments, when the micro-trench 1202 is formed using mechanical die sawing, the sidewalls 1202s of the micro-trench 1202 may be substantially straight, while the bottom surface 1202b may have a curved profile. In some embodiments, the angle at the junction between the side wall 1202s and the bottom surface 1202b of the micro-trench 1202 may be greater than 90 degrees. That is, in die 1102, the discontinuity pattern 1172 may be larger at the base (where the discontinuity pattern 1172 emerges from the semiconductor substrate 111) and narrow all the way to a substantially constant width toward the top (e.g., at the level of the back surface 111 r). In some embodiments, the range of depth D, pitch P, width W, and length L of the micro-trench 1202 may be similar to the range of depth D, pitch P, width W, and length L of the micro-trench 1201 shown in fig. 4A and 4B. As shown in fig. 5A and 5B, the depth D of the micro groove 1202 may be considered as the distance from the level of the rear surface 111r to the bottommost point of the micro groove 1202. In other words, the depth D of the micro-groove 120 is the maximum depth of the micro-groove 1202. The pitch P, width W, and length L may be considered similar to the pitch P, width W, and length L previously discussed with reference to fig. 4A and 4B. In some embodiments, the surface roughness (arithmetic average roughness) of the sidewalls 1202s of the micro-trench 1202 is in a range from 5 μm to 1000 μm.

Referring to fig. 6A and 6B, the micro-trench 1203 of the die 1103 is formed by a dicing process using laser sawing. In some embodiments, the micro grooves 1203 may be strip-shaped micro grooves 120A as shown in fig. 2A or mesh-shaped micro grooves 120B as shown in fig. 2B. In some embodiments, the strip-shaped micro-trenches may be obtained by removing a portion of the semiconductor substrate 111 by laser sawing. In some embodiments, the mesh-like micro-grooves may be obtained by laser sawing to form micro-grooves (e.g., the micro-grooves 121 of fig. 2B) along a first direction and then forming micro-grooves (e.g., the micro-grooves 122 of fig. 2B) along one or more directions that intersect the first direction. In some embodiments, when the micro-trench 1203 is formed using laser sawing, the sidewalls 1203s of the micro-trench 1203 may be sloped and the bottom surface 1203b may have a curved profile. In some embodiments, the angle at the junction between the sidewalls 1203s and the bottom surface 1203b of the micro-groove 1203 may be greater than 90 degrees. Further, the angle α between the level of the rear surface 111r and the sidewall 1203s of the micro groove 1203 may be in a range from 45 degrees to 90 degrees. That is, in die 1103, the discontinuity pattern 1173 may have a truncated solid (truncated) shape, i.e., larger at the base and narrowing toward the top (e.g., at the level of the back surface 111 r). In some embodiments, the range of depth D, pitch P, width W, and length L of the micro-trench 1203 may be similar to the depth D, pitch P, width W, and length L of the micro-trench 1201 shown in fig. 4A and 4B. In some embodiments, the surface roughness (arithmetic mean roughness) of the sidewalls 1203s of the micro-groove 1203 is in the range from 5 μm to 1000 μm.

Fig. 7A is a schematic top view of a die 1104 according to some embodiments of the present disclosure. Fig. 7B and 7C are schematic cross-sectional views of a die 1104 according to some embodiments of the present disclosure taken along lines I-I and II-II of fig. 7A, respectively. In some embodiments, micro-trenches 1204 are formed in die 1104 via a wet etch process. In some embodiments, a patterning auxiliary mask (not shown) may be disposed on the semiconductor substrate 111 prior to applying the etchant. Patterning the auxiliary mask may include openings that expose regions from which portions of the semiconductor substrate 111 are removed to form micro trenches 1204. In some embodiments, the shape of the micro-trenches may be determined depending on the material of the semiconductor substrate 111 and the composition of the etchant used. For example, when the semiconductor substrate 111 is made of crystalline silicon, the etchant may include KOH, and the micro-grooves 1204 may be formed by exposing a (111) surface (miller index) of silicon. That is, sidewalls 1204s of micro-groove 1204 may diagonally join each other at the bottom of micro-groove 1204, and bottom surface 1204b of micro-groove 1204 may correspond to the junction of the two sidewalls 1204 s. In some embodiments, the bottom surface 1204b has a substantially straight profile. Furthermore, the sidewalls 1204s of adjacent microchannels 1204 may be directly joined to one another, thereby providing the discontinuous pattern 1174 with a prismatic shape including a triangular base. That is, the discontinuous pattern 1174 may include a stripe-shaped pattern having a triangular prism shape (triangular prism shape) and extending parallel to each other. In some embodiments, facing sidewalls 1204s of two adjacent discontinuous patterns (also referred to as striped patterns) 1174 can constitute sidewalls 1204s of microchannels 1204 separating adjacent striped patterns 1174. In these embodiments, the width W of the micro-groove 1204 and the pitch P of the micro-groove 1204 may be consistent and measured as the distance between the tips R of adjacent stripe patterns 1174. However, the present invention is not limited thereto. Fig. 7D is a schematic cross-sectional view of a die 1105 in accordance with some alternative embodiments. The cross-sectional view of fig. 7D may be taken along a position corresponding to the line I-I of fig. 7A. In die 1105, micro trenches 1205 are also formed via wet etching, discontinuous pattern 1175 may be a trapezoidal prism (pitch prism), and pitch P may be greater than width W of micro trenches 1205.

Fig. 8A is a schematic cross-sectional view of a semiconductor device 15 according to some embodiments of the present disclosure. In some embodiments, semiconductor device 15 includes package 10 and cooling cover 600A stacked on package 10. In some embodiments, interposer 200, die 110, and cooling cap 600A are stacked in sequence on substrate 400 of package 10. In some embodiments, the cooling cover 600A faces the back surface 111r of the die 110. In some embodiments, cooling cover 600A extends over cooling zone CR and over a portion of peripheral zone PR or all of peripheral zone PR. In some embodiments, cooling cap 600A includes a housing 610 and a fluid port 620. In some embodiments, the housing 610 includes a floor panel (also referred to as a panel) 612, side panels (also referred to as panels) 614, and optionally a roof panel (also referred to as a panel) 616. In some embodiments, bottom panel 612, side panels 614, and top panel 616 may be assembled together to form housing 610. For example, side panels 614 may join bottom panel 612 and top panel 616. In some embodiments, fluid ports 620 include a fluid inlet port 620in and a fluid outlet port 620 out. In some embodiments, the cooling cover 600A is disposed with the backplane panel 612 facing the back surface 111r of the die 110. A circulation space CS may be formed between the backplane panel 612 and the rear surface 111r of the die 110, in which the micro-grooves 120 and the discontinuous pattern 117 are located. In some embodiments, fluid port 620 is connected to a fluid channel 630. In some embodiments, fluid ports 620 include a fluid inlet port 620in and a fluid outlet port 620 out. Similarly, the fluid channels 630 include a fluid inlet channel 630in and a fluid outlet channel 630 out. In some embodiments, the fluid channel 630 extends at least partially over the cooling region CR. As such, the fluid port 620 and the fluid channel 630 are in fluid communication with the circulation space CS and the micro channel 120. In some embodiments, fluid port 620 has an opening on side panel 614. For example, fluid port 620 is open in opposing side panels 614 (non-adjacent side panels 614 facing each other) and is connected to floor panel 612 by fluid channel 630. That is, the fluid inlet port 620in may be connected to the backplane panel 612 through a fluid inlet channel 630in, and the fluid outlet port 620out may be connected to the backplane panel 612 through a fluid outlet channel 630 out. In some embodiments, the fluid inlet port 620in may include: an interface duct 622in open in one of the side panels 614; and a connecting conduit 624in joining the interface conduit 622in with the fluid inlet channel 630 in. In some embodiments, the cross-sectional area of interface conduit 622in may be greater than the cross-sectional area of connecting conduit 624 in. In some embodiments, the interface conduit 622in and the connecting conduit 624in may be circular conduits. In some alternative embodiments, the interface conduit 622in and the connecting conduit 624in may be rectangular conduits. In some embodiments, the fluid outlet port 620out has a similar structure as the fluid inlet port 620 in. That is, the fluid outlet port 620out has an interface conduit 622out and a connecting conduit 624 out. In some embodiments, the interface conduits 622in, 622out and the connecting conduits 624in, 624out extend along a first direction. In some embodiments, the first direction is orthogonal to the side panel 614 in which the fluid port 620 opens. In some embodiments, the fluid channel 630 extends along a second direction that is different from the first direction. In some embodiments, the second direction is parallel to the plane of side panel 614. In some embodiments, the second direction is orthogonal to the backplane panel 612. For example, the second direction is perpendicular to the first direction.

In some embodiments, the backplane panel 612 includes a seal groove 640 that receives the seal ring 700. In some embodiments, a seal ring 700 is disposed between the cooling cap 600A and the die 110 to seal the circulation space CS. In some embodiments, the seal ring 700 is disposed on the continuous ring pattern 119 in the peripheral region PR. In some embodiments, fluid ports 620 and/or fluid channels 630 open in the area of backplane panel 612 enclosed by sealing channel 640. In some embodiments, the seal ring 700 may include an adhesive material and may secure the cooling cap 600A to the die 110. In some embodiments, sealing the circulation space CS via the sealing ring 700 facilitates placement and replacement of the cooling cover 600A.

It should be noted that although fig. 8A illustrates the application of the CoWoS package 10 to the cooling cover 600A, the present invention is not limited thereto. In alternative embodiments, other types of packages 10 may be assembled with cooling cover 600A. For example, in some alternative embodiments, an integrated fan-out (InFO) package may also be assembled with the cooling lid 600.

Fig. 8B is a schematic cross-sectional view of a semiconductor device 15 in use, according to some embodiments of the present disclosure. Fig. 8C is a schematic top view of semiconductor device 15 in use, according to some embodiments of the present disclosure. In some embodiments, fig. 8B and 8C illustrate the semiconductor device 15 with a cooling fluid CL (schematically represented by arrows) flowing through it. It should be noted that although in fig. 8C micro-grooves 120 are mesh-like micro-grooves (similar to die 110B of fig. 2B), the invention is not so limited. In some alternative embodiments, the semiconductor device 15 may include a die 110 having micro-grooves 120 and a discontinuous pattern 117 according to any of the above disclosed embodiments, for example, the micro-grooves 120 are stripe-shaped micro-grooves (similar to the die 110A shown in fig. 2A).

In some embodiments, the cooling fluid CL is a coolant. In some embodiments, the cooling fluid CL is a water-based coolant (water-based coolant). In some embodiments, an additive is added to the water to produce the cooling fluid CL. Examples of additives include surfactants (surfactants), corrosion inhibitors (corrosion inhibitors), biocides (biocides), antifreeze (antifreeze), and the like. In some embodiments, cooling fluid CL may enter cooling cap 600A from fluid inlet port 620 in. In some embodiments, the fluid inlet port 620in and the fluid outlet port 620out are connected to a cooling system (not shown), which may include a pump and a radiator joined by piping. Interface conduits 622in and 622out may be coupled to the conduit system of the cooling system. The pump may drive the cooling fluid CL to the cooling cap 600A via the fluid inlet port 620 in. For example, the cooling fluid CL may enter the semiconductor device 15 via the interface conduit 622 in. Thereafter, the cooling fluid CL travels through the connecting conduit 624in to the fluid inlet channel 630 in. Then, the cooling fluid CL passes through the fluid inlet channel 630in to reach the circulation space CS. In the circulation space CS, the cooling fluid CL may directly contact the cooling region CR of the die 110. For example, the cooling fluid CL may travel over the back surface 111r of the die 110. In some embodiments, the cooling fluid CL may enter one end of the microchannels 120, travel through the microchannels 120, and exit the microchannels 120 from the other end of the microchannels 120. For example, as shown in fig. 8C, when the micro-groove 120 is a mesh-like micro-groove formed by intersecting strip-shaped micro-grooves extending along two directions (as illustrated with respect to the die 110B shown in fig. 2B), the first flow direction D1 of the cooling fluid CL may be parallel to one of the extending directions of the strip-shaped micro-grooves. However, the cooling fluid may also flow in the second direction D2 in stripe-shaped micro grooves extending in the intersecting direction. In some embodiments, the fluid inlet channel 630in and the fluid outlet channel 630out may have an elongated shape (elongated shape) whose elongated direction is inclined with respect to the extending direction of the micro-groove 120. In some embodiments, the elongate direction of the fluid inlet channel 630in and the elongate direction of the fluid outlet channel 630out may be perpendicular to the elongate direction of at least some of the microchannels 120. In some embodiments, the fluid inlet channel 630in and the fluid outlet channel 630out may open across the plurality of discontinuous patterns 117 and the plurality of microchannels 120. In some embodiments, the cooling fluid CL may overfill the microchannels 120 and also cover the discontinuous pattern 117. After exiting the micro-trench 120, the cooling fluid CL may travel through the fluid outlet channel 630out and exit the semiconductor device 15 from the fluid outlet port 620 out.

In some embodiments, the temperature of the die 110 may increase during use. In some embodiments, the temperature of die 110 during use may be higher than the temperature of cooling cover 600A and the temperature of cooling fluid CL. In some embodiments, heat exchange may occur between the cooling fluid CL and the die 110 as the cooling fluid CL travels over the die 110. For example, the cooling fluid CL may warm from contact with the die 110 such that the temperature of the cooling fluid CL at the fluid outlet port 620out may be higher than the temperature of the cooling fluid CL at the fluid inlet port 620 in. In some embodiments, the cooling fluid CL may re-enter the piping of the cooling system via the fluid outlet port 620 out. In some embodiments, the cooling fluid CL may be cooled by a heat sink before being pumped back into the semiconductor device 15. In some embodiments, the cooling fluid CL is in direct contact with the semiconductor substrate 111. That is, heat exchange between the cooling fluid CL and the semiconductor substrate 111 can be achieved without using a Thermal Interface Material (TIM). In some embodiments, removing the thermal path through the thermal interface material may increase the thermal resistance of the semiconductor device 15.

Fig. 9A is a schematic cross-sectional view of a semiconductor device 25 according to some embodiments of the present disclosure. Semiconductor device 25 includes package 10 and cooling cover 600B. The semiconductor device 25 shown in fig. 9A is similar to the semiconductor device 15 shown in fig. 8A, and therefore, a detailed description thereof will not be given herein. In some embodiments, semiconductor device 25 further includes screws 810 and cooling lid 600B further includes vertical tubes 650 passing through top plate panel 616 and bottom plate panel 612. In some embodiments, vertical tubes 650 may be screw holes, and cooling cap 600B may be fastened to enclosure 10 via screws 810. In some embodiments, vertical conduit 650 is a closed channel that extends through housing 610 from top panel 616 to bottom panel 612. In some embodiments, the head of the screw 810 may be placed on the top plate panel 616, and the threads of the screw 810 may be fastened into the substrate 400 after being mated into the vertical pipe 650. In some embodiments, a threaded hole (not shown) may be formed in substrate 400 to receive a threaded end of screw 810. In some embodiments, the cooling cover 600B has a larger width than the interposer 200, and the vertical ducts 650 are disposed in the cooling cover 600B so as not to overlap the interposer 200. That is, the screws 810 may be disposed along the peripheral edge of the interposer 200.

Fig. 9B is a schematic cross-sectional view of a semiconductor device 35 according to some embodiments of the present disclosure. The semiconductor device 35 shown in fig. 9B is similar to the semiconductor device 15 shown in fig. 8A, and therefore, a detailed description thereof will not be given herein. In some embodiments, semiconductor device 35 further includes a clip 820. At semiconductor device 35, cooling cap 600A may be secured to package 10 by applying inward pressure. For example, the clamp 820 may be employed to press the cooling cover 600A and the package 10 together. In some embodiments, the upper arm 822 of the clamp 820 may be placed on the top plate panel 616 of the cooling cover 600A, and the lower arm 824 of the clamp 820 may be in contact with the bottom surface 400b of the substrate 400. The bottom surface 400b of the substrate 400 may be opposite to the top surface 400t on which the package 10 and the cooling cover 600A are stacked. In some embodiments, the upper arm 822 and the lower arm 824 of the clamp 820 may be connected by a clamp body 826. The combined action of the upper arm 822 and the lower arm 824 may securely fasten the cooling cover 600A and the package 10 together. In some embodiments, a plurality of clamps 820 may be applied to secure cooling cover 600A to package 10.

Fig. 9C is a schematic cross-sectional view of a semiconductor device 45 according to some embodiments of the present disclosure. The semiconductor device 45 shown in fig. 9C is similar to the semiconductor device 15 shown in fig. 8A, and therefore, a detailed description thereof will not be given herein. In some embodiments, semiconductor device 45 includes a package 12 and a cooling cover 600A stacked on package 12. The package 12 shown in fig. 9C is similar to the package 10 shown in fig. 8A, and therefore, a detailed description thereof will not be given herein. However, package 12 also includes a die 130 disposed on interposer 200 alongside die 110. In some embodiments, the die 130 includes a semiconductor substrate 131, the semiconductor substrate 131 having: a contact pad 133 formed on the active surface of the semiconductor substrate 131; and a passivation layer 135 covering the active surface and exposing portions of the contact pads 133. In some embodiments, the die 130 is disposed with the contact pads 133 facing the interposer 200. In some embodiments, the die 130 is connected to the interposer 200 via conductive terminals 310. The conductive terminals 310 may establish electrical connections between the contact pads 133 and the interposer 200. In some embodiments, the conductive terminals 310 are micro-bumps. As shown in fig. 9C, the rear surface 131r of the semiconductor substrate 131 faces the cooling cover 600A. In some embodiments, the back surface 131r of the semiconductor substrate 131 may be substantially flat. In some embodiments, semiconductor device 45 further includes a heat spreading layer 830 formed on back surface 131r of die 130. In some embodiments, heat spreading layer 830 may include a Thermal Interface Material (TIM). In some embodiments, the thermal interface material is an adhesive material. In some embodiments, the thermal interface material comprises a grease-based material (grease-based material), a phase change material (phase change material), a gel (gel), an adhesive, a polymer, a metallic material, or a combination thereof. In some embodiments, the thermal interface material comprises lead-tin based solder (PbSn), silver paste (Ag), gold, tin, gallium, indium, or other suitable thermally conductive material. The thermal interface material may be formed by deposition, lamination, printing, plating, or any other suitable technique, depending on the type of material used. In some embodiments, the thermal interface material is a gel-type material. In some embodiments, the thermal interface material is a film-type material (e.g., carbon nanotubes or graphite). In some embodiments, cooling cover 600A is bonded to die 130 of package 12 via heat spreading layer 830. In some embodiments, the die 130 may be disposed under a region of the cooling cover 600A other than the region surrounded by the sealing trench 640. In some embodiments, heat generated by die 130 during operation of semiconductor device 45 may be dissipated through heat dissipation layer 830.

Fig. 10A-10D are schematic perspective views of cooling

caps

600B, 600C, 600D, and 600E, respectively, according to some embodiments of the present disclosure. In some embodiments, the cooling cover 600A or the cooling cover 600B shown in fig. 8A, 9B, and 9C may be replaced by a

cooling cover

600C, 600D, or 600E. In the perspective views of fig. 10A-10D, the components of the corresponding cooling covers are shown, although the

panels

612, 614, 616 of the housing 610 may not necessarily be transparent. Referring to FIG. 10A, the cooling cap 600B of FIG. 9A is shown. As illustrated in fig. 10A, the fluid inlet port 620in and the fluid outlet port 620out may be open on the opposite side panel 614 of the housing 610. In some embodiments, the fluid inlet port 620in and the fluid outlet port 620out are connected to the fluid inlet channel 630in and the fluid outlet channel 630out, respectively. The sealing groove 640 formed in the backplane panel 612 may surround the fluid inlet channel 630in and the fluid outlet channel 630out and may pass under the fluid inlet port 620in and the fluid outlet port 620 out. The vertical tubes 650 may form channels that penetrate the cooling cover 600B from the bottom plate panel 612 to the top plate panel 616, and may be designed to receive screws (e.g., screws 810 shown in fig. 9A) to secure the cooling cover 600B to an underlying package (e.g., package 10 shown in fig. 9A).

Fig. 10B is a schematic perspective view of a cooling cap 600C according to some embodiments of the present disclosure. The cooling cover 600C shown in fig. 10B is similar to the cooling cover 600B shown in fig. 10A, and thus, a detailed description thereof will not be repeated herein. However, the cooling cover 600C may include: a plurality of fluid ports 620 having openings in side panels 614; and a plurality of fluid channels 630 having openings in the backplane panel 612. For example, cooling cover 600C includes: four

fluid ports

6201, 6202 having an opening in one of the side panels 614; and four

fluid ports

6203, 6204, having openings in side panel 614 opposite the side panel in which

fluid ports

6201 and 6202 are open. In some embodiments, the plurality of fluid ports 620 may be located at different levels. For example, two fluid ports 6201 and two fluid ports 6203 may be open at a first level closer to the bottom plate panel 612 than

fluid ports

6202 and 6204,

fluid ports

6202 and 6204 may be located at a second level closer to the top plate panel 616. In some embodiments, multiple fluid ports 620 may be connected to different fluid channels 630 depending on the level at which the fluid ports 620 are located and/or the side panel 614 with the fluid ports 620 open. For example, the cooling cap 600C may include three fluid channels 630, two of the three fluid channels 630 (6301 and 6303) reaching above a first level but not reaching a second level, and one of the three fluid channels 630 (6302) reaching above a second level. The three fluid channels 630 may all have openings in the floor panel 612 that are located within the area enclosed by the sealing groove 640. In some embodiments, the fluid channel 6302 up to the second level is located between two

fluid channels

6301, 6303 up to the second level and is connected to

fluid ports

6202, 6204 located at the second level. In some embodiments, the

fluid channels

6301, 6303 that do not reach the second level connect with

fluid ports

6201, 6203 located at the first level. That is, the fluid ports 6201 and fluid channels 6301 are located on one side of the fluid channel 6302 and are directly connected to each other, while the fluid ports 6203 and fluid channels 6303 are located on the opposite side of the fluid channel 6302 and are directly connected to each other. In some embodiments, the

fluid ports

6201, 6203 at the first level may be used as fluid inlet ports. On the other hand, the

fluid ports

6202, 6204 at the second level may be used as fluid outlet ports. However, the present invention is not limited thereto. In some alternative embodiments, the fluid inlet ports may be

fluid ports

6202, 6204 at the second level and the fluid outlet ports may be

fluid ports

6201, 6203 at the first level.

Fig. 10C is a schematic perspective view of a cooling cover 600D according to some embodiments of the present disclosure. The cooling cover 600D may include a plurality of

vertical ducts

650, 660 having openings at one end in the bottom panel 612 and openings at the other end in the top panel 616. In some embodiments, vertical tubes 650 serve as screw holes. In some embodiments, vertical conduits 650 are located in a region outside the enclosed region (enclosure) of sealed trench 640. In some embodiments, vertical pipe 660 is a fluid port and is located in the region enclosed by sealed trench 640. In some embodiments, vertical pipes 660 include pipes having different diameters. For example, the vertical pipe 660 may include a narrower fluid port 661 and a wider fluid port 662. In some embodiments, the narrower fluid ports 661 are disposed toward the corners (corner) of the region enclosed by the sealing groove 640, and the wider fluid ports 662 are disposed at the center of the region enclosed by the sealing groove 640. However, the present invention is not limited thereto. In some embodiments, the diameter of the narrower fluid port 661 is smaller than the diameter of the wider fluid port 662. In some embodiments, the wider fluid port 662 may serve as a fluid inlet port and the narrower fluid port 661 may serve as a fluid outlet port. However, the present invention is not limited thereto. In some embodiments, the fluid inlet port and fluid outlet port may have openings in the top panel 616 rather than in the side panels 614. In some embodiments, the fluid inlet port and the fluid outlet port may be directly connected to the backplane panel 612 without intervening fluid channels.

Fig. 10D is a schematic perspective view of a cooling cap 600E according to some embodiments of the present disclosure. The cooling cover 600E shown in FIG. 10D is similar to the cooling cover 600B shown in FIG. 10A and therefore will not be described in detail herein. However, the cooling cover 600E also includes vertical ducts 660, the vertical ducts 660 having openings in the top panel 616 of the housing 610. In some embodiments, vertical pipe 660 is located in the region enclosed by sealed trench 640. In some embodiments, fluid ports 620 may be connected to fluid channels 630, while vertical tubes 660 may be directly open in floor panel 612 without intervening fluid channels. In some embodiments, the fluid port 620 may serve as a fluid inlet port and the vertical pipe 660 may serve as a fluid outlet port. In some alternative embodiments, the fluid port 620 may function as a fluid outlet port and the vertical pipe 660 may function as a fluid inlet port.

Based on the above, a semiconductor device includes a package and a cooling cover disposed on the package. In some embodiments, the cooling cap allows a coolant flow to be in direct contact with the package, thereby eliminating the need for a thermal interface material. In some embodiments, the direct contact of the coolant with the package ensures efficient heat exchange, thereby providing a cooling effect to the package. In some embodiments, the cooling cover and the package form a circulation space through which a coolant flows. In addition, in the case where the micro grooves are formed on the rear surface of the die of the package, the coolant may flow through the micro grooves, thereby improving the heat dissipation efficiency of the semiconductor device.

In some embodiments of the present invention, a semiconductor device includes a package and a cooling lid. The package includes a first die having an active surface and a back surface opposite the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes a plurality of micro-grooves in the cooling region of the back surface. The cooling cap is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling zone and in communication with the plurality of microchannels. In some embodiments, the semiconductor device further comprises a seal ring located over the peripheral region, wherein the seal ring seals a space between the cooling cap and the plurality of microchannels. In some embodiments, the seal ring includes an adhesive material, and the cooling cover is adhered to the first die by the seal ring. In some embodiments, the cooling cover also includes a fluid inlet channel and a fluid outlet channel, the fluid inlet channel connected to the fluid inlet port and the fluid outlet channel connected to the fluid outlet port, the fluid inlet port and the fluid outlet port each extending along a first direction, and the fluid inlet channel and the fluid outlet channel each extending along a second direction perpendicular to the first direction. In some embodiments, the package further comprises: an interposer, wherein the first die is stacked on the interposer and the active surface is electrically connected to the interposer; and a substrate, wherein the interposer, the first die, and the cooling cover are stacked sequentially on the substrate. In some embodiments, the semiconductor device further comprises a screw, wherein the cooling cover is fixed to the package by the screw. In some embodiments, the semiconductor device further comprises a clamp, wherein the cooling cover is fixed to the package by the clamp. In some embodiments, the package further includes a second die located beside the first die, the semiconductor device further includes a heat spreading layer located between the second die and the cooling lid, and the heat spreading layer includes a Thermal Interface Material (TIM). In some embodiments, the bottom surface of the plurality of microchannels is curved. In some embodiments, the sidewalls of each micro-trench are sloped.

In some embodiments of the present invention, a semiconductor device includes a package and a cooling lid. The package includes a substrate, an interposer, and a die. The interposer is disposed over and electrically connected to the substrate. The die is disposed over and electrically connected to the interposer. The die includes a continuous ring pattern and a plurality of discontinuous patterns enclosed by the continuous ring pattern on an upper surface of the die opposite the interposer. The cooling cap is stacked on the die. The cooling cover includes a fluid inlet port and a fluid outlet port over the plurality of discontinuous patterns. In some embodiments, the semiconductor device further includes a seal ring between the cooling cap and the continuous ring pattern of the die. In some embodiments, the plurality of discontinuous patterns comprises a plurality of strip patterns parallel to each other, and the plurality of strip patterns is connected to the continuous loop pattern. In some embodiments, the plurality of discontinuous patterns are arranged in an array and spaced apart from the continuous loop pattern. In some embodiments, the plurality of discontinuous patterns are square patterns, triangular patterns, or diamond patterns.

In some embodiments of the present invention, a method of manufacturing a semiconductor device includes at least the following steps. A die is provided. The die has an active surface and a back surface opposite the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. Forming a plurality of micro-grooves in the cooling region of the back surface. Placing the die on an interposer such that the active surface of the die faces the interposer. Placing the interposer on a substrate. Attaching a cooling cover to the back surface of the die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling zone and in communication with the plurality of microchannels. In some embodiments, the plurality of microchannels are formed prior to placing the die on the interposer. In some embodiments, the plurality of microchannels are formed after the die is placed on the interposer. In some embodiments, the plurality of micro-trenches are formed by an etching process. In some embodiments, the plurality of microchannels are formed by a dicing process.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor device, comprising:

a package comprising a first die having an active surface and a back surface opposite the active surface, wherein the back surface has a cooling region and a peripheral region enclosing the cooling region, and the first die comprises a plurality of microchannels in the cooling region of the back surface; and

a cooling cap stacked on the first die, wherein the cooling cap includes a fluid inlet port and a fluid outlet port located over the cooling region and in communication with the plurality of microchannels.

2. The semiconductor device of claim 1, further comprising a seal ring located over the peripheral region, wherein the seal ring seals a space between the cooling cap and the plurality of microchannels.

3. The semiconductor device of claim 1, further comprising a screw, wherein the cooling cover is fixed to the package by the screw.

4. The semiconductor device of claim 1, further comprising a clamp, wherein the cooling cap is secured to the package by the clamp.

5. The semiconductor device of claim 1, wherein the package further comprises a second die located beside the first die, the semiconductor device further comprises a heat spreading layer located between the second die and the cooling lid, and the heat spreading layer comprises a Thermal Interface Material (TIM).

6. A semiconductor device, comprising:

a package, comprising:

a substrate;

an interposer disposed over and electrically connected to the substrate; and

a die disposed over and electrically connected to the interposer, wherein the die comprises a continuous ring pattern and a plurality of discontinuous patterns enclosed by the continuous ring pattern on an upper surface of the die opposite the interposer; and

a cooling cap stacked on the die, wherein the cooling cap includes a fluid inlet port and a fluid outlet port over the plurality of discontinuous patterns.

7. The semiconductor device of claim 6, wherein the plurality of discontinuous patterns comprises a plurality of stripe-shaped patterns parallel to each other, and the plurality of stripe-shaped patterns are connected to the continuous loop pattern.

8. The semiconductor device of claim 6, wherein the plurality of discontinuous patterns are arranged in an array and spaced apart from the continuous ring pattern.

9. A method of manufacturing a semiconductor device, comprising:

providing a die having an active surface and a back surface opposite the active surface, wherein the back surface has a cooling region and a peripheral region enclosing the cooling region;

forming a plurality of micro-grooves in the cooling region of the back surface;

placing the die on an interposer such that the active surface of the die faces the interposer;

placing the interposer on a substrate; and

attaching a cooling cover to the back surface of the die, wherein the cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and in communication with the plurality of microchannels.

10. The manufacturing method of a semiconductor device according to claim 9, wherein the plurality of micro trenches are formed by an etching process.