CN112436011B - Flash memory device and method of manufacturing the same - Google Patents

Flash memory device and method of manufacturing the same Download PDF

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CN112436011B
CN112436011B CN202011496589.0A CN202011496589A CN112436011B CN 112436011 B CN112436011 B CN 112436011B CN 202011496589 A CN202011496589 A CN 202011496589A CN 112436011 B CN112436011 B CN 112436011B
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gate
layer
substrate
flash memory
memory device
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CN112436011A (en
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杨道虹
周俊
孙鹏
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Wuhan Xinxin Integrated Circuit Co.,Ltd.
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

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Abstract

The invention provides a flash memory device and a manufacturing method thereof, wherein the material of a floating gate is replaced by at least one of amorphous silicon and monocrystalline silicon from the traditional doped polycrystalline silicon of 530 ℃ or 620 ℃, so that the problem of filling holes in the floating gate is solved, the area of a storage unit is further continuously shrunk possibly, the storage capacity can be improved after the area of the storage unit is shrunk, and the reliability of the device is ensured.

Description

Flash memory device and method of manufacturing the same
Technical Field
The present invention relates to the field of integrated circuit manufacturing technologies, and in particular, to a flash memory device and a method for manufacturing the same.
Background
Along with the development of the internet of things technology, the demand of an intelligent high-capacity low-power-consumption terminal on the miniaturization of a memory chip is more and more strong, and the existing code type flash memory of the 55 nm-65 nm technical node realizes the 50% improved storage capacity compared with the 90nm technical node through the area miniaturization of a storage unit, but the demand of the current size further miniaturization and the further improvement of the storage capacity of the memory chip is difficult to meet.
In addition, for the conventional planar code flash memory, the area shrinkage of the memory array region and the logic circuit at the periphery thereof is the only path for further realizing the memory chip shrinkage, wherein the device size design of the logic circuit region depends on many factors such as power supply voltage, memory cell operating voltage, chip operating frequency, power consumption, chip performance, reliability, etc., and the area design of each memory cell in the memory array region depends on the chip reliability, thereby limiting the shrinkage limit of the memory cell area manufactured by the manufacturing process of the conventional planar code flash memory.
Therefore, how to provide a flash memory device and a method for manufacturing the same, which can achieve a smaller memory cell area, and ensure the reliability of the flash memory device while obtaining a higher storage capacity, is one of the important problems to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a flash memory device and a manufacturing method thereof, which aim to realize smaller memory cell area and ensure the reliability of the flash memory device after the memory cell area is reduced while obtaining higher storage capacity.
To achieve the above object, the present invention provides a flash memory device comprising: a substrate and a plurality of memory cells formed on the substrate, each of the memory cells having an area of less than 0.04 μm2Each storage unit is provided with a grid stacking structure and a source region and a drain region which are positioned in the substrate at two sides of the grid stacking structure, and the grid stacking structure comprises a tunneling dielectric layer, a floating grid, an inter-grid dielectric layer and a control grid which are sequentially stacked on the substrate; wherein the material of the floating gate comprises at least one of amorphous silicon and monocrystalline silicon.
Optionally, the inter-gate dielectric layer includes a first silicon oxide layer, an intermediate dielectric layer, and a second silicon oxide layer, which are stacked in sequence, the dielectric constant k of the intermediate dielectric layer is higher than that of silicon oxide, and at least a part of the intermediate dielectric layer is a high-k dielectric with k greater than 8.
Optionally, each of the memory cells has an area of 0.018432 μm2～0.038088μm2。
Optionally, the memory cells of the flash memory device are arranged in rows and columns to form a memory array, a plurality of active regions with lengths extending along the column direction are formed in the substrate, the memory cells in the same column are formed in the same active region, the line width of each active region is 0.048 μm to 0.069 μm, and the distance between two adjacent active regions is 0.048 μm to 0.069 μm.
Optionally, the control gates of the memory cells in the same row are connected together to form a gate line with a length extending along the row direction, and the line width of the gate line is 0.096 μm to 0.138 μm.
Optionally, the drain region and the source region are formed in the active region on both sides of each gate line, and two adjacent rows of the memory cells share the same source region; and the space between two adjacent gate lines above the source region is 0.062-0.089 μm; and/or the distance between two adjacent gate lines above the drain region is 0.13-0.187 μm.
Optionally, the flash memory device further comprises a source line polysilicon layer filled in a gap between two adjacent gate lines above the source region, and an overlapping width of the source line polysilicon layer and the adjacent gate lines is 0.048 μm to 0.069 μm.
Optionally, the flash memory device further includes an interlayer dielectric layer formed on the substrate and filled between adjacent gate stack structures above the drain region, a contact hole having a bottom portion exposing a portion of the surface of the drain region is formed in the interlayer dielectric layer, a dielectric sidewall is formed on an inner sidewall of the contact hole, a contact plug is further filled in the contact hole, the bottom portion of the contact plug electrically contacts the drain region, and a dielectric constant of the dielectric sidewall is higher than 4.
Optionally, a line width of the contact hole in the column direction is 0.048 μm to 0.069 μm, and/or a distance between the contact hole and the gate line is 0.041 μm to 0.059 μm.
Based on the same inventive concept, the present invention also provides a method for manufacturing a flash memory device according to the present invention, comprising the steps of:
providing a substrate, forming a shallow trench isolation structure with the top surface higher than the top surface of the substrate in the substrate to define a plurality of active regions and define a trench for forming a floating gate;
depositing a tunneling dielectric layer and a floating gate layer on the substrate, wherein the deposited floating gate layer at least fills the groove;
flattening the top surface of the floating gate layer to the top surface of the shallow trench isolation structure, and etching the floating gate layer to form a floating gate;
depositing a first silicon oxide layer, an intermediate dielectric layer, a second silicon oxide layer and a control gate layer on the substrate in sequence, and etching the control gate layer, the second silicon oxide layer, the intermediate dielectric layer and the first silicon oxide layer in sequence to form a gate stack structure with a control gate, an inter-gate dielectric layer, a floating gate and a tunneling dielectric layer;
performing source-drain ion implantation on the active regions at two sides of the gate stack structure to form a sourceA region and a drain region to form an area of less than 0.04 μm2The memory cell of (1).
Compared with the prior art, the technical scheme of the invention at least has the following beneficial effects:
the floating gate is made of traditional doped polycrystalline silicon at 530 ℃ or 620 ℃ and is replaced by at least one of amorphous silicon and monocrystalline silicon, so that the problem that filling holes exist in the floating gate is solved, the area of the storage unit can be continuously reduced, the storage capacity can be improved after the area of the storage unit is reduced, and the reliability of the device is ensured.
Drawings
FIG. 1 is a schematic diagram of a top view of a device in a portion of a region of a flash memory cell in accordance with an embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of the device structure taken along line XX' in fig. 1.
Fig. 3 is a schematic cross-sectional view of the device structure taken along the YY' line in fig. 1.
Fig. 4 is a flow chart of a method of manufacturing a flash memory device according to an embodiment of the present invention.
Fig. 5 to 12 are schematic cross-sectional views of device structures in a method of manufacturing a flash memory device according to an embodiment of the present invention.
Detailed Description
The technical solution proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. As used herein, "and/or" means either or both.
Referring to fig. 1 to 3, an embodiment of the invention provides a flash memory device, including: the memory Cell structure includes a substrate 100 and a plurality of memory cells formed on the substrate 100, all of the memory cells being arranged in rows and columns to form a memory array. Wherein the area of a single memory Cell is equal to the total area of the chip occupied by the memory array divided by the number of memory cells, in this embodiment, each of the memory cellsThe area of the Cell is less than 0.04 μm2Further, it may be 0.018432 μm2～0.038088μm2。
In this embodiment, the substrate 100 may be any suitable semiconductor material known to those skilled in the art, such as silicon, germanium, silicon-on-insulator, and the like. The substrate 100 is formed with a shallow trench isolation structure 101, a material of the shallow trench isolation structure 101 includes silicon dioxide, a plurality of active regions 100a are defined in the substrate 100, a length of each active region 100a extends along a column direction of the memory array, the memory cells in the same column are formed in the same active region 100a, a line width D3 of each active region 100a is 0.048 μm to 0.069 μm, and a distance D4 between adjacent active regions 100a is 0.048 μm to 0.069 μm, that is, a bit line distance D1 of the memory array is D3+ D4 and is 0.096 μm to 0.138 μm.
In this embodiment, each memory Cell has a gate stack structure and a source region 100s and a drain region 100d in an active region 100a located on both sides of the gate stack structure. The gate stack structure includes a tunneling dielectric layer 102, a floating gate 103, an inter-gate dielectric layer 104 and a control gate 105 stacked on the substrate 100 in sequence. The tunneling dielectric layer 102 is used to isolate the floating gate 103 from the active region 100a, and may be made of silicon dioxide, etc., the floating gate 103 is used to store electrons, and the inter-gate dielectric layer 104 is used to isolate the control gate 105 from the floating gate 103, which requires a higher dielectric constant and a good insulating property.
It should be noted that, the advanced method for patterning floating gates in code type flash memories is developed from conventional photolithography to a self-aligned planarization process using silicon dioxide as a barrier layer, and one implementation manner of this process is to first fabricate a shallow trench isolation structure with a top higher than a top surface of a substrate in a substrate to define a trench for forming a floating gate, and then fill silicon in the trench and planarize the trench to the top of the shallow trench isolation structure. As the size of the active region is reduced, the requirement for the silicon filling capability required for forming the floating gate is higher and higher, and the prior art usually selects doped polysilicon at 530 ℃ or 620 ℃, but when the area of the memory cell is reduced to 0.04 μm2When the time reaches or below, continueThe use of conventional floating gate materials, either 530 degrees celsius doped polysilicon or 620 degrees celsius doped polysilicon, creates the problem of filling voids in the floating gate. Based on this, in this embodiment, the material of the floating gate 103 is changed to amorphous Silicon (or amorphous Silicon) and/or monocrystalline Silicon, and this material can solve the problem that after the size of the active region 100a is reduced, when the floating gate is formed by filling the floating gate material in the trench between the shallow trench isolation structures 101 and self-aligned planarization process, a filling cavity exists in the floating gate, thereby ensuring the reliability of the flash memory device after the area of the memory cell is reduced.
In addition, the conventional intergate dielectric layer is usually ONO (silicon oxide SiO)2Silicon nitride Si3N4Silicon oxide SiO2) Stacked structure, but scaled down to 0.04 μm in memory cell area2When the voltage is lower than the voltage, the traditional inter-gate dielectric layer is difficult to maintain higher control gate coupling coefficient, and the reliability of the flash memory device is influenced. Based on this, in the present embodiment, in order to maintain a high control gate coupling coefficient in a cell with a reduced size, an inter-gate dielectric layer (silicon nitride Si) in a conventional inter-gate dielectric layer is used3N4) In other words, in this embodiment, the inter-gate dielectric layer 104 includes a first silicon oxide layer (not shown), an intermediate dielectric layer (not shown) and a second silicon oxide layer (not shown) stacked in sequence, the dielectric constant k of the intermediate dielectric layer is higher than that of silicon dioxide as a whole, and at least a portion of the material is a high-k dielectric with a k greater than 8, and the high-k dielectric includes at least one of zirconium oxide, hafnium oxide, aluminum nitride, and the like. In addition, the first silicon oxide layer and the second silicon oxide layer may be grown by high temperature thermal oxidation HTO or atomic layer deposition ALD.
In the present embodiment, the control gates of the memory cells in the same row are connected together to form a gate line having a length extending in the row direction of the memory array, and the line width of the gate line (that is, the line width of the control gate 105) D7 is 0.096 μm to 0.138 μm. In addition, each gate line may serve as a word line of the memory array and perpendicularly intersect all of the active regions 100a of the memory array, and thus, a dimension D2 of one memory Cell in the column direction is 0.192 μm to 0.276 μm.
In this embodiment, a drain region 100d and a source region 100s are formed in the active region 100a on both sides of each gate line, and two adjacent rows of the memory cells share the same source region 100 s. And the spacing D8 between adjacent gate lines above the source region 100s (or between adjacent control gates 105 above the source region 100 s) is 0.062 μm to 0.089 μm, and the spacing D0 between adjacent gate lines above the drain region 100D (or between adjacent control gates 105 above the drain region 100D) is 0.13 μm to 0.187 μm. A gap between the adjacent gate lines above the source region 100s is filled with a source line polysilicon layer 108, and an overlapping width D9 of the source line polysilicon layer 108 and the gate line (i.e., an overlapping width of the source line polysilicon layer 108 and the control gate 105) is 0.048 μm to 0.069 μm. The top of the source line polysilicon layer 108 is in electrical contact with the source region 100 s.
In this embodiment, a gate sidewall 109 is further formed on the sidewall of the gate stack structure to protect the sidewalls of the control gate 105 and the floating gate 103, and to isolate the source line polysilicon layer 108 from the control gate 105 and the floating gate 103 respectively. The top surface of the gate stack structure is also covered with an etch protection layer 106. The gate sidewall 109 may be a single-layer structure or a composite structure formed by stacking multiple layers, for example, silicon oxide, silicon nitride, or the like, and the etching protection layer 106 may be silicon nitride, silicon oxynitride, silicon carbonitride, or the like.
In this embodiment, the flash memory device further includes an interlayer dielectric layer 110 formed on the substrate 100 and filled between adjacent gate lines above the drain region 100d, the interlayer dielectric layer 110 is made of, for example, silicon dioxide, a low-k dielectric having a dielectric constant k lower than that of silicon dioxide, and the like, a contact hole (not shown, refer to 110a in fig. 11) exposing a part of the surface of the drain region 100d is formed in the interlayer dielectric layer 110, a contact plug 107 is filled in the contact hole, and a bottom of the contact plug 107 is electrically contacted with the drain region 100 d. The material of the contact plug 107 includes at least one of metal (copper, tungsten, or the like), silicide, doped polysilicon, and the like.
Optionally, in this embodiment, in order to solve the problem of contact hole short circuit between memory cells caused by the filling of the cavity in the interlayer dielectric layer 110, and reduce the electric field strength borne by the interlayer dielectric layer 110 between the contact hole and the control gate 105 and the gate sidewall 109, a dielectric sidewall 111 is further formed on the sidewall of the contact plug 107, that is, the dielectric sidewall 111 is sandwiched between the contact plug 107 and the interlayer dielectric layer 110, the dielectric constant k of the dielectric sidewall 111 is higher than 4, the material of the dielectric sidewall 111 includes but is not limited to high-k dielectrics such as silicon nitride, aluminum nitride, hafnium oxide, zirconium oxide, and the like, and the growth mode of the dielectric sidewall is a high-step coverage process such as Low Pressure Chemical Vapor Deposition (LPCVD) or Atomic Layer Deposition (ALD). The material of the dielectric sidewall 111 is preferably a high-k dielectric with k greater than 8.
Optionally, a line width D5 of the contact hole in a column direction of the memory array is 0.048 μm to 0.069 μm, and/or a line width in a row direction of the memory array is 0.048 μm to 0.069 μm.
Optionally, the distance D6 between the contact holes and the gate lines covered by the source line polysilicon layer 108 is 0.041 μm to 0.059 μm.
The above numerical ranges are inclusive of the endpoints.
In summary, in the flash memory device of this embodiment, the material of the floating gate is replaced by at least one of amorphous silicon and monocrystalline silicon from the conventional doped polycrystalline silicon at 530 ℃ or 620 ℃, so as to solve the problem of having a filling hole in the floating gate, thereby enabling the area of the memory cell to be continuously scaled, and achieving a higher storage capacity after the area of the memory cell is scaled, and simultaneously ensuring the reliability of the device.
Further, in the flash memory device of the embodiment, at least part of the silicon nitride layer in the ONO intergate dielectric layer formed by the existing silicon oxide-silicon nitride-silicon oxide stack is replaced by the high-k dielectric with the dielectric constant k larger than 8, thereby being capable of realizing the flash memory device with the area size smaller than 0.04 μm2The control gate coupling coefficient of the memory cell is kept high, and the reliability of the device is further improved after the area of the memory cell is reduced.
In addition, in the embodiment, the active layer is formed byThe design of the line width and the space of the region, the line width and the space of the control gate, the line width of the contact plug and the space between the contact plug and the control gate can break through the limit of the existing memory cell area, and even the area of the memory cell can be reduced to 0.018432 μm2。
Based on the same inventive concept, referring to fig. 4, an embodiment of the present invention further provides a method for manufacturing a flash memory device, which can be used for manufacturing the flash memory device, and specifically includes the following steps:
s1, providing a substrate, forming a shallow trench isolation structure with the top surface higher than the top surface of the substrate in the substrate to define a plurality of active regions and define a first trench for forming a floating gate;
s2, depositing a tunneling dielectric layer and a floating gate layer on the substrate, wherein the deposited floating gate layer at least fills the trench;
s3, flattening the top surface of the floating gate layer to the top surface of the shallow trench isolation structure, and etching the floating gate layer to form a floating gate;
s4, depositing a first silicon oxide layer, an intermediate dielectric layer, a second silicon oxide layer and a control gate layer on the substrate in sequence, and etching the control gate layer, the second silicon oxide layer, the intermediate dielectric layer and the first silicon oxide layer in sequence to form a gate stack structure with a control gate, an inter-gate dielectric layer, a floating gate and a tunneling dielectric layer;
s5, performing source-drain ion implantation on the active regions on two sides of the gate stack structure to form a source region and a drain region, so as to form a region with an area smaller than 0.04 μm2The memory cell of (1);
and S6, forming a source line polycrystalline silicon layer, an interlayer dielectric layer and a contact plug with a dielectric side wall.
Referring to fig. 5, in the step S1, a substrate 100 is first provided, and the substrate 100 may be any suitable semiconductor substrate material known to those skilled in the art, such as silicon, silicon-on-insulator, germanium, silicon germanium, germanium-on-insulator, silicon germanium-on-insulator, gallium arsenide, indium phosphide, or an epitaxial wafer. Then, the substrate 100 is oxidized by a thermal oxidation process such as dry oxidation or wet oxidation to form a pad oxide (not shown). Next, a patterned mask layer (not shown) is formed on the pad oxide layer by a related process such as chemical vapor deposition, photolithography and etching, the patterned mask layer has a corresponding active region pattern, the material of the patterned mask layer is different from that of the pad oxide layer, and the patterned mask layer may include at least one of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, a low-k dielectric having a dielectric constant k lower than 3, a high-k dielectric having a dielectric constant k higher than 7, an organic coating layer, and photoresist. Then, the patterned mask layer is used as a mask to etch the pad oxide layer and the substrate 100 with a partial thickness, so as to form a plurality of shallow trenches (not shown) in the substrate 100, wherein an active region 100a is formed between adjacent shallow trenches, and the shallow trenches are used for forming a shallow trench isolation structure in the following to isolate adjacent memory cells. Then, a liner oxide layer (not shown) may be formed on the inner surface of each shallow trench through processes such as thermal oxidation and high density plasma chemical vapor deposition (HDP CVD), and an insulating isolation material may be deposited on the substrate 100, where the deposited insulating isolation material at least fills each shallow trench, and the deposited insulating isolation material is subjected to top planarization by using a Chemical Mechanical Polishing (CMP) process until the remaining thickness of the insulating isolation material reaches a desired thickness, and the insulating isolation material may include at least one of silicon oxide, tetraethoxysilane TEOS, silicon nitride, and silicon oxynitride. The substrate 100 may then be etched back to a desired depth, thereby forming shallow trench isolation structures 101 having a top surface higher than the top surface of the substrate 100, with trenches 101a between adjacent shallow trench isolation structures 101 defining locations for subsequent formation of floating gates 103.
Referring to fig. 6, in step S2, a tunnel dielectric layer 102a may be formed on the surface of the active region 100a and the shallow trench isolation structure 101 by a thermal furnace process, a rapid thermal oxidation process, an in-situ steam generation (ISSG) process, or a chemical vapor deposition process; then, a common deposition method in the art, such as chemical vapor deposition, may be used to deposit a floating gate layer including amorphous silicon and/or monocrystalline silicon on the surfaces of the tunneling dielectric layer 102a and the shallow trench isolation structure 101, and further planarize the floating gate layer 103a by a chemical mechanical planarization process until the top of the shallow trench isolation structure 101 is exposed, and the thickness of the remaining floating gate layer meets the requirement of the floating gate thickness.
Referring to fig. 6 and 7, in step S3, first, a hard mask layer is deposited on the floating gate layer 103a and the shallow trench isolation structure 101 and a photoresist layer is coated thereon; then, the floating gate layer 103a and the tunnel dielectric layer 102a are etched by photolithography and etching processes to expose a portion of the surface of the active region 100a, and the photoresist layer and the hard mask layer are removed to form the floating gate 103. Optionally, after the floating gate 103 is formed, the top of the shallow trench isolation structure 101 is further etched back by using a dry etching process until the height of the shallow trench isolation structure 101 reaches the final requirement.
Referring to fig. 8 and 9, in step S4, first, a first oxide layer (not shown), an intermediate dielectric layer (not shown) and a second oxide layer (not shown) are sequentially covered on the floating gate 103, the active region 100a and the surface of the shallow trench isolation structure 101 by a suitable process such as high temperature thermal oxidation, chemical vapor deposition, atomic layer deposition, etc. to form the inter-gate dielectric layer 104. The dielectric constant k of the middle dielectric layer is higher than that of silicon dioxide, at least part of the material is a high-k dielectric with k larger than 8, the high-k dielectric comprises at least one of zirconium oxide, hafnium oxide, aluminum nitride and the like, and the high-k dielectric can be formed through processes of chemical vapor deposition, atomic layer deposition and the like. Alternatively, the first silicon oxide layer and the second silicon oxide layer may be grown by high temperature thermal oxidation HTO or atomic layer deposition ALD. Then, a polysilicon layer and an etching protection layer 106 may be sequentially deposited on the inter-gate dielectric layer 104 by a deposition method commonly used in the art, such as chemical vapor deposition, and the material of the etching protection layer 106 may be, for example, silicon nitride, silicon oxynitride, silicon carbonitride, and the like. Next, the etching protection layer 106, the polysilicon layer, and the inter-gate dielectric layer 104 are patterned by photolithography and etching processes to form the control gate 105. The control gates 105 formed for the memory cells in the same row are connected together to form a gate line. At this time, a gate stack structure of each memory cell is formed, which includes a tunnel dielectric layer 102, a floating gate 103, an intergate dielectric layer 104, and a control gate 105 sequentially stacked on a substrate 100. Then, a sidewall material may be further deposited and sidewall etched through a conventional gate sidewall manufacturing process to form a gate sidewall 109 on the sidewall of the gate stack structure, where the material of the gate sidewall is, for example, silicon oxide, silicon nitride, or the like.
Referring to fig. 9, in step S5, the gate stack structure and the gate sidewall 109 are used as masks to perform source/drain ion implantation on the active region 100a at two sides of the gate stack structure to form a source region 100S and a drain region 100d, so as to obtain a source region 100S and a drain region 100d having an area smaller than 0.04 μm2A plurality of memory cells.
Referring to fig. 10 to 12, in step S6, first, a source line polysilicon layer 108 is filled in the gap between adjacent gate stack structures above the source region 100S by a conventional source line manufacturing process such as polysilicon deposition and chemical mechanical planarization, etching, etc., and the formed source line polysilicon layer 108 extends to a portion of the top surface of the gate stack structures to form corresponding overlap regions. Then, an interlayer dielectric layer 110 is deposited on the substrate 100 and the source line polysilicon layer 108, the interlayer dielectric layer 110 at least fills the gap between adjacent gate stack structures above the drain region 100d, and the deposition thickness of the interlayer dielectric layer 110 can bury both the gate stack structures and the source line polysilicon layer 108. Next, the interlayer dielectric layer 110 is etched to form a contact hole 110a exposing a portion of the surface of the drain region 100 d. Then, depositing a dielectric material with a dielectric constant k larger than 4, and etching the deposited dielectric material to form a dielectric sidewall spacer 111 on the sidewall of the contact hole 110 a. Thereafter, a conductive material such as a conductive metal is filled in the contact hole 110a by a conventional contact hole filling process to form a contact plug 107.
The desired bit lines and other structures may be subsequently formed by metal interconnect line processes and the like to complete the fabrication of the flash memory device.
The method for manufacturing the flash memory device of the embodiment can manufacture the memory unit with smaller size and ensure the reliability of the formed flash memory device.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art according to the above disclosure are within the scope of the present invention.

Claims (9)

1. A flash memory device is characterized by comprising a substrate and a plurality of memory cells formed on the substrate, wherein the area occupied by each memory cell on the surface of the substrate is less than 0.04 mu m2Each storage unit is provided with a grid stacking structure and a source region and a drain region which are positioned in the substrate at two sides of the grid stacking structure, and the grid stacking structure comprises a tunneling dielectric layer, a floating grid, an inter-grid dielectric layer and a control grid which are sequentially stacked on the substrate; the flash memory device comprises a floating gate, a plurality of gate lines and a plurality of source line polycrystalline silicon layers, wherein the floating gate is made of at least one of amorphous silicon and monocrystalline silicon, two adjacent rows of storage units share the same source region, control gates of the storage units in the same row are connected into a whole to form the gate lines with the lengths extending along the row direction, the flash memory device further comprises the source line polycrystalline silicon layers filled in gaps between two adjacent gate lines above the source region, the overlapping width of the source line polycrystalline silicon layers and the gate lines is 0.048-0.069 mu m, and the distance between two adjacent gate lines above the source region is smaller than that between two adjacent gate lines above the drain region.
2. The flash memory device according to claim 1, wherein the inter-gate dielectric layer comprises a first silicon oxide layer, an intermediate dielectric layer and a second silicon oxide layer which are stacked in sequence, the intermediate dielectric layer has a dielectric constant k higher than that of silicon dioxide as a whole, and at least a part of the material is a high-k dielectric with k greater than 8.
3. The flash memory device of claim 1, wherein each of the memory cells has an area of 0.018432 μm2～0.038088μm2。
4. The flash memory device according to claim 3, wherein the memory cells of the flash memory device are arranged in rows and columns to form a memory array, a plurality of active regions having lengths extending in the direction of the columns are formed in the substrate, the memory cells of the same column are formed in the same active region, each of the active regions has a line width of 0.048 μm to 0.069 μm, and a pitch between adjacent two of the active regions is 0.048 μm to 0.069 μm.
5. The flash memory device according to claim 4, wherein the gate line has a line width of 0.096 μm to 0.138 μm.
6. The flash memory device according to claim 5, wherein the drain region and the source region are respectively formed in the active region at both sides of each of the gate lines, and a pitch of two adjacent gate lines above the source region is 0.062 μm to 0.089 μm; and/or the distance between two adjacent gate lines above the drain region is 0.13-0.187 μm.
7. The flash memory device of claim 1, further comprising an interlayer dielectric layer formed on the substrate and filled between adjacent gate stack structures above the drain region, wherein a contact hole having a bottom exposing a portion of the surface of the drain region is formed in the interlayer dielectric layer, a dielectric sidewall is formed on an inner sidewall of the contact hole, a contact plug is further filled in the contact hole, a bottom of the contact plug electrically contacts the drain region, and a dielectric constant of the dielectric sidewall is higher than 4.
8. The flash memory device of claim 7, wherein a line width of the contact hole in a column direction is 0.048 μm to 0.069 μm, and/or a pitch of the contact hole and the gate line is 0.041 μm to 0.059 μm.
9. A method of manufacturing a flash memory device according to any one of claims 1 to 8, comprising the steps of:
providing a substrate, forming a shallow trench isolation structure with the top surface higher than the top surface of the substrate in the substrate to define a plurality of active regions and define a trench for forming a floating gate;
depositing a tunneling dielectric layer and a floating gate layer on the substrate, wherein the deposited floating gate layer at least fills the groove;
flattening the top surface of the floating gate layer to the top surface of the shallow trench isolation structure, and etching the floating gate layer to form a floating gate;
depositing a first silicon oxide layer, an intermediate dielectric layer, a second silicon oxide layer and a control gate layer on the substrate in sequence, and etching the control gate layer, the second silicon oxide layer, the intermediate dielectric layer and the first silicon oxide layer in sequence to form a gate stack structure with a control gate, an inter-gate dielectric layer, a floating gate and a tunneling dielectric layer;
performing source-drain ion implantation on the active regions at two sides of the gate stack structure to form a source region and a drain region, thereby forming a gate stack structure with an area less than 0.04 μm2The memory cell of (1).
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