CN114005749A

CN114005749A - Manufacturing method of groove and manufacturing method of memory device

Info

Publication number: CN114005749A
Application number: CN202111283409.5A
Authority: CN
Inventors: 谢岩; 邹浩
Original assignee: Wuhan Xinxin Semiconductor Manufacturing Co Ltd
Current assignee: Wuhan Xinxin Semiconductor Manufacturing Co Ltd
Priority date: 2021-11-01
Filing date: 2021-11-01
Publication date: 2022-02-01

Abstract

The invention provides a manufacturing method of a groove and a manufacturing method of a memory device, comprising the following steps: providing a front-end device; forming an ODL layer; baking the ODL layer to make the ODL layer more compact and weaken the lateral etching rate; the opening of the corresponding groove formed in the ODL layer is not expanded outwards and is not etched laterally, and the key size of the opening of the corresponding groove is effectively controlled. The etching layer by layer is to etch the patterned photoresist layer, the SHB layer and the ODL layer, the etching of the corresponding opening of the groove is carried out by adopting a multilayer film layer structure, the pattern and the size of the opening are sequentially transmitted, the resolution and the fidelity of the pattern of the opening are improved, the accurate control of the key size of the pattern of the opening is realized, the key size of the groove can be accurately controlled, and the key size of the groove can be further reduced. The key size of the groove is small, the length of the groove of the storage device is correspondingly reduced, a small-size semi-floating gate buried gate groove with effective vertical morphology is formed, the electrical performance of the semi-floating gate device is improved, and the yield of the storage device wafer is improved.

Description

Manufacturing method of groove and manufacturing method of memory device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a groove and a manufacturing method of a memory device.

Background

Semiconductor memories are used in various electronic fields. Among other things, nonvolatile memory can hold data for long periods of time in the event of a power outage. A semi-floating gate transistor is a mainstream nonvolatile memory. The semi-floating gate Transistor replaces the traditional silicon oxide erasing window by using the quantum Tunneling Effect of a Tunneling Field-Effect Transistor (TFET) and a pn junction diode, realizes the charging and discharging of the floating gate, can greatly reduce the working voltage of the Transistor, improves the working speed of the Transistor, realizes the faster data writing and erasing under low voltage, and is convenient to meet the requirement of low power consumption of a chip.

The semi-floating gate transistor has good storage performance: the method has the advantages of high speed, small area, no large capacitance and low power consumption, and the key process of the method needs to form a small-sized vertical buried gate channel (U-shaped channel) on a silicon substrate and then fill polysilicon to form a semi-floating gate structure. The existing semi-floating gate transistor manufacturing process makes the Critical Dimension (CD) of the U-shaped groove further smaller and more difficult. The minimum size of the semi-floating gate structure is the largest factor that restricts the working efficiency of the device and the area of the transistor, and the Critical Dimension (CD) of the U-shaped channel of the semi-floating gate transistor determines the length of the channel of the semi-floating gate transistor, so that the manufacture of the U-shaped channel with smaller Critical Dimension (CD) is a critical problem that needs to be solved urgently in the industry.

Disclosure of Invention

The invention provides a manufacturing method of a groove and a manufacturing method of a memory device. The method and the device realize the accurate control of the critical dimension of the corresponding opening pattern of the groove, thereby accurately controlling the critical dimension of the groove and further reducing the critical dimension of the groove.

The invention provides a manufacturing method of a groove, which comprises the following steps:

providing a front-end device, wherein the front-end device comprises a substrate and a liner oxide layer and a nitride layer which are positioned on the substrate; forming shallow trench isolations distributed at intervals in the front-end device; the region between the adjacent shallow trench isolations is defined as an active region;

removing the nitride layer to form a groove between the adjacent shallow trench isolations;

forming an ODL layer, filling the groove and covering the shallow trench isolation, and baking the ODL layer;

forming an SHB layer and a light resistance layer which sequentially cover the ODL layer;

etching layer by layer to pattern the photoresist layer, the SHB layer and the ODL layer, and sequentially transferring the opening patterns of the corresponding grooves from the photoresist layer to the ODL layer;

and etching the liner oxide layer exposed by the opening in the active region and the substrate with partial thickness by taking the patterned ODL layer as a mask to form the groove.

Further, baking the ODL layer includes: the baking temperature is 300-400 ℃, and the baking time is as follows: 60-120 minutes.

Further, after the etching to pattern the ODL layer and before the forming the trench, the method further includes:

and performing wet etching, removing the exposed parts of the shallow trench isolations, which are positioned on the two sides of the groove and positioned in the opening of the ODL layer, and enlarging the groove.

Further, etching to pattern the ODL layer includes: the etching pressure is less than 10 mTorr; power: 300W-500W; bias voltage: 100V-200V; the etching gas comprises argon and oxygen, the flow rate of the etching gas is 1000 sccm-2000 sccm, and the flow ratio of the argon to the oxygen is 5: 1-10: 1.

Further, the manufacturing method further comprises: a BARC layer is formed between the SHB layer and the photoresist layer.

Further, etching layer by layer to pattern the photoresist layer, the SHB layer, and the ODL layer, includes:

patterning the light resistance layer by adopting a photoetching process, wherein the patterned light resistance layer is provided with a first opening corresponding to the groove;

etching the BARC layer by using the patterned photoresist layer as a mask, and transferring the pattern of the photoresist layer to the BARC layer;

removing the photoresistance layer, etching the SHB layer by taking the patterned BARC layer as a mask, and transferring the pattern of the BARC layer to the SHB layer;

removing the BARC layer, etching the ODL layer by taking the patterned SHB layer as a mask, transferring the pattern of the SHB layer to the ODL layer, and forming a second opening in the ODL layer; the critical dimension of the second opening remains the critical dimension of the first opening.

Further, an X direction and a Y direction which are perpendicular to each other are defined in a plane parallel to the substrate, a direction perpendicular to the plane of the substrate is defined as a Z direction, and the shallow trench isolations and the active regions are alternately arranged along the X direction.

Further, after forming the trench, the method further includes:

implanting ions into the side walls of the groove at the two ends in the X direction for doping, so that the substrate on the side walls at the two ends in the X direction is amorphized;

and oxidizing and removing the substrate after amorphization, so that the side walls of the finally formed groove at two ends in the X direction are defined by the adjacent shallow groove isolation.

The invention also provides a manufacturing method of the memory device, which comprises the steps of manufacturing the groove by adopting the method and manufacturing the semi-floating gate transistor by utilizing the groove.

Further, after the groove is formed, a gate insulating layer is formed, the gate insulating layer covers the surface of the groove and the upper surface of the substrate, and the gate insulating layer is etched to form a contact window exposing the substrate.

Further, the manufacturing method further comprises: and after the gate insulating layer and the contact window are formed, continuously forming a semi-floating gate, an inter-gate dielectric layer and a control gate to form a gate stack.

Furthermore, a side wall is formed on the side wall of the gate stack, ion implantation is performed by taking the side wall as a mask to form a source region and a drain region, the contact window is close to one side of the drain region, and the gate insulating layer is not arranged between the substrate and the semi-floating gate.

Further, adjacent gate stacks share a source region.

The invention has the following beneficial effects:

the invention provides a manufacturing method of a groove, which comprises the following steps: providing a front-end device; forming an ODL layer; baking the ODL layer; etching layer by layer to pattern the photoresist layer, the SHB layer and the ODL layer, and sequentially transferring the opening patterns of the corresponding grooves from the photoresist layer to the ODL layer; and etching the liner oxide layer exposed by the opening in the active region and the substrate with partial thickness by taking the patterned ODL layer as a mask to form the groove.

And baking the ODL layer to make the ODL layer more compact and have better plasma resistance, so that the lateral etching rate of the ODL layer is reduced, the ODL layer is etched to be patterned, the opening of the corresponding groove formed in the ODL layer is not expanded outwards and is not etched laterally, and the key size of the opening of the corresponding groove is effectively controlled. The photoresist layer, the SHB layer and the ODL layer are etched layer by layer to be patterned, the etching of the corresponding opening of the groove is carried out by adopting a multi-layer film layer structure, the pattern and the size of the opening are sequentially transmitted, the resolution and the fidelity of the opening pattern are improved, the accurate control of the critical dimension of the opening pattern is realized, the critical dimension of the groove can be accurately controlled, and the critical dimension of the groove can be further reduced. The critical dimension of the trench is made small, and accordingly the channel length of the memory device is reduced, so that the effective current and the read window of the memory device can be increased. The key size of the groove is small, and a small-size semi-floating gate buried gate channel with effective vertical appearance is formed. The function of the semi-floating gate device is improved, and the yield of the wafer of the memory device is improved.

Drawings

Fig. 1 is a flowchart of a method for forming a trench according to the present embodiment.

Fig. 2 is a top view of the memory device of the present embodiment after the first trench and the second trench are formed.

Fig. 3 to 12b are sectional views of the steps of the method of manufacturing the memory device of the present embodiment.

Fig. 13 is a cross-sectional view of a gate insulating layer formed in the method of manufacturing a memory device according to the present embodiment.

Fig. 14 is a cross-sectional view of the semi-floating gate material layer after being formed by the method for manufacturing a memory device of the present embodiment.

Fig. 15 is a cross-sectional view of a control gate material layer formed by the method of manufacturing a memory device of the present embodiment.

Fig. 16 is a cross-sectional view of the memory device of the present embodiment after forming the individual separated semi-floating gate transistors.

Fig. 17 is a cross-sectional view of the source and drain formed by the method of manufacturing a memory device of the present embodiment.

Fig. 18 is a schematic view after a gate insulating layer is formed in another method of manufacturing a memory device of the present embodiment;

fig. 19 is a schematic view after forming a floating gate material layer in another method of fabricating a memory device of the present embodiment;

fig. 20 is a cross-sectional view of another method of fabricating a memory device of this embodiment after forming a control gate material layer.

Fig. 21 is a cross-sectional view of the source and drain formed by another method of fabricating a memory device of this embodiment.

Description of reference numerals:

10-a semi-floating gate transistor; 100-a substrate; 100 a-a first contact window; 100 b-a second contact window; 101-common source; 103-a first drain; 104-a second drain; 105-doped region; 111-a gate insulating layer;

120-a first floating gate; 121-a layer of floating gate material; 130-an inter-gate dielectric layer; 131-a silicon oxide layer; 132-a silicon nitride layer; 140-a first control gate; 141-a control gate material layer;

152-pad oxide layer; 153-a nitride layer; 154-ODL layer; 155-SHB layer; 156-BARC layer; 157-a photoresist layer;

30-a first trench; 40-a second trench; 50-a groove; 300-a first gate stack; 400-a second gate stack; AA-active region; STI-shallow trench isolation; m-mask layer; SP-side wall; i-common source region; II, a first drain region; III-a second drain region;

a V-source region; IV-a drain region; 100 c-contact window; 160-intergate dielectric layer; 161-a silicon oxide layer; 162-a silicon nitride layer; 163-source; 164-a drain; 170-floating gate material layer; 181-a control gate material layer; 180-control gate.

Detailed Description

For the sake of reference and clarity, the descriptions, abbreviations or abbreviations of the technical terms used hereinafter are summarized as follows:

BARC: bottom Anti Reflection Coating;

ODL: organic Dielectric Layer;

SHB: Si-O-based Hard Mask, a silicon-based Hard Mask interlayer structure layer.

As described in the background, it is difficult to further reduce the Critical Dimension (CD) of the U-shaped trench in the conventional semi-floating gate transistor fabrication process. The main reason for restricting the reduction of the trench (U-shaped trench) is: the mask layer ODL layer for forming the trench is used due to its excellent step coverage, but its loose property causes it to be easily etched laterally, thereby causing the CD of the trench to be enlarged.

Specifically, the substrate is etched by using the ODL layer as a mask to form a trench, and when the ODL layer is etched longitudinally in a depth direction in a process of opening the ODL layer (etching the ODL layer to pattern the ODL layer) to form a mask opening corresponding to the trench, the ODL layer is also etched transversely (laterally) in a plane parallel to the substrate, that is, the size of the opening in a top view direction is increased, and the critical size of the trench formed by using the hard mask opening is also increased, so that the critical size (CD) of the U-shaped trench cannot be further decreased. The critical dimension of the trench becomes larger, the channel of the semi-floating gate transistor becomes longer, the longer the channel, the smaller the channel current, and the electrical performance of the semi-floating gate transistor becomes worse, which are all undesirable.

The method for fabricating the memory device of the present invention is further described in detail with reference to the accompanying drawings and the embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be understood that the drawings in the specification are in simplified form and are not to be taken in a precise scale, for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

It is noted that the terms "first," "second," and the like, hereinafter are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other sequences than described or illustrated herein. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the structure in the figures is inverted or otherwise oriented (e.g., rotated), the exemplary term "at … …" can also include "at … …" and other orientational relationships.

The present embodiment provides a method for manufacturing a trench, as shown in fig. 1, including the following steps:

s1, providing a front-end device, wherein the front-end device comprises a substrate and a liner oxide layer and a nitride layer which are positioned on the substrate; forming shallow trench isolations distributed at intervals in the front-end device; the region between the adjacent shallow trench isolations is defined as an active region;

s2, removing the nitride layer to form a groove between the adjacent shallow trench isolations;

s3, forming an ODL layer, filling the groove and covering the shallow trench isolation, and baking the ODL layer;

s4, forming an SHB layer and a light resistance layer which sequentially cover the ODL layer;

s5, etching layer by layer to pattern the light resistance layer, the SHB layer and the ODL layer, and sequentially transferring the opening patterns of the corresponding grooves from the light resistance layer to the ODL layer;

and S6, etching the pad oxide layer exposed by the opening in the active region and the substrate with partial thickness by taking the patterned ODL layer as a mask to form the groove.

The method for manufacturing the memory device according to the present embodiment will be described in detail with reference to fig. 2 to 12b, and the method for manufacturing the trench in the memory device will be described with emphasis on.

Fig. 2 is a top view of a memory device of the present embodiment forming a first trench and a second trench, and fig. 3 to 10, 11a and 12a are cross-sectional views along X1X2 of fig. 2 corresponding to each step; fig. 11b and 12b are cross-sectional views along Y1Y2 of fig. 2 corresponding to each step.

As shown in fig. 2 and 3, a front-end device is provided, which includes a substrate 100 and a pad oxide layer 152 and a nitride layer 153 on the substrate; forming Shallow Trench Isolation (STI) distributed at intervals in the front-end device; and the area between the adjacent shallow trench isolation STI is defined as an active area AA. The X direction and the Y direction perpendicular to each other are defined in a plane parallel to the substrate 100, and the Z direction (memory device thickness direction) is defined in a direction perpendicular to the plane of the substrate 200. Illustratively, the shallow trench isolation STI and the active area AA are alternately arranged in the X direction.

Specifically, a substrate 100 is provided, a pad oxide layer 152 and a nitride layer 153 are sequentially formed on the substrate 100, and the pad oxide layer 152 relieves stress on the substrate 100 caused by the nitride layer 153 formed subsequently. The liner oxide layer 152 of the present embodiment is made of, for example, silicon oxide, and can be manufactured by a furnace oxidation process, and the thickness of the liner oxide layer 152 is, for example, the

The material of the nitride layer 153 is, for example, silicon nitride, and the thickness of the nitride layer 153 can be

The nitride layer 153 may be formed using a Chemical Vapor Deposition (CVD) or Low Pressure Chemical Vapor Deposition (LPCVD) process. The substrate 100 in this embodiment is, for example, single crystal silicon, polycrystalline silicon, or silicon-on-insulator.

Etching nitride layer 153, pad oxide layer 152 and partial thickness of substrate 10And 0, forming an isolation groove, and filling an isolation layer in the isolation groove to form Shallow Trench Isolation (STI). Along the X direction, the region between adjacent shallow trench isolation STI is an active area AA. Specifically, the isolation layer fills the isolation trench and covers the upper surface of the nitride layer 153, and a Chemical Mechanical Polishing (CMP) process is performed to perform a top surface planarization process to remove the isolation layer on the upper surface of the nitride layer 153. The isolation layer may be at least one of silicon oxide or Tetraethylorthosilicate (TEOS). The silicon oxide may be, for example, thermally decomposed SiO₂. The isolation layer may be formed using a Plasma Enhanced Chemical Vapor Deposition (PECVD) or a High Aspect Ratio Process (HARP) Process.

As shown in fig. 4, after the shallow trench isolation STI is formed, the nitride layer 153 is removed. Specifically, the nitride layer 153 may be removed by wet etching, such as phosphoric acid, and after the nitride layer 153 is removed, a groove P is formed between adjacent STI regions.

As shown in fig. 5, an ODL layer 154 is applied, the ODL layer 154 filling the recess P above the pad oxide layer 152 and covering the shallow trench isolation STI. The ODL layer may be a Carbon coating, which is a polymer with high Carbon content (Spin-On-Carbon, SOC).

As shown in fig. 6, the ODL layer is baked, and the process parameters include: the baking temperature is 300-400 ℃, and the baking time is as follows: 60-120 minutes. And baking the ODL layer to make the ODL layer more compact and have better plasma resistance, so that the lateral etching rate of the ODL layer is reduced, and when the ODL layer is patterned by subsequent etching, the opening corresponding to the groove formed in the ODL layer is not expanded outwards and is not etched laterally, so that the key size of the opening corresponding to the groove is effectively controlled.

As shown in fig. 7, SHB layer 155 is formed, SHB layer 155 covering ODL layer 154; a photoresist layer 157 is formed, the photoresist layer 157 covering the SHB layer 155. The ODL layer 154 and the SHB layer 155 constitute a mask layer M, which is a hard mask. Optionally, a BARC layer 156 may also be formed between SHB layer 155 and photoresist layer 157. The ODL layer 154, the SHB layer 155, the BARC layer 156, and the photoresist layer 157 are sequentially stacked. The thickness h of the ODL layer 154 is, for example

The thickness of the SHB layer 155 is, for example

The BARC layer 156 has a thickness of

The thickness of the photoresist layer 157 is, for example, as follows

Etching layer by layer to pattern the photoresist layer, the SHB layer and the ODL layer, and sequentially transferring an opening pattern corresponding to a groove from the photoresist layer to the ODL layer, specifically comprising:

step S51, patterning the photoresist layer 157 by using a photolithography process, where the patterned photoresist layer 157 has a first opening K1 corresponding to the trench, the first opening K1 is located right above the pad oxide layer 152 between adjacent shallow trench isolations in the active region AA, and the first openings K1 are distributed at intervals along the X direction.

In step S52, the BARC layer 156 is etched using the patterned photoresist layer 157 as a mask to transfer the pattern of the photoresist layer 157 to the BARC layer 156. Illustratively, the BARC layer 156 is etched using a dry etch.

Step S53, removing the photoresist layer 157, etching the SHB layer 155 with the patterned BARC layer 156 as a mask, transferring the pattern of BARC layer 156 onto the SHB layer 155, and removing all of the SHB layer 155 directly under the first opening K1. Illustratively, the SHB layer 155 is etched using a dry etch.

Step S54, as shown in fig. 8 and 9, the BARC layer 156 is removed, the ODL layer 154 is etched using the patterned SHB layer 155 as a mask, the pattern of the SHB layer 155 is transferred to the ODL layer 154, the ODL layer 154 exposed by the opening in the SHB layer 155 is completely removed, and the ODL layer 154 in the recess P is also removed. A second opening K2 is formed in ODL layer 154. ODL layer 154 is etched, illustratively, using a dry etch to form second opening K2.

The process parameters for etching to pattern the ODL layer 154 include: the etching pressure is less than 10 mTorr; power: 300W-500W; bias voltage: 100V-200V; the etching gas comprises argon and oxygen, the flow rate of the etching gas is 1000 sccm-2000 sccm, and the flow ratio of the argon to the oxygen is 5: 1-10: 1.

In the embodiment, the ODL layer is more compact by adopting the baking process, has better plasma resistance, obviously weakens the lateral etching rate, effectively controls the Critical Dimension (CD) of the opening in the ODL layer not to expand, and simultaneously adopts large-flow argon (Ar) and small-flow oxygen (O)₂) The combination of (a) and (b) can provide better control over opening Critical Dimension (CD) expansion, resulting in smaller line width trenches.

This embodiment enables sequential pattern transfer, with the critical dimension of the second opening K2 in the open area of the patterned ODL layer 154 remaining as the critical dimension of the first opening K1 in the open area of the patterned photoresist layer 157.

In this embodiment, a four-layer film structure formed by stacking the ODL layer 154, the SHB layer 155, the BARC layer 156, and the photoresist layer 157 is used to etch the corresponding opening of the trench, and the four-layer film structure sequentially transfers the pattern and the dimension, thereby improving the resolution and the fidelity of the pattern, and realizing the precise control of the critical dimension of the opening pattern, so as to precisely control the critical dimension of the trench.

Then, forming a groove; the trench may be gradually formed through wet etching and dry etching.

As shown in fig. 9 and 10, a wet etching is performed to remove the portions (inner portions of the oval circles) of the STI located at the two sides of the groove P and exposed by the second opening K2, and the groove is opened to be larger, so as to form a trench by a subsequent dry etching. Can be removed by reaction with dilute hydrofluoric acid with the shallow trench isolation STI in that portion (the inner portion of the oval).

As shown in fig. 11a and 11b, a dry etching is performed by using the stacked layer of the patterned ODL layer 154 and the SHB layer 155 as a hard mask, and the liner oxide layer 152 exposed by the second opening K2 and the substrate 100 with a partial thickness therebelow are etched and removed in the X direction, so as to form a trench in the active area AA. Illustratively, the trenches (U-shaped trenches) include first trenches 30 and second trenches 40 distributed in the Y direction in the active area AA, a plurality of the first trenches 30 are spaced apart in the X direction, and a plurality of the second trenches 40 are also spaced apart in the X direction. The first grooves 30 and the second grooves 40 may be symmetrically distributed.

Then, as shown in fig. 11a to 12b, ion implantation doping is performed on the sidewalls of the trench at the two ends in the X direction, so as to amorphize the substrate on the sidewalls at the two ends in the X direction; specifically, in one embodiment, boron may be ion implanted to amorphize portions of the sidewall substrate 100 at both ends in the X direction (inner portion of the oval circle), thereby facilitating oxidation and removal of the remaining substrate 100 at both sides of the trench (inner portion of the oval circle). Implanting boron into the sidewall of the trench at both ends in the X direction can also block the leakage between the source and drain caused by the conduction through the remaining substrate 200 (part inside the oval circle) on the sidewall of the trench (e.g., arsenic can be implanted into the source and drain). The bottom of the trench is not implanted with boron. In other embodiments, the dopant (ion implantation element) for amorphizing the substrate by ion implantation may further comprise: at least one of germanium, arsenic, nitrogen, indium, arsenic, carbon, xenon, antimony and argon. ODL layer 154 and SHB layer 155 are then removed.

Oxidizing the substrate 100 with the non-crystallized side wall of the groove (U-shaped groove) by means of thermal oxidation; and removing the oxide layer oxidized on the sidewall of the trench by using dilute hydrofluoric acid, thereby removing the remaining substrate 100 on both sides of the trench, so that the finally formed sidewalls of the trench at both ends in the X direction are defined by the adjacent shallow trench isolation STI (refer to fig. 2 and 12 a). And forming semi-floating gates in the grooves in sequence, wherein the semi-floating gates of each device are mutually isolated and insulated in the X direction through Shallow Trench Isolation (STI) around the side wall, and if substrates are left on the side walls at two ends of the X direction of the grooves, the insulation and the electrical property between a single device and adjacent devices are influenced. The liner oxide layer 152 may also be removed when removing the oxide layer on the sidewalls of the trench at both ends in the X direction.

The method for forming the groove can be applied to forming a memory, and the groove is used for forming the semi-floating gate transistor.

And after forming the groove, forming a grid insulation layer, covering the surface of the groove and the upper surface of the substrate by the grid insulation layer, and etching the grid insulation layer to form a contact window exposing the substrate.

And after forming the gate insulating layer and the contact window, continuously forming the semi-floating gate, the inter-gate dielectric layer and the control gate to form a gate stack.

And forming a side wall on the side wall of the grid laminated layer, carrying out ion implantation by taking the side wall as a mask to form a source region and a drain region, wherein a grid electrode junction insulating layer is not arranged between the substrate and the semi-floating gate at one side of the contact window close to the drain region.

The method for forming the trench of the present embodiment can be applied to two exemplary methods for manufacturing the memory device. In a first example, a memory device includes two adjacent semi-floating gate transistors having different drain regions and sharing the same source region, which helps to reduce the area occupied by all semi-floating gate transistors on a substrate and increase the integration density of the memory device. Illustratively, the structure of two adjacent semi-floating gate transistors is symmetrical, as shown in FIGS. 12 a-17. In a second example, the memory device includes a single semi-floating gate transistor, as shown in FIGS. 18-21.

Fig. 17 is a schematic cross-sectional structure of a first exemplary manufactured memory device with U-shaped channels. The memory device may also include other types of memory elements, logic elements, and the like. The present embodiment is specifically described by taking as an example the fabrication of a memory device including two semi-floating gate transistors sharing a source region. The two semi-floating gate transistors sharing the source region are respectively called a first semi-floating gate transistor and a second semi-floating gate transistor, and the first semi-floating gate transistor and the second semi-floating gate transistor are formed through the same process.

The steps after forming the trench in the method for manufacturing the memory device of the first example will be described in detail with reference to fig. 13 to 17.

As shown in fig. 13, a common source region i, a first drain region ii and a second drain region iii are preset on one side of the substrate close to the upper surface thereof, and are located on both sides of the common source region. Specifically, the first drain region ii, the first trench 30, the common source region i, the second trench 40, and the second drain region iii are sequentially distributed along the Y direction. The position of a common source region for forming a first semi-floating gate transistor and a second semi-floating gate transistor is called a common source region I, a first drain region II is used for forming a drain region of the first semi-floating gate transistor, a second drain region III is used for forming a drain region of the second semi-floating gate transistor, a semi-floating gate in the subsequently formed first semi-floating gate transistor is called a first semi-floating gate, and a semi-floating gate in the subsequently formed second semi-floating gate transistor is called a second semi-floating gate. The substrate 100 may be entirely of the second doping type or formed with a well region of the second doping type. Optionally, the substrate 100 has a well region (e.g., P-well) with a second doping type, the well region further has a doped region 105 formed therein with the first doping type and extending from the inside to the upper surface of the substrate 100, and the source region and the drain region of the semi-floating gate transistor are formed on top of the doped region 105.

A first trench 30 is formed in the substrate between the common source region i and said first drain region ii and a second trench 40 is formed in the substrate between the common source region i and said second drain region iii. The first trench 30 and the second trench 40 have a depth of about

In this embodiment, the depth of the first trench 30 and the depth of the second trench 40 are both greater than the depth of the doped region 105, that is, the bottom surface of the first trench 30 and the bottom surface of the second trench 40 are farther away from the upper surface f1 of the substrate than the bottom of the doped region 105 with reference to the upper surface f1 of the substrate 100.

In addition, it can be considered that the steps of well implantation, other ion implantation, annealing, etc. are completed in the substrate, and a well region (for example, a P-well in the present embodiment) of the second doping type and a doped region 105 extending from the inside of the well region to the upper surface of the substrate 100 are formed in the substrate 100.

A gate insulating layer 111 is formed, and the gate insulating layer 111 covers the surfaces of the first and

second trenches

30 and 40 and the upper surface of the substrate 100. The gate insulating layer 111 is used to isolate the substrate 100 from the floating gate material layer 121 formed later, and the gate insulating layer 111 covering the upper surface of the substrate can also serve as an etching stop when the floating gate material layer 121 is patterned. The material of the gate insulating layer 111 may include at least one of silicon dioxide, silicon nitride, and silicon oxynitride, and may be fabricated by thermal oxidation, Chemical Vapor Deposition (CVD), atomic layer deposition, or the like. The gate insulating layer 111 is dry etched to expose the substrate 100, and a first contact window 100a and a second contact window 100b are formed. Dry etching, the process is controllable, and the first contact window 100a and the second contact window 100b can be precisely formed. Specifically, the first contact window 100a is located between the first drain region ii and the first trench 30, and the second contact window 100b is located between the second drain region iii and the second trench 40.

As shown in fig. 14, a semi-floating gate material layer 121 is formed, wherein the semi-floating gate material layer 121 covers the substrate 100 exposed by the first contact window 100a and the second contact window 100b, and also covers the gate insulating layer 111 between the first contact window 100a and the second contact window 100b, and fills the first trench 30 and the second trench 40. The material of the semi-floating gate material layer 121 is polysilicon.

Specifically, as shown in fig. 13 and 14, a floating gate material original layer (original state) is formed on the substrate 100, covering the gate insulating layer 111 and the upper surface of the substrate 100 exposed by the first contact window 100a and the second contact window 100 b. The original layer of floating gate material of this embodiment fills the first trench 30 and the second trench 40, for example. The floating gate material original layer is used for forming the semi-floating gates of the first semi-floating gate transistor and the second semi-floating gate transistor. The original layer of floating gate material has a second doping type. In this embodiment, the material of the original layer of floating gate material is, for example, p-type doped polysilicon, wherein the p-type dopant may be introduced by a doping gas during a deposition process or by ion implantation after the polysilicon is deposited. Illustratively, polysilicon may be deposited to a thickness by a CVD process, followed by p-type ion implantation and annealing followed by Chemical Mechanical Polishing (CMP) to planarize the upper surface of the polysilicon to a desired thickness, e.g., the thickness of an original layer of floating gate material above the upper surface of the substrate 100About

Next, the original layer of floating gate material is etched to pattern, the remaining original layer of floating gate material is referred to as a semi-floating gate material layer 121 (intermediate state), and the semi-floating gate material layer 121 covers the substrate 100 exposed by the first contact window 100a and the second contact window 100b and also covers the gate insulating layer 111 located between the first contact window 100a and the second contact window 100 b. The projection of the layer of semi-floating gate material 121 on the substrate 100 completely covers the first contact window 100a and the second contact window 100 b. Preferably, the semi-floating gate material layer 121 and the second contact window 100b are aligned on a side close to the second drain region iii, and the semi-floating gate material layer 121 and the first contact window 100a are aligned on a side close to the first drain region ii. The semi-floating gate material layer 121 may be formed by etching the original layer of floating gate material using dry or wet etching. The gate insulating layer 111 is removed outside the coverage of the floating gate material layer 121.

It should be understood that if the gate insulating layer 111 between the contact window and the drain region is not preserved when forming the contact window, there will be no etching stop layer when etching the original layer of floating gate material, and the etching selectivity between the original layer of floating gate material (e.g. polysilicon material) and the substrate 100 (e.g. silicon material) is low, which may cause serious substrate damage, and thus affect the performance of the semi-floating gate transistor. In this embodiment, when the original layer of the floating gate material is etched, the gate insulating layer 111 located between the first drain region ii and the first contact window 100a and between the second drain region iii and the second contact window 100b may be used as an etching blocking layer, so as to prevent the surface of the substrate 100 from being damaged during the etching process. Preferably, the original layer of floating gate material can be etched in a dry etching mode of "End point detection (End PT) + Over etching (Over Etch)" to ensure that the semi-floating gate material within the removal range is removed completely.

As shown in fig. 15, an inter-gate dielectric layer 130 is formed, where the inter-gate dielectric layer 130 covers at least the upper surface and the side surfaces of the semi-floating gate material layer 121, and may also cover the upper surface of the substrate 100 at two sides of the semi-floating gate material layer 121. The material of the inter-gate dielectric layer 130 may be silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials, and the inter-gate dielectric layer 130 may have a single-layer structure or a multi-layer structure (e.g., an ONO structure) with more than two layers. Illustratively, the intergate dielectric layer 130 includes a silicon oxide layer 131 and a silicon nitride layer 1031 (i.e., an ON structure) stacked together.

A control gate material layer 141 is formed, and the control gate material layer 141 covers the inter-gate dielectric layer 130. The control gate material layer 141 is used to form the control gates of the first and second semi-floating gate transistors. Polysilicon with a certain thickness can be deposited by CVD or the like, and planarized to a desired thickness to obtain the control gate material layer 141. The control gate material layer 141 may be polysilicon of a first doping type, and in this embodiment, the control gate material layer 141 is doped n-type, for example.

As shown in fig. 16 and 17, the control gate material layer 141, the intergate dielectric layer 130 and the semi-floating gate material layer 121 are etched to form the independent and separate semi-floating gate transistors.

Specifically, the control gate material layer 141, the inter-gate dielectric layer 130 and the semi-floating gate material layer 121 of the common source region i are etched, and the control gate material layers 141 of the first drain region ii and the second drain region iii are etched; the remaining portions of the control gate material layer 141, the inter-gate dielectric layer 130 and the semi-floating gate material layer 121 between the first drain region ii and the common source region i form a first gate stack 300, and the remaining portions between the second drain region iii and the common source region i form a second gate stack 400.

The first gate stack 300 is located between the first drain region ii and the common source region i for forming a first semi-floating gate transistor. The first gate stack 300 includes a first floating gate 120 obtained by etching the semi-floating gate material layer 121, a first control gate 140 obtained by etching the control gate material layer 141, and a first inter-gate dielectric layer obtained by etching the inter-gate dielectric layer 130. The second gate stack 400 is located between the second drain region iii and the common source region i, and is used for forming a second semi-floating gate transistor, and the second gate stack 400 includes a second semi-floating gate obtained by etching the semi-floating gate material layer 121, a second control gate obtained by etching the control gate material layer 141, and a second inter-gate dielectric layer obtained by etching the inter-gate dielectric layer 130. Photolithography and an anisotropic dry etching process may be used to form the first gate stack 300 and the second gate stack 400. In the dry etching process, in order to avoid damage to the substrate 100 of the first drain region ii and the second drain region iii, the inter-gate dielectric layer 130 in the region may not be completely removed by adjusting the etching conditions. The gate insulating layer 111 of the common source region i is exposed.

As shown in fig. 17, a sidewall SP of the semi-floating gate is formed; specifically, side walls SP are formed on the sidewalls of the first gate stack 300 and the second gate stack 400, and ion implantation and annealing are performed to form a common source 101 in the substrate 100 corresponding to the common source region i, a first drain 103 in the substrate 100 corresponding to the first drain region ii, and a second drain 104 in the substrate 100 corresponding to the second drain region iii.

Through the above steps, the first and second half floating gate transistors are formed on the substrate 100.

The steps after forming the trench in the method for manufacturing the memory device of the second example will be described in detail with reference to fig. 18 to 21. The present embodiment is specifically described by taking the fabrication of a single semi-floating gate transistor memory device as an example.

As shown in fig. 18, a substrate 100 is provided, on the upper surface side of which a source region V and a drain region IV are provided. Specifically, the source region V, the trench 50, and the drain region IV are sequentially distributed along the Y direction. Forming a gate insulating layer 111 on the substrate 100, and etching the gate insulating layer 111 to form a contact window 100c exposing the substrate 100, wherein the contact window 100c is located between the drain region IV and the trench 50.

As shown in fig. 18 and 19, a floating gate material original layer (not shown) covering the substrate 100 and the gate insulating layer 111 is formed between the source region V and the drain region IV. Etching the floating gate material original layer to remove a partial region of the floating gate material original layer on one side of the source region V and a region between the contact window 100c and the drain region IV; the remaining original layer of floating gate material after etching is used as the semi-floating gate material layer 170 of the semi-floating gate transistor, which is also the final semi-floating gate. The gate insulating layer 111 outside the coverage of the semi-floating gate material layer 170 is removed by etching. A semi-floating gate material layer 170 covers the substrate 100 exposed by the contact window 100c and also covers the gate insulating layer 111 between the contact window 100c and the source region V; the material of the semi-floating gate material layer 170 is polysilicon.

As shown in fig. 20, an inter-gate dielectric layer 160 and a control gate material layer 181 are formed, and the inter-gate dielectric layer 160 covers the upper surface and the side surfaces of the semi-floating gate material layer 170, and also covers the upper surface of the substrate 100 at both sides of the semi-floating gate material layer 170. The control gate material layer 181 covers the inter-gate dielectric layer 160. The control gate material layer 181 serves as the control gate of the semi-floating gate transistor. The intergate dielectric layer 160 may have a single-layer structure or a multi-layer structure (e.g., an ONO structure) having two or more layers. Illustratively, the intergate dielectric layer 160 includes a silicon oxide layer 161 and a silicon nitride layer 161 stacked (i.e., ON structure).

As shown in fig. 20 and 21, the control gate material layer 181 and the intergate dielectric layer 160 are etched. Etching the control gate material layer 181 of the source region V and the drain region IV, and also etching to remove the inter-gate dielectric layer 160 on the sidewall of the semi-floating gate material layer 170 close to one side of the source region V; the remaining layer of control gate material serves as the control gate 180 of the semi-floating gate transistor. In the dry etching process, in order to avoid damage to the substrate 100 of the source region V and the drain region IV, the inter-gate dielectric layer 160 in the region may not be completely removed by adjusting the etching conditions.

Forming a semi-floating gate side wall SP; specifically, the semi-floating gate, the inter-gate dielectric layer 160 and the control gate 180 form a gate stack, a sidewall SP is formed on a sidewall of the gate stack, and ion implantation and annealing are performed to form a source 163 in the substrate 100 corresponding to the source region V and a drain 164 in the substrate 100 corresponding to the drain region IV.

In summary, the present invention provides a method for manufacturing a memory device, including: providing a front-end device; forming an ODL layer; baking the ODL layer; etching layer by layer to pattern the photoresist layer, the SHB layer and the ODL layer, and sequentially transferring the opening patterns of the corresponding grooves from the photoresist layer to the ODL layer; and etching the liner oxide layer exposed by the opening in the active region and the substrate with partial thickness by taking the patterned ODL layer as a mask to form the groove.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the device disclosed by the embodiment, the description is relatively simple because the device corresponds to the method disclosed by the embodiment, and the relevant part can be referred to the method part for description.

The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.

Claims

1. A method for manufacturing a trench is characterized by comprising the following steps:

2. The method of claim 1, wherein baking the ODL layer comprises: the baking temperature is 300-400 ℃, and the baking time is as follows: 60-120 minutes.

3. The method of claim 1, wherein after the etching to pattern the ODL layer and before the forming the trench, further comprising:

4. The method of claim 1, wherein etching to pattern the ODL layer comprises: the etching pressure is less than 10 mTorr; power: 300W-500W; bias voltage: 100V-200V; the etching gas comprises argon and oxygen, the flow rate of the etching gas is 1000 sccm-2000 sccm, and the flow ratio of the argon to the oxygen is 5: 1-10: 1.

5. The method of fabricating a trench according to claim 1, wherein the method further comprises: a BARC layer is formed between the SHB layer and the photoresist layer.

6. The method of claim 5, wherein etching layer by layer to pattern the photoresist layer, the SHB layer, and the ODL layer comprises:

7. The method of claim 1, wherein an X direction and a Y direction are defined in a plane parallel to the substrate and perpendicular to each other, a Z direction is defined in a plane perpendicular to the substrate, and the shallow trench isolations and the active regions are alternately arranged along the X direction.

8. The method of forming a trench according to claim 7 further comprising, after forming the trench:

9. A method of fabricating a memory device comprising forming a trench using the method of any of claims 1-8, and using said trench to form a semi-floating gate transistor.

10. The method of manufacturing a memory device according to claim 9, wherein after the trench is formed, a gate insulating layer is formed to cover a surface of the trench and an upper surface of the substrate, and the gate insulating layer is etched to form a contact window exposing the substrate.

11. The method of fabricating a memory device of claim 10, further comprising: and after the gate insulating layer and the contact window are formed, continuously forming a semi-floating gate, an inter-gate dielectric layer and a control gate to form a gate stack.

12. The method of manufacturing a memory device according to claim 11, wherein a sidewall is formed on a sidewall of the gate stack, ion implantation is performed using the sidewall as a mask to form a source region and a drain region, and the gate insulating layer is not formed between the substrate and the semi-floating gate on a side of the contact window adjacent to the drain region.

13. The method of claim 11, wherein adjacent ones of the gate stacks share a source region.