CN112434800B - Control device and brain-like computing system - Google Patents

Control device and brain-like computing system Download PDF

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Publication number
CN112434800B
CN112434800B CN202011313163.7A CN202011313163A CN112434800B CN 112434800 B CN112434800 B CN 112434800B CN 202011313163 A CN202011313163 A CN 202011313163A CN 112434800 B CN112434800 B CN 112434800B
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task
trigger
module
current
functional
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CN112434800A (en
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裴京
施路平
王冠睿
马骋
徐海峥
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Tsinghua University
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Tsinghua University
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/061—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using biological neurons, e.g. biological neurons connected to an integrated circuit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present disclosure relates to a control device and a brain-like computing system, the device comprising: the first trigger module; a second trigger module; the multiplexer is electrically connected with the first trigger module and the second trigger module; the control module is electrically connected to the multi-path selection module and is used for controlling the multi-path selector to transmit any one of the one or more first trigger signals and any one of the one or more second trigger signals to one or more functional cores in the processor so that the one or more functional cores execute the subtasks of the tasks according to the received first trigger signals and the received second trigger signals. Through the device, the embodiment of the disclosure can realize the segmentation of independent tasks, quicken the execution speed, reduce the running time, improve the performance of the chip and reduce the power consumption.

Description

Control device and brain-like computing system
Technical Field
The disclosure relates to the technical field of artificial intelligence, in particular to a control device and a brain-like computing system.
Background
The explosive growth of large data information network core intelligent mobile devices has resulted in massive unstructured information, accompanied by a dramatic increase in the energy efficient processing requirements for such information. Traditional von neumann architecture chips adopt bus communication, synchronization, serial and centralized working modes, increase density according to moore's law, and are expected to be scaled up to physical limits in the next 10 to 15 years, and the development is necessarily fundamentally limited.
The chip architecture of the many-core neuromorphic chip is derived from the chip architecture, and the structure is different from the traditional computer processing mode, and has great advantages when processing some non-formalized problems through the distributed storage and parallel collaborative processing of information. The trigger mechanism of the traditional many-core neuromorphic chip architecture has larger limitation and cannot divide independent tasks.
Disclosure of Invention
In view of this, the present disclosure proposes a control device comprising:
the first trigger module is used for generating one or more first trigger signals, wherein each first trigger signal corresponds to each task;
the second trigger module is electrically connected with the first trigger module and is used for generating one or more second trigger signals according to the first trigger signals, wherein the second trigger signals correspond to the subtasks of the tasks;
the multiplexer is electrically connected with the first trigger module and the second trigger module;
the control module is electrically connected to the multi-path selection module and is used for controlling the multi-path selector to transmit any one of the one or more first trigger signals and any one of the one or more second trigger signals to one or more functional cores in the processor so that the one or more functional cores execute the subtasks of the tasks according to the received first trigger signals and the received second trigger signals.
In a possible implementation manner, the device further includes a first timing module, electrically connected to the first trigger module, where the first timing module includes a first timing clock, and the first timing module is configured to start the first timing clock when receiving the first trigger signal, so as to time an execution period of a current task;
the first triggering module is further configured to determine that a condition for triggering an execution period of a next task is met and generate a first triggering signal corresponding to the execution period of the next task when the first timing clock reaches a first threshold, all the subtasks of the current task are completely executed, and the current task is not the last task.
In a possible implementation manner, the first trigger module is further configured to generate a forced ending signal, where the first timing clock reaches a third threshold, and the forced ending signal is used to forcibly end execution of each current sub-task in the current task, so as to forcibly end execution of the current task;
the control module is further configured to transmit the forced ending signal to each functional core of the current task using the multiplexer.
In one possible implementation manner, the device further comprises a second timing module electrically connected to the second trigger module, where the second timing module includes one or more second timing clocks, and the second timing module is configured to start the one or more second timing clocks when receiving the second trigger signal, so as to time the execution period of each sub-task of the current task,
the second triggering module is further configured to determine that a condition for triggering an execution period of a next sub-task of each current sub-task in the current task is met when the second timing clock reaches a second threshold and the function cores corresponding to the second triggering signals all end execution of each current sub-task, and generate the second triggering signals corresponding to each next sub-task.
In a possible implementation manner, the control module is further configured to receive an operation end signal output by each functional core corresponding to the second trigger signal, and generate a subtask end signal when each functional core outputs the operation end signal, so as to determine that all functional cores corresponding to the second trigger signal end execution of the current subtask;
The apparatus further comprises:
and the first storage module is electrically connected with the control module and used for storing the subtask ending signal.
In one possible implementation manner, the control module is further configured to generate a task end signal to determine that all the subtasks of the current task corresponding to the first trigger signal are all ended to be executed, where the subtask end signals of all the subtasks of the current task are stored in the first storage module;
the apparatus further comprises:
and the second storage module is electrically connected with the control module and used for storing the task ending signal.
In one possible implementation manner, the control module is further configured to allocate functional cores for each task and subtasks of each task, number functional cores in the processor, number a first functional core set allocated to each task, and number a second functional core set corresponding to each subtask of each task.
In one possible implementation, the apparatus includes a plurality of phase group registers, a first select register, a functional core register, a second select register, wherein,
the phase group register is configured as a two-dimensional register with the size of s x n bits, the first dimension represents the current task number, the second dimension represents the subtask number included in the current task, and s and n are both positive integers;
The first selection register is configured as a two-dimensional register with m x y bits, the first dimension represents the current functional core number, the second dimension represents the task number to which the current functional core belongs, wherein m and y are positive integers, and y=log 2 s；
The functional core register is configured as a two-dimensional register with the size of n x m bits, wherein the first dimension represents the subtask number, and the second dimension represents the functional core included in the subtask;
the second selection register is configured as a two-dimensional register with m x bits, the first dimension represents the number of the functional core, and the second dimension represents the subtask number of the current functional core, wherein x=log 2 n。
In one possible implementation, the control module is further configured to,
releasing the functional core in the processor corresponding to the first trigger signal under the condition that a preset condition is met, wherein the preset condition comprises:
the current task is the last task and the current task is finished executing; or alternatively
When execution of the current task is forcibly ended.
According to another aspect of the present disclosure, there is provided a brain-like computing system including the control device.
Through the device, the embodiment of the disclosure can generate one or more first trigger signals according to the number of the tasks to be executed, generate one or more second trigger signals, control corresponding functional cores to execute all sub-tasks of the current task according to the first trigger signals and the one or more second trigger signals, support parallel or mixed operation of a plurality of asynchronous tasks, and simultaneously divide the current task into all sub-tasks to enable the functional cores with similar tasks to be executed simultaneously, so that independent tasks can be divided through a two-stage trigger mechanism, the execution speed is increased, the running time is reduced, and the performance of the chip is improved; the corresponding functional cores are controlled by the trigger signals, so that the unselected functional cores are in a dormant state, and the power consumption is reduced. The task may be a network or an application task, for example, a task for performing a neural network operation (for example, a VGG network or a res net50 network), or a task for running application software, etc.
Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features and aspects of the present disclosure and together with the description, serve to explain the principles of the disclosure.
Fig. 1 shows a schematic diagram of a control device according to an embodiment of the present disclosure.
Fig. 2 shows a grouping schematic of processor functional cores according to an embodiment of the present disclosure.
Fig. 3 shows a schematic trigger timing diagram of a control device according to an embodiment of the present disclosure.
Fig. 4 shows a schematic trigger timing diagram of a control device according to an embodiment of the present disclosure.
Fig. 5 shows a schematic diagram of a control device according to an embodiment of the present disclosure.
Fig. 6a, 6b show schematic diagrams of a control device according to an embodiment of the present disclosure.
Detailed Description
Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
In addition, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.
With the continuous development of the technical field of neural networks, massive unstructured information is generated, and the energy-efficient processing requirement for the information is increased sharply. The many-core neuromorphic chip architecture is different from the traditional computer processing mode, and has great advantages when processing some non-formalized problems through distributed storage and parallel collaborative processing of information. However, the trigger mechanism in the conventional chip cannot perform independent network task division when performing multiple networks, and has a large limitation.
In order to further improve performance, the embodiment of the disclosure provides a control device, which controls functional cores through two stages, wherein the first stage of triggering can divide different networks or applications, and the second stage of triggering can divide similar computing tasks in the networks or the applications and distribute the computing tasks in the functional cores for operation, so that the performance of chips is effectively improved, and the control device has higher application value.
Referring to fig. 1, fig. 1 shows a schematic diagram of a control device according to an embodiment of the disclosure.
As shown in fig. 1, the apparatus includes:
a first trigger module 10 for generating one or more first trigger signals, wherein each first trigger signal corresponds to a respective task;
The second trigger module 20 is electrically connected to the first trigger module 10, and is configured to generate one or more second trigger signals according to the first trigger signals, where the second trigger signals correspond to sub-tasks of the task;
a multiplexer 30 electrically connected to the first trigger module 10 and the second trigger module 20;
the control module 40 is electrically connected to the multiplexing module 30, and is configured to control the multiplexer 30 to transmit any one of the one or more first trigger signals and any one of the one or more second trigger signals to one or more functional cores in the processor 1, so that the one or more functional cores execute the sub-tasks of the tasks according to the received first trigger signals and second trigger signals.
Through the device, the embodiment of the disclosure can generate one or more first trigger signals according to the number of the tasks to be executed, generate one or more second trigger signals, control corresponding functional cores to execute all sub-tasks of the current task according to the first trigger signals and the one or more second trigger signals, support parallel or mixed operation of a plurality of asynchronous tasks, and simultaneously divide the current task into all sub-tasks to enable the functional cores with similar tasks to be executed simultaneously, so that independent tasks can be divided through a two-stage trigger mechanism, the execution speed is increased, the running time is reduced, and the performance of the chip is improved; the corresponding functional cores are controlled by the trigger signals, so that the unselected functional cores are in a dormant state, and the power consumption is reduced. The task may be a network or an application task, for example, a task for performing a neural network operation (for example, a VGG network or a res net50 network), or a task for running application software, etc.
The control device of the embodiment of the present disclosure may be used in a terminal or a server, where the terminal is also called a User Equipment (UE), a Mobile Station (MS), a Mobile Terminal (MT), etc., and is a device that provides voice and/or data connectivity to a user, for example, a handheld device with a wireless connection function, an in-vehicle device, etc. Currently, some examples of terminals are: a mobile phone, a tablet, a notebook, a palm, a mobile internet device (mobile internetdevice, MID), a wearable device, a Virtual Reality (VR) device, an Augmented Reality (AR) device, a wireless terminal in industrial control (industrial control), a wireless terminal in unmanned driving (selfdriving), a wireless terminal in teleoperation (remote medical surgery), a wireless terminal in smart grid (smart grid), a wireless terminal in transportation security (transportation safety), a wireless terminal in smart city (smart city), a wireless terminal in smart home (smart home), a wireless terminal in the internet of vehicles, and the like.
The various modules of the disclosed embodiments may be implemented by special purpose hardware circuits, or by general purpose hardware circuits, and the control modules may include, for example, a controller with functions to execute instructions, and may be implemented in any suitable manner, for example, using a microprocessor, a Central Processing Unit (CPU), control logic in a memory controller, etc., including, but not limited to, the following types of chips: ARC 625D, atmel AT91SAM, microchip PIC18F26K20, silicone Labs C8051F320. Within the processor 101, the executable instructions may be executed by hardware circuits such as logic gates, switches, application specific integrated circuits (Application Specific Integrated Circuit, ASIC), programmable logic controllers, and embedded microcontrollers.
Referring to fig. 2, fig. 2 shows a block diagram of a processor functional core according to an embodiment of the present disclosure.
In one possible implementation, the processor to which the apparatus of the embodiments of the present disclosure may be applied may be a many-core neuromorphic chip, as shown in fig. 2, where the processor may include a plurality of functional cores, and the functional cores of the processor may be grouped according to different types of tasks.
In one example, as shown in fig. 2, step_grp (beat timing group) and phase_grp (Phase timing group) may respectively represent corresponding function core sets, step_grp0, step_grp1, step_grp2 represent function core sets corresponding to respective first trigger signals, phase_grp0, phase_grp1, phase_grp2, phase_grp3, phase_grp4, phase_grp5 represent function core sets corresponding to respective second trigger signals, and C00 to C44 represent different function cores. For example, phase_grp0 corresponds to a set of functional cores including functional cores C00, C01, C10, and C11, phase_grp1, phase_grp2, phase_grp3, phase_grp4, and phase_grp5 are described in terms of the relationship of the functional cores, phase_grp0 corresponds to a set of three functional cores including phase_grp0, phase_grp1, and phase_grp2, phase_grp1, and step_grp2 are described in terms of the relationship of phase_grp3, phase_grp4, and phase_grp5, as shown in fig. 2, one phase_grp may be included in one or more phase_grp (e.g., C13 is included in phase_grp1 and is included in phase_grp3), one core is a set of three functional cores corresponding to phase_grp0, phase_grp1, phase_grp2 is included in phase_grp3), and two separate cores are provided in one core is a set of cores, and two separate cores may be overlapped with each other (e.g., phase grp3 is included in Phase grp3) and data may be overlapped with each other as shown in fig. 2.
In one example, the same step_grp may be used to perform the same network task, each phase_grp under the same step_grp may be used to perform the same or similar tasks under the same network task, and the functional cores under the same phase_grp may be used to perform primitive operations, in one possible implementation, after ending a certain network task or application task, the set of functional cores may be repartitioned.
In a possible implementation manner, the control device may be applied to a system on a chip including a plurality of functional cores (or called processor cores), each first trigger signal corresponds to a part of the functional cores in the system on a chip, that is, a set of functional cores, the first trigger signal may trigger the functional cores to operate by generating second trigger signals to perform sub-tasks, and each second trigger signal may correspond to one or more of the part of the functional cores. The corresponding relation between the first trigger signal, the second trigger signal and the functional core can be set manually or automatically according to the requirement. The correspondence may be released after a complete task is performed (e.g., completing a neural network operation) for subsequent resetting.
In one possible implementation manner, the correspondence between the first trigger signal, the second trigger signal and the functional cores may be reset before starting a complete task, specifically, if there are enough idle functional cores needed, the setting may be completed and the execution of a complete task may be started, if there are no idle functional cores, the release of the functional cores after the execution of other tasks is ended may be waited, and after the number of idle functional cores meets the requirement, the setting may be completed and the execution of a complete task may be started. Because the same functional core can respectively correspond to different second trigger signals or first trigger signals, multiplexing signals can be set for the functional cores which can be multiplexed after the setting is completed, so that the functional cores can be used as idle functional cores to participate in operation when other tasks are set for the functional cores, the functional cores are fully utilized, and the performance and the utilization rate of the system are improved.
In one possible implementation, the execution period of the current task may include one or more execution periods of the subtasks, i.e., between two first trigger signals, a second trigger signal of multiple periods may occur. Taking a neural network operation task as an example, for a neural network with smaller operation amount, a first trigger signal can complete one operation (current task) of the whole neural network in one execution period, wherein a second trigger signal can complete one link of the neural network operation, such as operation of a network layer, in each period, and a functional core corresponding to each second trigger signal can execute similar operation (subtask) in each link, such as addition or multiplication, and each functional core can be used for executing corresponding primitive operation. For example, still taking fig. 2 as an example, four functional cores C00, C01, C10, C11 corresponding to phase_grp0 may perform addition, 6 functional cores C02, C03, C12, C13, C22, C23 corresponding to phase_grp1 may perform multiplication, etc., respectively, which the present disclosure is not limited to. For a neural network with a large operation amount, the first trigger signal may complete one link in one operation of the whole neural network in one execution period, for example, an operation of one network layer (current task), that is, the current task may also be a subtask of a higher-level task (whole neural network operation task), in this case, the setting of functional cores between the subtasks may be used, and between the subtasks and the execution period of the subtasks, there may be no need to release functional cores and repartition. The second trigger signal may complete a part of links in each period, for example, a convolution operation in an operation of a network layer, and the functional core corresponding to each second trigger signal may perform a similar operation (subtask) in each link.
In one possible implementation manner, the first trigger module may generate the first trigger signal according to an external input signal, or may generate the first trigger signal by itself. For example, the apparatus may further include an external trigger module 90 (as shown in fig. 5), for the initial first trigger signal, the external trigger module 90 may generate and input a start signal when a new task needs to be performed, so that the first trigger module generates the first trigger signal, or the external trigger module 90 may directly generate the first trigger signal; in the task execution process, the first trigger module may generate a new first trigger signal when it is determined that the task period is not ended. As will be described in detail below.
Referring to fig. 3, fig. 3 is a schematic diagram illustrating a trigger timing of a control device according to an embodiment of the disclosure.
Wherein clk represents a reference clock, clk set 1 represents a reference clock number; step group0 and step group1 represent sets of functional cores (or beat timing groups) corresponding to respective first trigger signals, and different first trigger signals may be used to trigger respective corresponding sets of functional cores to perform different tasks, for example, one first trigger signal is used to perform an operation task of one neural network, and another first trigger signal is used to perform an operation task of another neural network, or an operation task of application software, etc. The set of functional cores corresponding to the first trigger signal may be referred to as a beat timing group; step_c0 represents a first trigger signal corresponding to step group0, and may be referred to as a beat trigger signal corresponding to step group 0; step_ck0 sets 1 to indicate that a beat trigger signal is received; step_ck1 represents a beat trigger signal corresponding to step group1, and step_ck1 is set 1 to represent that a beat trigger signal is received; p_grp0_ck and p_grp1_ck respectively represent two second trigger signals corresponding to step group0, the second trigger signals can be called phase trigger signals, the functional core set corresponding to the second trigger signals can be called phase timing sequence group, and the phase trigger signal set 1 represents that one phase trigger signal is received; p_grp2_ck, p_grp3_ck and p_grp4_ck respectively represent three phase trigger signals corresponding to step group1, and the phase trigger signal setting 1 represents that one phase trigger signal is received; s_grp0_finish represents a signal that the corresponding function core set of step group0 totally ends execution, that is, a signal that all subtasks of the current task (that is, the task corresponding to step group 0) totally end execution, which may be called a beat end signal of step group0, where the beat end signal is set to 1 when all phase timing groups in step group0 end execution of the corresponding all subtasks, otherwise, is set to 0; s_grp1_finish represents a signal that the corresponding set of functional cores of step group1 all end execution, which may be referred to as a beat end signal of step group 1; and setting 1 when all phase time sequence groups in step group1 finish executing all corresponding subtasks, otherwise setting 0.
As shown in fig. 3, in one possible implementation manner, for step group0, when step_ck0 is received, p_grp0_ck and p_grp1_ck are triggered, and all phase timing groups in step group0 are triggered at the same time, and a new phase timing group working period (may be called an execution period) is started, where the phase timing group working periods of different phase timing groups may be the same or different, a beat timing clock (may be called a first timing clock) may be started after receiving a beat trigger signal, when the clock number of the beat timing clock is equal to the beat end clock number, it may be checked whether all phase timing groups in the beat timing group end working, or whether a signal of s_grp0_finish 1 is received, if yes, then a next beat timing group working period (step_c0 automatic 1) is triggered, or all functional cores in the end timing groups are released, when the next beat timing group starts to end after waiting for the next end working period, or when all beat timing groups end to end, and all beat timing groups are forced to end, and if all phase timing groups do not end, a signal is forced to end after all beat timing groups are forced, and all the beat timing clocks are forced to end, and all the timing clocks are completed. The same applies to step_ck1.
It should be noted that the number of duty cycle clocks of the phase timing group in the same beat timing group may be the same or different; the phase timing groups belonging to the same beat timing group are synchronous when receiving the phase trigger signal and triggering the corresponding first subtask, the automatic triggering of the subsequent subtasks after the execution of the first subtask is finished can be asynchronous, and the phase timing groups belonging to different beat timing groups can be asynchronously triggered. Different beat timing groups may also be asynchronous.
Referring to fig. 4, fig. 4 is a schematic diagram illustrating a trigger timing of a control device according to an embodiment of the disclosure.
In one example, as shown in fig. 4, clk represents a reference clock, clk set 1 represents 1 reference clock number; s_ck represents a first trigger signal, which may be referred to as a beat trigger signal, and phase group0 and phase group1 represent different sets of functional cores (or referred to as phase timing groups) corresponding to second trigger signals, which may be referred to as phase timing groups; s_ck is set 1 to indicate that a beat trigger signal is received; p_grp0_ck represents a second trigger signal corresponding to phase group0, and the second trigger signal may be referred to as a phase trigger signal; p_grp0_ck is set 1 to indicate that a corresponding phase trigger signal is received; p_grp1_ck represents a phase trigger signal corresponding to phase group 1; p_grp1_ck represents that a corresponding phase trigger signal is received; core0, core1 and core2 respectively represent three functional cores under phase group0, and core3 and core4 respectively represent two functional cores under phase group 1; the p_grp0_finish indicates a signal that all the functional cores of phase group0 end execution, and may be referred to as a phase group0 phase end signal; and setting 1 when all the functional cores in the phase group0 finish execution operation, otherwise, setting 0, wherein p_grp1_finish represents a signal for finishing the execution of all the functional cores in the phase group1, which can be called a phase end signal of the phase group1, and setting 1 when all the functional cores in the phase group1 finish execution operation, otherwise, setting 0. The beat end signal may be obtained from the phase end signal phase of the phase timing group corresponding to each phase timing group under the beat timing group, that is, p_grp0_finish and p_grp1_finish phase may be obtained as s_grp0_finish in fig. 4. p0, p1, p2, and p3 respectively represent that the corresponding functional core is in the corresponding execution operating state.
In one possible implementation, as shown in fig. 4, for phase group0, when s_ck is received, p_grp0_ck is triggered synchronously, and all the functional cores in the phase group0 are triggered simultaneously, so that core0, core1 and core2 are controlled to start executing operations, wherein the time for executing operations by different functional cores may be the same or different, a phase timing clock (may be called a second timing clock) may be started after the functional cores start working, when the clock number of the phase timing clock is equal to the clock number of the phase end clock, whether the functional cores in the phase timing group all end the current subtasks may be checked, if yes, a next phase timing group working period (may be called an executing period) is triggered, otherwise, after all the operations for executing the current subtasks are waited to complete, a next phase timing group working period is started. If the function core in the phase time sequence group checks that all the subtasks of the current task end execution, the p_grp0_finish is set to 1, and when the function core in the phase time sequence group does not completely end the operation of executing all the subtasks of the current task, the execution is continued until the next task is started after the complete of all the execution, or a forced ending signal of the beat time sequence group is received to forcedly end all the subtasks. The same applies to phase group 1.
It should be noted that, the clocks of each functional core executing operation under the same phase timing group may be the same or different; functional cores belonging to the same phase timing group are triggered synchronously, and functional cores belonging to different phase timing groups can be triggered asynchronously.
The triggering sequence of the control device is described above by way of example, and is described below by way of example in connection with a possible implementation of the control device.
Referring to fig. 5, fig. 5 shows a schematic diagram of a control device according to an embodiment of the disclosure.
In a possible implementation manner, as shown in fig. 5, the apparatus may further include a first timing module 50 electrically connected to the first trigger module 10, where the first timing module 50 may include a first timing clock, and the first timing module 50 is configured to start the first timing clock when receiving the first trigger signal, so as to time an execution period of a current task;
in a possible implementation manner, the first trigger module 10 may be further configured to determine that a condition for triggering an execution period of a next task is met and generate a first trigger signal corresponding to the execution period of the next task when the first timing clock reaches a first threshold, and all subtasks of the current task are all executed and the current task is not the last task.
In the embodiment of the disclosure, all the subtasks of the current task are completely executed, namely, the completion of the execution of the current task is indicated, and by judging whether all the subtasks of the current task are completely executed or not and triggering the execution period of the next task when all the subtasks are completely executed, the idle of the functional cores can be reduced as much as possible, each functional core is utilized to the greatest extent, and the execution efficiency is improved.
In one example, the first threshold may be set in advance and the different first trigger signals may correspond to different first thresholds. For example, the first threshold (clock number) may be directly input from the outside, or a parameter related to the first threshold may be input, and the control module may perform a correlation operation to determine the first threshold according to the obtained parameter.
In one possible implementation, as shown in fig. 5, the apparatus may include a register module 70.
In one example, the register module 70 may include a first threshold register to receive a first threshold of external input.
In one example, the first threshold may be a change value that changes according to different tasks, and may be received each time the execution period of the current task is triggered, or may be a preset fixed value, and may be received only once, and may be reused later.
In one example, in a case where a condition for triggering an execution period of a next task is satisfied, the execution period of the next task may be triggered, that is, the execution of the next task is started, and the execution manner of the next task may be the same as that of the current task.
In one example, the first timing clock may be timed once every one reference clock cycle and determine whether the first threshold is reached.
By setting the first threshold, the embodiment of the disclosure can realize the advanced control and deployment of the execution periods of different network applications, thereby realizing asynchronous independent operation of different tasks and accelerating the operation speed.
In one example, the first timing clock may be re-clocked from 0 whenever a new first trigger signal is generated.
By comparing the timing time length of the first timing clock with the first threshold value, whether the condition for triggering the execution period of the next task is met or not is judged, and the control of the execution period of the current task can be realized, so that different tasks can be better scheduled, the running time is reduced, and the execution efficiency is improved.
In a possible implementation manner, the first trigger module 10 may be further configured to generate a forced ending signal, where the first timing clock reaches a third threshold, where the forced ending signal is used to forcedly end execution of each current sub-task in the current task, so as to forcedly end execution of the current task;
In a possible implementation, the control module 40 may be further configured to transmit the forced ending signal to each functional core of the current task by using the multiplexer 30, so that each functional core ends the operation.
In an example, the third threshold may be greater than the first threshold, may be a variable value that is changed according to different tasks, and may be received each time the execution period of the current task is triggered, or may be a preset fixed value, and may be received only once, and may be reused later.
In one example, the register module 70 may include a third threshold register to store a third threshold value, which may be read or written to obtain the third threshold value or set.
In one example, in the case that the current task reaches the third threshold value and is still not completed, the current task may be blocked due to a program error, for example, for a certain link in a certain neural network task, the estimated clock number required for executing the link task is 500 clocks, so that in the case that the first timing clock reaches 1000 clocks and the link task is not completed, if the execution of the link task is still not completed, a program error is likely to occur, and a dead loop cannot be completed (this is a pathological state) and forced termination is required, so that in this case, the third threshold value may be set to 1000 clocks, and the task is not completed when the third threshold value is reached and forced termination is required. If the current task is a subtask of the previous task, the whole previous task can be forcedly ended, and after the execution of the whole task is forcedly ended, the function core set corresponding to the first trigger signal can be released, so that unnecessary function core resources are prevented from being occupied.
By means of the mechanism for realizing forced ending of the current task, the maximum clock number of the current task execution is controlled, the dead loop that the task cannot end due to program errors and the like can be avoided, the possibility of wasting a large amount of unnecessary functional core resources is avoided, the power consumption is further reduced, and the running efficiency is improved.
In one possible implementation, as shown in fig. 5, the apparatus may further include a second timing module 60 electrically connected to the second trigger module 20, where the second timing module 60 may include one or more second timing clocks, and the second timing module is configured to start the one or more second timing clocks when receiving the second trigger signal, to time an execution period of each sub-task of the current task,
in a possible implementation manner, the second trigger module 20 may be further configured to determine that a condition for triggering an execution period of a next sub-task of the current sub-tasks in the current task is met and generate the second trigger signal corresponding to each next sub-task when the second timing clock reaches a second threshold and the function cores corresponding to the second trigger signals all end execution of the current sub-tasks.
According to the embodiment of the disclosure, under the condition that the function core set corresponding to the current subtask is not completely finished to be executed, after the function core set is completely finished to be executed, the execution period of the next subtask is triggered, so that the possibility that the current subtask is not finished to start the next subtask and the current task is blocked in a certain subtask and cannot be continued is prevented, the error reporting condition is prevented, the deployment and the scheduling of each task can be successfully executed, and the corresponding performance is improved.
In one example, the second threshold may be preset, and the set of functional cores corresponding to the different second trigger signals may correspond to the corresponding second end clock number.
In one example, the register module 70 may include a second threshold register to receive a second threshold of external input.
In one example, the second end clock number may be a change value that is changed according to different subtasks, and may be received each time the execution period of the subtasks under the current task is triggered, or may be a preset fixed value, and may be received only once, and may be reused later.
The second threshold value is determined according to the preset second end clock number, so that the execution period of different subtasks can be controlled and deployed in advance, asynchronous independent operation of the different subtasks is realized, and the operation speed is increased.
In one example, when the condition of triggering the execution period of the next sub-task of each current sub-task is met, triggering the execution period of each next sub-task of each current sub-task, that is, starting to execute each next sub-task, the execution mode of the next sub-task may be the same as that of the current sub-task, and so on until all sub-tasks of the current task are executed or the execution of the sub-task is finished after receiving the forced ending signal.
In one example, the second timing module 60 controls the second timing clock to start timing when the second trigger signal is received, and the second timing clock may determine whether the second threshold is reached at each clock count; each second trigger signal may correspond to a second timing clock, and different second timing clocks may correspond to different second thresholds, for example, after a functional core set corresponding to one second trigger signal receives the second trigger signal, the second timing clock corresponding to the functional core set may be started and compared with the corresponding second threshold; the execution cycles of the functional core sets may be the same or different. The received second trigger signal here includes the second trigger signal generated from the first trigger signal and also includes the second trigger signal automatically generated in the case where the condition described below is satisfied, and the corresponding second timing clock may be re-timed from 0 whenever a new second trigger signal is generated.
And comparing the second timing clock with a second threshold value to judge whether the condition of triggering the execution period of the next sub-task of each current sub-task is met or not, so that the control of the execution period of each sub-task can be realized, each sub-task can be better scheduled, meanwhile, because different sub-tasks can have different execution periods, asynchronous execution of the sub-tasks can be realized, the execution speed of each sub-task is further accelerated, and the running time of the current task is reduced.
In a possible implementation manner, the control module 40 may be further configured to receive an operation end signal output by each functional core corresponding to the second trigger signal, and generate a subtask end signal when each functional core outputs the operation end signal, so as to determine that the functional core corresponding to the second trigger signal all ends execution of the current subtask;
in one possible implementation, the apparatus further includes: a first memory module (not shown) electrically connected to the control module for storing the subtask end signal.
In one example, each functional core of the processor generates an operation end signal upon completion of execution of its own operation (e.g., primitive operations such as multiplication, addition, etc.), and outputs the operation end signal to the control module.
Referring to fig. 6a together, fig. 6a and 6b are schematic diagrams of a control device according to an embodiment of the disclosure.
As shown in FIGS. 6a and 6b, the processor may include, for example, m functional cores (cores), and in one example, the control module may be further configured to number each functional core of the processor to uniquely identify each functional core, e.g., the functional cores of the processor may be configured with an identification of core [0], core [0] … core [ m-2], core [ m-1], respectively.
In one example, each of the function cores may be low (0) when performing the primitive operation, the operation end signal (for example, core_finish [0], corresponding to the function core [0 ]), and high (1) when the function core [0] completes the execution of the primitive operation, in which case the control module may determine the state (idle state or operation state) of the function core by detecting the operation end signal, and when the operation end signals of all the function cores in the function core set corresponding to the second trigger signal are all high, the control module generates the sub-task end signal to determine that the function cores corresponding to the second trigger signal all end the execution of the current sub-task.
In one example, the control module may perform an and operation on the operation end signal in each functional core to determine a subtask end signal corresponding to the second trigger signal.
In one example, the control module may be further configured to allocate functional cores to respective tasks, the control module may allocate idle functional cores to respective tasks according to operation requirements required by the tasks, for example, a current task corresponding to a first trigger signal may be allocated with a plurality of functional cores to obtain a beat timing group, one or more second trigger signals generated according to the first trigger signal correspond to one or more sub-tasks of the current task, the control module further allocates a plurality of functional cores allocated to the current task to respective sub-tasks according to operation requirements of the sub-tasks to obtain one or more phase timing groups, when a plurality of tasks (networks or applications) exist, the control module may allocate and obtain a plurality of beat time sequence groups and a plurality of phase time sequence groups, further, the control module may number each beat time sequence group and each phase time sequence group, as shown in fig. 6a, assuming that a certain beat time sequence group includes n phase time sequence groups (phase groups) and are numbered as phase_grp [0] to phase_grp [ n-1] in sequence, when the control module determines that operation end signals of all functional cores in the phase time sequence group corresponding to the subtasks are at high levels, the control module generates subtask end signals phase_grp_finish [0] (corresponding to the phase time sequence group phase_grp [0 ]) to phase_grp_finish [ n-1] (corresponding to the phase time sequence group phase_grp [ n-1 ]).
In one example, as shown in fig. 6a, the register module 70 may further include a function core register (core_en, for example core_en [0,0 ]), the function core register being configured as a two-dimensional register with a size of m×n bits, the first dimension representing a function core number (for example core_en [0,0 ]) the first dimension representing that the function core is a function core [0], which belongs to the phase timing group phase_grp [0 ]), the second dimension representing a subtask number comprised by a subtask, wherein n, m are both positive integers, and n is less than or equal to m.
In one example, the first storage module may include a subtask end signal register (phase_grp_finish) to store the subtask end signal, which may be configured as n bits, corresponding to each phase timing group (one task may include one or more subtasks, corresponding to one or more phase timing groups) when all functional cores in the phase timing group complete an operation, the subtask end signal corresponding to the phase timing group may be 1, otherwise may be 0.
In a possible implementation manner, the control module 40 may be further configured to generate a task end signal to determine that all the subtasks of the current task corresponding to the first trigger signal are all finished executing when the subtask end signals of all the subtasks of the current task are stored in the first storage module.
In one possible implementation, the apparatus may further include: a second memory module (not shown in fig. 5) electrically connected to the control module for storing the task end signal.
In one example, as shown in FIG. 6b, the control module may number (step_grp) for each beat timing group, e.g., assuming there are s tasks, the control module may establish s beat timing groups (numbered step_grp [0] -step_grp [ s-1 ]).
In one example, the register module 70 may include a phase group register (e.g., phase_group_en [0,0 ]), where the phase group register is configured as a two-dimensional register having a size of s×n bits, the first dimension representing a subtask number (or referred to as a phase timing group number), and the second dimension representing a current task number (or referred to as a beat timing group number) that the current task includes, where s, n are both positive integers. For example, the first dimension of the phase group register phase_group_en [0,0] represents the phase timing group phase_group [0], and the second dimension represents the beat timing group step_group [0], i.e., the phase timing group phase_group [0] belongs to the beat timing group step_group [0].
In one example, the second storage module may include a task end signal register (step_grp_finish) for storing task end signals of the respective beat timing groups, and the task end signal register may be configured to include s bits corresponding to the s beat timing groups, respectively, for example, the task end signal register step_grp_finish [1] for storing task end signals of the beat timing groups step_grp [1 ].
In one example, the control module may read the subtask end signal in the subtask end signal register phase_grp_finish, and perform an and operation on the subtask end signals of each subtask (phase timing group) to obtain a task end signal of the current task (beat timing group), for example, when all phase timing groups in one beat timing group end, i.e., all phase timing groups in one beat timing group correspond to the subtask end signal of 1, the result of performing the and operation is 1, and may set the task end signal of the task to 1, otherwise, the task end signal of the task is 0.
Referring to fig. 6a and 6b together, as shown in fig. 6a and 6b, each functional core may send an operation end signal to the control module (or the control module may obtain the operation end signal from each functional core), when the operation end signal of each functional core in the phase timing group is 1, after performing the phase operation, the control module completes the operation task of the phase timing group according to obtaining the sub-task end signal as 1, if each sub-task (phase timing group) of the current task (beat timing group) completes the operation, the sub-task end signal of each sub-task is 1, and stores the sub-task end signal in the sub-task end signal register, the control module may obtain a storage value in the sub-task end signal, and perform the phase operation, and may obtain the phase operation result as 1, and may determine that the current task is completed, and set the task end register corresponding to the current task as 1, which indicates that the current task is completed.
In one example, the register module 70 may also include a first select register (S_sel [0:m-1, as shown in FIG. 6b][0:y-1]) The first selection register is configured as a two-dimensional register with m x y bits, the first dimension represents the current functional core number, the second dimension represents the task number to which the current functional core belongs, wherein m and y are positive integers, and y=log 2 s, the control module may configure the first selection register such that the corresponding first trigger signal s_ck (0:s-1) is output to the corresponding functional core through the multiplexer.
In one example, as shown in fig. 6b, if the current task completes the operation (the value corresponding to the task end signal register step_grp_finish is 1), and the current task is not the last task, the next beat period is triggered, the first trigger signal corresponding to the execution period of the next task is generated, and each functional core freely selects any one of the first trigger signals as its own first trigger signal according to the configuration of the first selection register s_sel, or the control module sends any one of the first trigger signals s_ck (0:s-1) to any one of the functional cores according to the configuration of the first selection register s_sel.
In one example, the register module 70 may also include a second select register (as shown in FIG. 6a, P_sel [0:m-1 ]][0:x-1]) The second selection register is configured as a two-dimensional register with a size of m x bits, the first dimension representing the number of the functional core and the second dimension representing the subtask number of the current functional core, wherein x=log 2 n, the control module may configure the second selection register such that the corresponding second trigger signal p_ck (0: n-1) is output to the corresponding functional core through the multiplexer.
In one example, as shown in fig. 6a, if the current subtask completes the operation (the value corresponding to the subtask end signal register phase_grp_finish is 1), and the functional cores corresponding to the second trigger signals all end the execution of the current subtasks, the next phase period is triggered, the second trigger signals corresponding to the next subtasks are generated, each functional core freely selects any one of the second trigger signals as its own second trigger signal according to the configuration of the second selection register p_sel, or the control module sends any one of the second trigger signals p_ck (0: n-1) to any one of the functional cores according to the configuration of the first selection register p_sel.
According to the embodiment of the disclosure, the first trigger signal and the second trigger signal are arbitrarily selected by setting each functional core, so that the function expansion of a subsequent processor can be realized, and the adaptability and the flexibility are improved.
In one possible implementation, the control module may also be used to,
releasing the functional core in the processor corresponding to the first trigger signal under the condition that a preset condition is met, wherein the preset condition comprises:
the current task is the last task and the current task is finished executing; or alternatively
When execution of the current task is forcibly ended.
For example, if the current task is the last link of a neural network operation task, after the current task finishes executing, the whole neural network operation task may release the first trigger signal corresponding to the set of functional cores in the processor, that is, the set of functional cores may become idle for other tasks, and after the execution of the current task is forcedly ended, since the ending execution of the current task is forcedly ended after timeout, the ending execution of the whole neural network operation task may be caused, or the first trigger signal corresponding to the set of functional cores in the processor may be released. After finishing executing the current task, the reset and zero clearing operation can be performed on the corresponding first timing clock and each second timing clock.
By releasing the first trigger signal corresponding to the function core set in the processor after the execution of the task is finished, when only a few tasks are executed, the unselected function cores are in a dormant state, so that the power consumption is reduced, and meanwhile, the function cores in the idle state can be selected by other tasks by timely releasing the function cores, so that the running efficiency is improved, the waiting time of other tasks is reduced, and the execution speed is accelerated.
The control device of the embodiment of the disclosure can support parallel or mixed operation of a plurality of on-chip asynchronous network applications: different step triggers can correspondingly deploy different network applications, and the different network applications can run independently, so that the power consumption can be reduced, when only a few network applications execute, the core which is not selected is in a dormant state, the power consumption is reduced, and the running time can be reduced: for a network application, the core with similar operation tasks inside is divided into a phase sequence group, so that the execution speed is increased.
The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (9)

1. A control apparatus, characterized in that the apparatus comprises:
the first trigger module is used for generating one or more first trigger signals, wherein each first trigger signal corresponds to each task;
the second trigger module is electrically connected with the first trigger module and is used for generating one or more second trigger signals according to the first trigger signals, wherein the second trigger signals correspond to the subtasks of the tasks;
the multiplexer is electrically connected with the first trigger module and the second trigger module;
the control module is electrically connected with the multiplexer and used for controlling the multiplexer to transmit any one of the one or more first trigger signals and any one of the one or more second trigger signals to one or more functional cores in the processor so that the one or more functional cores execute the subtasks of the tasks according to the received first trigger signals and the received second trigger signals;
the device also comprises a first timing module electrically connected with the first trigger module, wherein the first timing module comprises a first timing clock, and the first timing module is used for starting the first timing clock when receiving the first trigger signal so as to time the execution period of the current task;
The first triggering module is further configured to determine that a condition for triggering an execution period of a next task is met and generate a first triggering signal corresponding to the execution period of the next task when the first timing clock reaches a first threshold, all the subtasks of the current task are completely executed, and the current task is not the last task.
2. The apparatus of claim 1, wherein the device comprises a plurality of sensors,
the first triggering module is further configured to generate a forced ending signal when the first timing clock reaches a third threshold, where the forced ending signal is used to forcibly end execution of each current subtask in the current task, so as to forcibly end execution of the current task;
the control module is further configured to transmit the forced ending signal to each functional core of the current task using the multiplexer.
3. The apparatus of claim 1, wherein the device comprises a plurality of sensors,
the device also comprises a second timing module electrically connected with the second trigger module, the second timing module comprises one or more second timing clocks, the second timing module is used for starting the one or more second timing clocks when receiving the second trigger signal so as to time the execution period of each subtask of the current task,
The second triggering module is further configured to determine that a condition for triggering an execution period of a next sub-task of each current sub-task in the current task is met when the second timing clock reaches a second threshold and the function cores corresponding to the second triggering signals all end execution of each current sub-task, and generate the second triggering signals corresponding to each next sub-task.
4. The apparatus of claim 1, wherein the device comprises a plurality of sensors,
the control module is further used for receiving operation ending signals output by each functional core corresponding to the second trigger signal, and generating subtask ending signals when each functional core outputs the operation ending signals so as to determine that the functional core corresponding to the second trigger signal totally ends the execution of the current subtask;
the apparatus further comprises:
and the first storage module is electrically connected with the control module and used for storing the subtask ending signal.
5. The apparatus of claim 4, wherein the device comprises a plurality of sensors,
the control module is further used for generating a task ending signal under the condition that all subtask ending signals of all subtasks of the current task are stored in the first storage module so as to determine that all subtasks of the current task corresponding to the first trigger signal are ended to be executed;
The apparatus further comprises:
and the second storage module is electrically connected with the control module and used for storing the task ending signal.
6. The apparatus of claim 1, wherein the control module is further configured to assign functional cores to each task, sub-tasks of each task, and number functional cores in the processor, to number a first set of functional cores assigned to each task, and to number a second set of functional cores corresponding to each sub-task of each task.
7. The apparatus of claim 1, wherein the apparatus comprises a plurality of phase group registers, a first select register, a functional core register, a second select register, wherein,
the phase group register is configured as a two-dimensional register with the size of s x n bits, the first dimension represents the current task number, the second dimension represents the subtask number included in the current task, and s and n are both positive integers;
the first selection register is configured as a two-dimensional register with m x y bits, the first dimension represents the current functional core number, the second dimension represents the task number to which the current functional core belongs, wherein m and y are positive integers, and y=log 2 s；
The functional core register is configured as a two-dimensional register with the size of n x m bits, wherein the first dimension represents the subtask number, and the second dimension represents the functional core included in the subtask;
the second selection register is configured as a two-dimensional register with m x bits, the first dimension represents the number of the functional core, and the second dimension represents the subtask number of the current functional core, wherein x=log 2 n。
8. The apparatus of claim 1 or 2, wherein the control module is further configured to,
releasing the functional core in the processor corresponding to the first trigger signal under the condition that a preset condition is met, wherein the preset condition comprises:
the current task is the last task and the current task is finished executing; or alternatively
When execution of the current task is forcibly ended.
9. A brain-like computing system, characterized in that the system comprises a control device according to any one of claims 1-8.
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