CN112416475A

CN112416475A - Triggering method

Info

Publication number: CN112416475A
Application number: CN202011313166.0A
Authority: CN
Inventors: 裴京; 施路平; 王冠睿; 马骋; 徐海峥
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2020-11-20
Filing date: 2020-11-20
Publication date: 2021-02-26
Also published as: WO2022104989A1

Abstract

The present disclosure relates to a triggering method, the method comprising: receiving a first trigger signal corresponding to an execution cycle of a current task, wherein the first trigger signal corresponds to a functional core set in a processor, and generating one or more second trigger signals according to the first trigger signal; and controlling the functional cores corresponding to the second trigger signals in the functional core set to execute the subtasks of the current task according to the one or more second trigger signals. According to the embodiment of the disclosure, parallel or mixed operation of a plurality of asynchronous tasks can be supported, and meanwhile, by means of a two-stage trigger mechanism, independent tasks can be segmented, execution speed is increased, operation time is reduced, performance of a chip is improved, and unselected functional cores can be in a dormant state, so that power consumption is reduced.

Description

Triggering method

Technical Field

The present disclosure relates to the field of computing devices, and in particular, to a triggering method.

Background

The explosive development of large data information network core intelligent mobile devices generates massive unstructured information, accompanied by a rapid increase in the energy-efficient processing demand for such information. The traditional von Neumann architecture chip adopts a working mode of bus communication, synchronization, serial and concentration, the density is increased according to Moore's law, the micro-scale is expected to reach the physical limit within 10 to 15 years in the future, and the development is bound to be fundamentally limited.

The structure is different from the traditional computer processing mode, and has great advantages when processing some non-formalized problems through distributed storage and parallel cooperative processing of information. The traditional triggering mechanism of the many-core neuromorphic chip architecture has great limitation and cannot perform independent task division.

Disclosure of Invention

In view of the above, the present disclosure provides a triggering method.

According to an aspect of the present disclosure, there is provided a triggering method, wherein the method includes:

receiving a first trigger signal corresponding to an execution cycle of a current task, wherein the first trigger signal corresponds to a functional core set in a processor, and generating one or more second trigger signals according to the first trigger signal;

and controlling the functional cores corresponding to the second trigger signals in the functional core set to execute the subtasks of the current task according to the one or more second trigger signals.

In one possible implementation, the method further includes:

when the first trigger signal is received, starting a first timing clock, wherein the first timing clock is used for timing the execution cycle of the current task;

and after the first timing clock reaches a first threshold value, judging whether a condition for triggering the execution period of the next task is met.

In one possible implementation, the method further includes:

when the one or more second trigger signals are received, starting one or more second timing clocks, wherein the one or more second timing clocks are respectively used for timing the execution cycle of each current subtask;

and after the second timing clock reaches a second threshold value, judging whether a condition for triggering an execution cycle of a next subtask of each current subtask in the current task is met.

In one possible implementation, the method further includes:

and generating a forced ending signal when the first timing clock reaches a third threshold value, wherein the forced ending signal is used for forcibly ending the execution of each current subtask in the current task so as to forcibly end the execution of the current task.

In one possible implementation, the method further includes:

receiving a first end clock number corresponding to the first trigger signal, where the first end clock number is used to determine the first threshold.

In a possible implementation manner, after the first clock reaches the first threshold, determining whether a condition for triggering an execution cycle of the next task is satisfied includes:

after the first timing clock reaches the first threshold, determining that a condition for triggering an execution period of the next task is met under the condition that all subtasks of the current task are completely executed and the current task is not the last task, and generating a first trigger signal corresponding to the execution period of the next task.

In one possible implementation, the method further includes:

receiving one or more second ending clock numbers corresponding to the one or more second trigger signals, where the second ending clock numbers are used to determine one or more second thresholds.

In a possible implementation manner, after the second timing clock reaches the second threshold, determining whether a condition for triggering an execution cycle of the next subtask of each current subtask in the current task is satisfied includes:

after the second timing clock reaches the second threshold, determining that a condition for triggering an execution cycle of the next subtask of each current subtask in the current task is satisfied under the condition that the functional cores corresponding to the second trigger signals all end execution of each current subtask, and generating the second trigger signals corresponding to each next subtask.

In one possible implementation, the method further includes:

releasing a function core set in the processor corresponding to the first trigger signal under the condition that a preset condition is met, wherein the preset condition comprises:

the current task is the last task and is executed after the current task is finished; or

After the execution of the current task is forcibly ended.

According to the method and the device, one or more second trigger signals are generated according to the received first trigger signal of the current task, and the corresponding functional cores are controlled to execute each subtask of the current task according to the one or more second trigger signals.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

Fig. 1 shows a packet schematic of a triggering method according to an embodiment of the present disclosure;

FIG. 2 shows a flow diagram of a triggering method according to an embodiment of the present disclosure;

FIG. 3 shows a flow diagram of a triggering method according to an embodiment of the present disclosure;

FIG. 4 illustrates a timing diagram of a first level of triggering of a triggering method according to an embodiment of the disclosure;

FIG. 5 shows a timing diagram of a second level of triggering of a triggering method according to an embodiment of the disclosure.

FIG. 6 illustrates an interface module architecture diagram of a trigger system according to an embodiment of the disclosure;

Detailed Description

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.

With the continuous development of the technical field of neural networks, massive unstructured information is generated, and the demand for high-energy-efficiency processing of the information is increased sharply. The many-core neuromorphic chip architecture is different from a traditional computer processing mode, and has great advantages in processing some non-formalized problems through distributed storage and parallel cooperative processing of information. However, the trigger mechanism in the conventional chip cannot perform independent network task division when multiple networks are executed, and has great limitation.

In order to further improve performance, the embodiments of the present disclosure provide a trigger device, where a function core is triggered and controlled at two levels, a first level of trigger may divide different networks or applications, and a second level of trigger may divide similar computation tasks in the networks or applications and allocate the tasks to perform operations in the function core, so as to effectively improve performance of a chip, and have a high application value.

The apparatus of the embodiment of the disclosure can be applied to a many-core neuromorphic chip, and fig. 1 shows a grouping schematic diagram of a triggering apparatus according to the embodiment of the disclosure. Step _ grp and Phase _ grp may respectively represent corresponding sets of function cores, step _ grp0, step _ grp1, and step _ grp2 represent sets of function cores corresponding to the respective first trigger signals, Phase _ grp0, Phase _ grp1, Phase _ grp2, Phase _ grp3, Phase _ grp4, and Phase _ grp5 represent sets of function cores corresponding to the respective second trigger signals, and C00 to C44 represent different function cores. For example, Phase _ grp0 corresponds to a set of function cores including function cores C00, C01, C10, C11, Phase _ grp1, Phase _ grp2, Phase _ grp3, Phase _ grp4, Phase _ grp5, as described in relation to the function cores, Phase _ grp0 corresponds to a set of three function cores Phase _ grp0, Phase _ grp1, Phase _ grp2, as described in relation to Phase _ grp3, Phase _ grp4, Phase _ grp5, as shown, a Phase _ grp may be included in one or more Phase _ grps, a function core may be included in one or more Phase _ grps (as in Phase 5, Phase _ grp 24, may be included in the same Phase _ grp1, may be used to perform the same task under the same network, or similar tasks, and a function core may be included in the same network under the same task processing task _ grp3, in one possible implementation, the set of functional cores may be re-partitioned after a network task or application task is completed.

Fig. 2 shows a flow chart of a triggering method according to an embodiment of the present disclosure. As shown in fig. 2, the method includes:

step S101, receiving a first trigger signal corresponding to an execution cycle of a current task, wherein the first trigger signal corresponds to a functional core set in a processor, and generating one or more second trigger signals according to the first trigger signal;

step S102, controlling, according to the one or more second trigger signals, the functional core corresponding to each second trigger signal in the functional core set to execute each subtask of the current task.

According to the embodiment of the disclosure, one or more second trigger signals are generated by receiving a first trigger signal of a current task, and corresponding functional cores are controlled to execute each subtask of the current task according to the one or more second trigger signals, so that parallel or mixed operation of a plurality of asynchronous tasks can be supported, and meanwhile, the current task is divided into the subtasks, so that the functional cores with similar tasks inside can be executed simultaneously, and thus, by a secondary trigger mechanism, the division of independent tasks can be realized, the execution speed is accelerated, the running time is reduced, and the performance of a chip is improved; the corresponding functional cores are controlled through the trigger signals, and the functional cores which are not selected can be in a dormant state, so that power consumption is reduced. The task may be a network or an application task, such as a task for performing neural network operations (for example, a VGG network or a ResNet50 network), or a task for running application software.

In one possible implementation, the method may be applied to a system on chip including a plurality of functional cores (or referred to as processor cores), such as shown in fig. 1. The method may be implemented by a component for triggering in a system on chip (see, e.g., fig. 6, infra). Each first trigger signal corresponds to a part of the functional cores in the system on chip, namely a set of functional cores, and the first trigger signal can trigger the functional cores to work and execute various subtasks by generating second trigger signals, and each second trigger signal can correspond to one or more of the part of the functional cores. The corresponding relation between the first trigger signal, the second trigger signal and the functional core can be manually or automatically set according to requirements. The correspondence may be released after a complete task is performed (e.g., a neural network operation is completed) for subsequent reconfiguration. In a possible implementation manner, the corresponding relationship between the first trigger signal, the second trigger signal, and the functional core may be reset before starting a complete task, specifically, if there are a sufficient number of idle functional cores required, the setting may be completed and a complete task may be started to be executed, if there are no idle functional cores, the functional core may be released after the other tasks are finished being executed, and after the number of idle functional cores meets the requirement, the setting may be completed and a complete task may be started to be executed. Because the same functional core can respectively correspond to different second trigger signals or first trigger signals, the multiplexing signals can be set for the functional core which can be multiplexed after the setting is finished, so that the functional core can be used as an idle functional core to participate in operation when the functional core is set by other tasks, the functional core is fully utilized, and the performance and the utilization rate of the system are improved.

In a possible implementation manner, within the execution period of the current task, the execution period of one or more subtasks may be included, that is, between two first trigger signals, a second trigger signal of multiple periods may occur. Taking the neural network operation task as an example, for a neural network with a small operation amount, the first trigger signal may complete one operation (current task) of the entire neural network in one execution cycle, where the second trigger signal may complete one link of the neural network operation in each cycle, for example, an operation of one network layer, and the functional core corresponding to each second trigger signal may perform a similar operation (subtask), for example, addition or multiplication, in each link, and each functional core may be configured to perform a corresponding primitive operation. For example, still taking fig. 1 as an example, the four functional cores C00, C01, C10, and C11 corresponding to Phase _ grp0 may respectively perform addition, the 6 functional cores C02, C03, C12, C13, C22, and C23 corresponding to Phase _ grp1 may respectively perform multiplication, and the like, which is not limited by the disclosure. For a neural network with a large computation amount, the first trigger signal may complete one link in one computation of the entire neural network within one execution cycle, for example, computation of one network layer (current task), that is, the current task may also be a subtask of a higher-level task (entire neural network computation task). In a possible implementation manner, after a link of the neural network operation task is completed, the corresponding relationship between the first trigger signal and the functional core and the second trigger signal and the functional core may be used, and after the whole neural network task is completed, the functional core is released.

In a possible implementation manner, the method further includes, when the first trigger signal is received, starting a first timing clock, where the first timing clock is used to time an execution cycle of the current task; and after the first timing clock reaches a first threshold value, judging whether a condition for triggering the execution period of the next task is met.

When the condition for triggering the execution cycle of the next task is satisfied, the execution cycle of the next task is triggered, that is, the next task starts to be executed, and the execution mode of the next task may be the same as that of the current task.

The first timing clock starts timing when receiving the first trigger signal, and the first timing clock may time once every reference clock cycle and determine whether the first threshold is reached. The received first trigger signal here includes a first trigger signal received from the outside and also includes a first trigger signal automatically generated when the following condition is satisfied, and the first clock may be restarted from 0 every time a new first trigger signal is generated.

By comparing the first timing clock with the first threshold value, whether the condition for triggering the execution period of the next task is met or not is judged, and the control on the execution period of the current task can be realized, so that different tasks can be better scheduled, the running time is reduced, and the execution efficiency is improved.

In one possible implementation, the method further includes: when the one or more second trigger signals are received, starting one or more second timing clocks, wherein the one or more second timing clocks are respectively used for timing the execution cycle of each current subtask; and after the second timing clock reaches a second threshold value, judging whether a condition for triggering an execution cycle of a next subtask of each current subtask in the current task is met.

Under the condition that the condition of triggering the execution period of the next subtask of each current subtask is met, triggering the execution period of the next task of each current subtask, namely starting to execute each next subtask, wherein the execution mode of the next subtask can be the same as that of the current subtask, and so on until all subtasks of the current task are executed completely or a forced end signal is received to finish the execution of the subtask.

The second timing clock starts timing when receiving a second trigger signal, and the second timing clock can judge whether a second threshold value is reached or not when one clock count passes; each second trigger signal may correspond to a second timing clock, and different second timing clocks may correspond to different second thresholds, for example, after a functional core set corresponding to one second trigger signal receives the second trigger signal, the second timing clock corresponding to the functional core set may be started and compared with the corresponding second threshold; the execution cycles of the functional core sets may be the same or different. The received second trigger signal here includes a second trigger signal generated based on the first trigger signal, and also includes a second trigger signal automatically generated when the following condition is satisfied, and the corresponding second clock may be re-clocked from 0 each time a new second trigger signal is generated.

By comparing the second timing clock with the second threshold value, whether the condition for triggering the execution period of the next subtask of each current subtask is met or not is judged, and the control of the execution period of each subtask can be realized, so that each subtask can be better scheduled.

In one possible implementation, the method further includes: receiving a first end clock number corresponding to the first trigger signal, where the first end clock number is used to determine the first threshold.

For example, if the first end clock count is 100, the first threshold is 100 reference clock cycles, and the first threshold is reached when the first clock counts to the 100 th reference clock cycle.

The value of the first end clock number may be preset, and the functional core sets corresponding to different first trigger signals may correspond to different first end clock numbers.

By determining the first threshold according to the preset first end clock number, the advance control and deployment of the execution periods of different network applications can be realized, so that asynchronous independent operation of different tasks is realized, and the operation speed is increased.

In one possible implementation, the method further includes: receiving one or more second ending clock numbers corresponding to the one or more second trigger signals, where the second ending clock numbers are used to determine one or more second thresholds.

For example, if the second end clock count is 20, the second threshold is 20 reference clock cycles, and the second threshold is reached when the second clock count reaches the 20 th reference clock cycle.

The value of the second ending clock number may be preset, and the functional core sets corresponding to different second trigger signals may correspond to the corresponding second ending clock numbers.

The second threshold value is determined according to the preset second ending clock number, so that the execution periods of different subtasks can be controlled and deployed in advance, asynchronous independent operation of the different subtasks is realized, and the operation speed is accelerated.

The first end clock number may be a variable value that changes according to different tasks, and is received each time the execution cycle of the current task is triggered, or may be a preset fixed value, and only needs to be received once, and can be reused subsequently; the second ending clock number may be a variable value that changes according to different subtasks, and may be received each time the execution period of the subtask under the current task is triggered, or may be a preset fixed value, and may only need to be received once, and may be reused subsequently.

In one possible implementation, the method further includes: releasing a function core set in the processor corresponding to the first trigger signal under the condition that a preset condition is met, wherein the preset condition comprises: the current task is the last task and is executed after the current task is finished; or after the execution of the current task is forcibly ended.

For example, if the current task is the last link of a neural network operation task, after the current task is finished executing, the entire neural network operation task is completed, the first trigger signal corresponding to the set of functional cores in the processor may be released, that is, the set of functional cores may become an idle state for use by other tasks, and after the current task is finished forcibly, since the end of the current task is finished forcibly after the timeout, the entire neural network operation task may be finished executing, and the first trigger signal corresponding to the set of functional cores in the processor may also be released. After the current task is finished, resetting and clearing operations can be carried out on the corresponding first timing clock and each second timing clock.

The first trigger signal is released after the execution of the task is finished, the functional core set corresponding to the processor is enabled, the functional cores which are not selected can be in the dormant state when only a few tasks are executed, power consumption is reduced, meanwhile, the functional cores which are not selected in the idle state can be selected by other tasks by timely releasing the functional cores, operation efficiency is improved, waiting time of other tasks is reduced, and execution speed is accelerated.

The conditions for ending the execution of the current task and triggering the execution cycle of the next task or next subtask are explained below by some examples.

In one possible implementation, the method further includes: and generating a forced ending signal when the first timing clock reaches a third threshold value, wherein the forced ending signal is used for forcibly ending the execution of each current subtask in the current task so as to forcibly end the execution of the current task.

The third threshold may be greater than the first threshold, may be a variable value that changes according to different tasks, and is received each time the execution cycle of the current task is triggered, or may be a preset fixed value, and only needs to be received once, and may be reused subsequently.

After the forced termination signal is generated, the forced termination signal may be sent to the function core set corresponding to the first trigger signal and corresponding to each second trigger signal, so as to terminate the execution of each current sub-task in the current task, thereby forcibly terminating the execution of the current task.

Specifically, when the current task reaches the third threshold and is not yet executed, the current task may be jammed due to a program error, for example, for a certain link in a certain neural network task, the estimated number of clocks required to execute the task of the link is 500, so that, when the first timing clock reaches 1000 clocks and the task of the link is not yet executed, the program error is likely to occur, and the dead loop cannot be ended (which is a pathological state) and needs to be forcibly ended, so that in this case, the third threshold may be set to 1000 clocks, and when the third threshold is reached, the task is still not ended, and is forcibly ended. If the current task is a certain subtask of the previous-level task, the whole previous-level task can be forcibly ended, and after the execution of the whole task is forcibly ended, the function core set corresponding to the first trigger signal can be released, so that unnecessary function core resources are prevented from being occupied.

The maximum clock number executed by the current task is controlled by a mechanism for realizing forced termination of the current task, so that dead cycle that the task cannot be terminated due to program errors and the like can be avoided, the possibility of wasting a large amount of unnecessary functional core resources is avoided, the power consumption is further reduced, and the running efficiency is improved.

In a possible implementation manner, after the first clock reaches the first threshold, determining whether a condition for triggering an execution cycle of the next task is satisfied includes: after the first timing clock reaches the first threshold, determining that a condition for triggering an execution period of the next task is met under the condition that all subtasks of the current task are completely executed and the current task is not the last task, and generating a first trigger signal corresponding to the execution period of the next task.

For example, when the first timing clock reaches the first threshold and the functional cores corresponding to the second trigger signals corresponding to the first trigger signal all complete execution of all their subtasks, if the current task is not the last task, the execution cycle of the next task may be triggered.

And when all subtasks of the current task are finished and the current task is the last task, finishing the execution of the task and releasing the corresponding function core set.

All subtasks of the current task are completely executed, namely the current task is completely executed, and by judging whether all subtasks of the current task are completely executed or not and triggering the execution period of the next task when all subtasks are completely executed, the idle of the functional cores can be reduced as much as possible, each functional core is utilized to the greatest extent, and the execution efficiency is improved.

In a possible implementation manner, after the second timing clock reaches the second threshold, determining whether a condition for triggering an execution cycle of the next subtask of each current subtask in the current task is satisfied includes: after the second timing clock reaches the second threshold, determining that a condition for triggering an execution cycle of the next subtask of each current subtask in the current task is satisfied under the condition that the functional cores corresponding to the second trigger signals all end execution of each current subtask, and generating the second trigger signals corresponding to each next subtask.

Specifically, the method for triggering the functional core set corresponding to the second trigger signal may include: the method comprises the steps of generating a first trigger signal according to a first sub-task of a functional core set, generating a second trigger signal according to the first trigger signal before the first sub-task of the functional core set starts to execute, and triggering according to the second trigger signal which is automatically generated after the first sub-task of the functional core set starts to execute.

By means of the method, under the condition that the functional core set corresponding to the current subtask does not finish execution completely, the execution cycle of the next subtask is triggered after the functional core set finishes execution completely, the possibility that the current subtask starts the next subtask after the current subtask is not finished and the current task card cannot continue in a certain subtask can be prevented, error reporting is prevented, deployment and scheduling of each task can be executed smoothly, and corresponding performance is improved.

Fig. 3 shows a flowchart of a triggering method according to an embodiment of the present disclosure, and as shown in fig. 3, the specific steps include:

and S010, receiving a first trigger signal corresponding to the execution cycle of the current task.

If the first trigger signal is received from the outside, the current task can be a new task, and the new task can be a first subtask of a previous task or a task which can be completed within an execution period of the first trigger signal; if the first trigger signal is automatically generated, the current task may be a subtask other than the first subtask among the previous task.

After receiving the first trigger signal, the first timing clock is cleared and timing is restarted.

And step S020, generating one or more second trigger signals according to the first trigger signal.

Step S030, controlling, according to the one or more second trigger signals, the functional core corresponding to each second trigger signal in the functional core set to execute each subtask of the current task.

And step S040, judging that the second timing clock reaches the second threshold value and the corresponding functional cores all finish the execution of the current subtask, if so, executing step S050, otherwise, continuing to execute step S040.

Here, the determination is performed by taking a certain second-level trigger corresponding function core set as an example (the function core set may trigger one or more corresponding subtasks through a second trigger signal), determining whether a second timing clock corresponding to the second trigger signal received by the function core set reaches a second threshold and whether the corresponding function core completely ends execution of its current subtask, and the same applies to determination of the remaining second trigger signals.

It should be noted that the second timing clock may re-time when receiving the second trigger signal corresponding to the new subtask, and there may be a redundant task duration between the subtasks due to the timeout of a certain subtask, so that the first timing clock may have already reached the first threshold when the second timing clock has not reached the second threshold. That is, it may occur that the first timing clock reaches the first threshold value, and all of the subtasks do not finish executing.

And step S050, judging whether the current subtask is the last subtask of the function core set corresponding to the second trigger signal, if so, outputting a signal indicating that all subtasks finish execution for judgment in step S070, and otherwise, executing step S060.

It should be noted that, since the set of functional cores in the second-level trigger may trigger the execution cycle of one or more subtasks by one or more second trigger signals, and the second-level trigger includes one or more sets of functional cores, even if the subtask is the last subtask of the set of functional cores, the subtask is not meant to be the last subtask of the current task.

Step S060, triggering the execution cycle of the next subtask of each current subtask in the current task.

Specifically, after triggering the execution period of the next subtask of each current subtask in the current task, the process returns to the step S040.

And step S070, judging whether the first timing clock reaches a first threshold value, if so, executing step S080, otherwise, continuing to execute step S070.

In a possible implementation manner, the first threshold may be determined according to a first end clock number corresponding to the first trigger signal.

Specifically, if the first timing clock does not reach the first threshold, the first timing clock continues to time and continuously determines whether the first timing clock reaches the first threshold

And step S080, judging whether all subtasks of the current task are completely executed, if so, executing step S090, otherwise, executing step S110.

Step S090, determining whether the current task is the last task, if yes, executing step S130, otherwise executing step S100.

Step S100, triggering an execution cycle of a task next to the current task.

Specifically, if the current task is not the last task, the execution cycle of the next task to the current task may be triggered by the automatically generated first trigger signal, where the current task and the next task may be regarded as subtasks of the previous-level task.

And step S110, judging whether the first timing clock reaches a forced ending clock, if so, executing step S120, otherwise, returning to execute step S080.

Specifically, under the condition that all subtasks of the current task are not completely finished and executed, whether the first timing clock reaches a forced finishing clock is judged, if yes, a program error condition exists, the task needs to be finished forcibly, otherwise, the execution is returned to wait for all subtasks to be completely finished, or when the forced finishing clock is reached before all subtasks are finished, the subsequent steps are carried out.

In step S120, a forced termination signal is generated.

Specifically, after the first timing clock reaches the forced end clock, a forced end signal is generated, and may be sent to the function core set corresponding to the first trigger signal and corresponding to each second trigger signal, so as to end execution of each current sub-task in the current task, thereby forcibly ending execution of the current task.

Step S130, ending the work and releasing the functional core set corresponding to the first trigger signal.

When all subtasks of the current task are completely executed and the current task is the last task, the current task can be a subtask of a previous-level task which needs a plurality of execution cycles, or can be a complete task which can be completed only by one execution cycle, and no matter what kind of situation, the previous-level task or the complete task is completely executed, and at the moment, the corresponding functional core set can be released for other tasks to use; and when the first timing clock reaches a forced ending clock, and the executed current task is forcibly ended, whether the current task is the last subtask of the current task or not, the execution of the previous-stage task or the complete task can be ended, and the corresponding functional core is released for other tasks to use.

FIG. 4 is a timing diagram illustrating a first stage of triggering of a triggering device according to an embodiment of the disclosure, where clk represents a reference clock and clk 1 represents a reference clock number; step group0 and step group1 represent the sets of functional cores corresponding to the first trigger signals, and different first trigger signals may be used to trigger the corresponding sets of functional cores to perform different tasks, for example, one first trigger signal is used to perform a calculation task of a neural network, and another first trigger signal is used to perform a calculation task of another neural network, or a running task of an application software, etc. The set of functional cores corresponding to the first trigger signal may be referred to as a beat timing group; step _ ck0 represents a first trigger signal corresponding to step group0, which may be referred to as a beat trigger signal corresponding to step group 0; step _ ck0 is set to 1 to indicate that a beat trigger signal (which may be a beat trigger signal from an external input or a beat trigger signal automatically generated when a condition is satisfied, the same applies below) is received; step _ ck1 represents a beat trigger signal corresponding to step group1, and step _ ck1 is set to 1 to represent that a beat trigger signal is received; p _ grp0_ ck and p _ grp1_ ck respectively represent two second trigger signals corresponding to step group0, the second trigger signals may be referred to as phase trigger signals, a functional core set corresponding to the second trigger signals may be referred to as a phase time sequence group, and setting a phase trigger signal to 1 indicates that one phase trigger signal is received (the phase trigger signal may be generated according to a beat trigger signal, or may be automatically generated when a condition is met, the same applies below); p _ grp2_ ck, p _ grp3_ ck and p _ grp4_ ck respectively represent three phase trigger signals corresponding to step group1, and the setting of the phase trigger signal to 1 represents that one phase trigger signal is received; s _ group 0_ finish represents a signal that the corresponding functional core set of step group0 finishes executing all, that is, a signal that all subtasks of the current task (i.e., the task corresponding to step group 0) finish executing all, which may be referred to as a step group0 beat end signal, and the beat end signal is set to 1 when all phase sequence groups finish executing corresponding all subtasks within step group0, otherwise set to 0; s _ group 1_ finish represents a signal that the corresponding set of functional cores of step group1 all finish executing, which may be referred to as a beat finish signal of step group 1; all the phase sequence groups in step group1 are set to 1 when the execution of all the corresponding subtasks is finished, otherwise, set to 0.

As shown in fig. 4, in one possible implementation, for step group0, when step _ ck0 is received, p _ grp0_ ck and p _ grp1_ ck are triggered, all phase groups in step group0 group are triggered at the same time, a new phase group work cycle (which may be called an execution cycle) is started, wherein the work cycles of the phase groups of different phase groups may be the same or different, a beat clock (which may be called a first clock) may be started after receiving a beat trigger signal, when the number of clocks of the beat clock equals the number of beat end clocks, it may be checked whether all phase groups in the beat group end work, it may also be checked whether a signal of s _ grp0_ finish set 1 is received, if so (at this time s _ grp0_ finish set 1), a next clock cycle of the phase group work cycle (at this time, step _ ck0 is set to 1 automatically) or all beat core functions in the beat group are released and ended, otherwise, after the work is completely finished, the next working period of the beat time sequence group is started or the work is finished, if the work is not completely finished when the forced finishing clock is reached, a forced finishing signal is generated, the execution of all the phase time sequence groups under the beat time sequence group is forcibly finished, and the related first timing clock and each second timing clock are reset and cleared. The same applies to step _ ck 1.

It should be noted that the number of working cycle clocks of the phase timing group under the same beat timing group may be the same or different; the phase sequence groups belonging to the same beat sequence group are synchronous when receiving the phase trigger signal and triggering the corresponding first subtask, the automatic triggering of the subsequent subtasks after the first subtask is finished can be asynchronous, and the phase sequence groups belonging to different beat sequence groups can be asynchronously triggered. The different sets of beat timings may also be asynchronous.

Fig. 5 shows a timing diagram of the second stage triggering of the triggering device according to the embodiment of the disclosure, and fig. 5 describes the operation timing of step group0 in fig. 4 in more detail. Wherein clk represents a reference clock, and 1 to clk represents 1 reference clock number; s _ ck represents a first trigger signal which can be called a beat trigger signal, phase group0 and 1 represent functional core sets corresponding to different second trigger signals, and the functional core set corresponding to the second trigger signals can be called a phase timing group; setting s _ ck to 1 represents that a beat trigger signal is received; p _ grp0_ ck represents a second trigger signal corresponding to phase group0, and the second trigger signal may be referred to as a phase trigger signal; p _ grp0_ ck is set to 1 to indicate that a corresponding phase trigger signal is received; p _ grp1_ ck represents a phase trigger signal corresponding to phase group 1; p _ grp1_ ck is set to 1 to indicate that a corresponding phase trigger signal is received; core0, core1, and core2 represent three functional cores under phase group0, respectively, and core3 and core4 represent two functional cores under phase group1, respectively; p _ grp0_ finish represents a signal that the functional cores of phase group0 all finish executing, and may be referred to as phase group0 phase finish signal; if all the functional cores in phase group0 finish executing the operation, 1 is set, otherwise 0 is set, s _ group 1_ finish indicates that all the functional cores in phase group1 finish executing the signal, which may be referred to as a phase group1 phase end signal, and if all the functional cores in phase group1 finish executing the operation, 1 is set, otherwise 0 is set. The phase end signal of the phase timing group corresponding to each phase timing group under the beat timing group can be obtained by taking the phase end signal phase of the phase timing group, that is, the phase of p _ grp0_ finish and the phase of p _ grp1_ finish phase can be taken as s _ grp0_ finish in fig. 5. p0, p1, p2 and p3 respectively indicate that the corresponding functional core is in the corresponding execution operation state.

As shown in fig. 5, in a possible implementation manner, for phase group0, when s _ ck is received, p _ group 0_ ck is triggered synchronously, and all functional cores in a phase group0 group are triggered simultaneously, and core0, core1, and core2 are controlled to start to execute operations, where the time for different functional cores to execute operations may be the same or different, a phase timing clock (may be referred to as a second timing clock) may be started after the functional cores start to operate, when the clock number of the phase timing clock is equal to the phase end clock number, whether all functional cores in the phase group end the current sub-task may be checked, if so, a next phase group working cycle (may be referred to as an execution cycle) is triggered, otherwise, a next phase group working cycle is started after all operations of the current sub-task are finished. If the function cores in the phase sequence group finish executing all the subtasks of the current task, setting p _ grp0_ finish to 1, and when the function cores in the phase sequence group do not finish executing all the subtasks of the current task, continuing executing until the next task is started after finishing all the executing, or receiving a forced ending signal of the beat sequence group and forcibly ending all the current subtasks. The same applies to phase group 1.

It should be noted that the number of clocks for executing operations by each functional core in the same phase time sequence group may be the same or different; functional cores belonging to the same phase timing group are synchronously triggered, and functional cores belonging to different phase timing groups can be asynchronously triggered.

The method described above can be applied to the system shown in fig. 6, and fig. 6 shows an interface schematic diagram of a trigger system according to an embodiment of the present disclosure, where the trigger system is composed of a trigger module 100, the trigger module 100 includes a first trigger module 101 and a second trigger module 102, and the external trigger module 200, the register module 300, and the functional core module 400 are respectively connected to the trigger module 100.

In a possible implementation manner, the external trigger module 200 inputs a first trigger signal to the first trigger module 101, and the first trigger module 101 may generate one or more second trigger signals according to the first trigger signal, and output the one or more second trigger signals to the second trigger module 102 to trigger an execution cycle of a subtask under the current task corresponding to the second trigger signal. The second trigger module 102 receives the one or more second trigger signals, and may output each received second trigger signal to the functional core module 400, where the functional core module includes each functional core, so as to control a functional core set corresponding to each sub-task to start executing work. The first trigger signal may be generated by the external trigger module 200 and output to the first trigger module 101, or may be automatically generated by the first trigger module 101, for example, when the above condition for triggering the execution cycle of the next task is satisfied, the first trigger module 101 may automatically generate the first trigger signal of the execution cycle of the next task; the second trigger signal may be generated by the first trigger module 100 according to the first trigger signal, or may be automatically generated by the second trigger module 102, for example, when the above-mentioned condition for triggering the execution cycle of the next subtask of the current subtasks in the current task is satisfied, the second trigger module 102 may automatically generate the second trigger signal of the execution cycle of the next subtask.

The first end clock number and the forced end clock number may be output to the first trigger module 101 by the register module 300, and values of the first end clock number and the forced end clock number may be preset in the register module 300; the second end clock count may be output by the register module 300 to the second flip-flop module 102, the value of the second end clock count may be preset in the register module 300,

specifically, the first end clock count and the forced end clock count may be variable values that change according to different tasks, and are output to the first trigger module 101 by the register module 300 each time the first trigger module 101 triggers the execution cycle of the current task, or may be preset fixed values, and only need to be output to the first trigger module 101 by the register module 300 once, and may be reused subsequently; the second ending clock number may be a variable value that changes according to different subtasks, and is output to the second trigger module 102 by the register module 300 each time the second trigger module 102 triggers the execution cycle of the subtask in the current task, or may be a preset fixed value, and only needs to be output to the second trigger module 102 by the register module 300 once, and may be reused subsequently.

Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein were chosen in order to best explain the principles of the embodiments, the practical application, or technical improvements to the techniques in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method of triggering, the method comprising:

2. The triggering method of claim 1, further comprising:

3. The triggering method of claim 1, further comprising:

4. The triggering method of claim 2, further comprising:

5. The triggering method of claim 2, further comprising:

6. The method according to claim 2, wherein determining whether a condition for triggering an execution cycle of the next task is satisfied after the first clock reaches the first threshold value comprises:

7. The triggering method of claim 3, further comprising:

8. The method according to claim 3, wherein after the second clock reaches the second threshold, determining whether a condition for triggering an execution cycle of the next subtask among the current subtasks is satisfied includes:

9. The triggering method according to claim 1 or 4, characterized in that the method further comprises:

After the execution of the current task is forcibly ended.