CN112433974A - Server and server mainboard - Google Patents
Server and server mainboard Download PDFInfo
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- CN112433974A CN112433974A CN202011311238.8A CN202011311238A CN112433974A CN 112433974 A CN112433974 A CN 112433974A CN 202011311238 A CN202011311238 A CN 202011311238A CN 112433974 A CN112433974 A CN 112433974A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
Abstract
The application discloses server motherboard includes: a server main board body, a CPU; the CPU is provided with N groups of PCIE interfaces, each group of PCIE interfaces is the link width of X8, and each group of PCIE interfaces is provided with a target interface which corresponds to the group of PCIE interfaces and is used for outputting information which represents the type of a device connected with the PCIE interface to the CPU; the N groups of PCIE interfaces are respectively connected with the N connectors; for any one connector, the connector is allowed to connect with BP, and the connector is allowed to connect with PCIE card of X8, and the connector adjacent to the connector are allowed to connect with PCIE card of X16 together. By applying the scheme of the application, the flexibility of the PCIE link width of the server mainboard is improved, and PCIE devices connected with the CPU can be flexibly configured. The application also provides a server with corresponding effect.
Description
Technical Field
The invention relates to the technical field of computer design, in particular to a server and a server mainboard.
Background
With the continuous development of computer technology, in order to reduce or even get rid of the dependence on processors such as Intel and AMD in China, the development of CPUs and motherboards is more and more emphasized.
However, some current CPU motherboards are simple in design, and Link Width of PCIE is fixed, so that the CPU motherboards cannot be configured automatically and flexibly according to different PCIE devices. For example, fig. 1 is a schematic diagram of a server motherboard design scheme of the current maritime light 7000 edition, and it can be seen that PCIE link width is already fixed during design and development, and an application scenario is limited and not flexible enough.
In summary, how to effectively improve the flexibility of the PCIE link width of the server motherboard is a technical problem that needs to be solved by those skilled in the art at present.
Disclosure of Invention
The invention aims to provide a server and a server mainboard, so as to effectively improve the flexibility of PCIE link width of the server mainboard.
In order to solve the technical problems, the invention provides the following technical scheme:
a server motherboard, comprising:
a server main board body, a CPU;
the CPU is provided with N groups of PCIE interfaces, each group of PCIE interfaces is the link width of X8, and each group of PCIE interfaces is provided with a target interface which corresponds to the group of PCIE interfaces and is used for outputting information which represents the type of a device connected with the PCIE interface to the CPU; n is a positive integer;
the N groups of PCIE interfaces are respectively connected with the N connectors;
for any one connector, the connector is allowed to connect with BP, and the connector is allowed to connect with PCIE card of X8, and the connector adjacent to the connector are allowed to connect with PCIE card of X16 together.
Preferably, each target interface comprises a first GPIO interface and a second GPIO interface;
moreover, for any one target interface, when the first GPIO interface of the target interface is at the first level and the second GPIO interface is at the second level, it indicates that the PCIE interface corresponding to the target interface is connected to the PCIE card of X8 through the connector and the RISER of X8;
for any one target interface, when the first GPIO interface of the target interface is at the first level and the second GPIO interface is at the first level, it indicates that the PCIE interface corresponding to the target interface is connected to the PCIE card of X16 through a connector and a RISER of X16, and another connector connected to the RISER of X16 is adjacent to the connector corresponding to the target interface;
for any target interface, when the first GPIO interface of the target interface is at the second level and the second GPIO interface is at the second level, it indicates that the PCIE interface corresponding to the target interface is connected to the BP through the connector.
Preferably, the first level is a high level, and the second level is a low level.
Preferably, each connector is a slim line type connector.
Preferably, the CPU is a 32-core CPU of the marine light 7000.
Preferably, for any connector, when the connector is connected with the BP, the connector is connected with the NVME hard disk of the 2 block X4 through the BP.
A server comprises the server mainboard of any one of the above-mentioned items.
By applying the technical scheme provided by the embodiment of the invention, the PCIE of the CPU is divided into N groups of PCIE, each group of PCIE interfaces are all the link width of X8, and the N groups of PCIE interfaces are respectively connected with N connectors; for any one connector, the connector is allowed to connect with BP, and the connector is allowed to connect with PCIE card of X8, and the connector adjacent to the connector are allowed to connect with PCIE card of X16 together. Since the connector is allowed to be connected with the BP, or connected with the PCIE card of X8, or connected with the PCIE card of X16, the flexibility of the link width of the PCIE in the scheme of the present application is greatly improved, that is, for any group of PCIE, it is not limited that the PCIE can only be used as a specific link width to connect a specific device. Since the connector is allowed to be connected with the BP, or connected with a PCIE card of X8, or connected with a PCIE card of X16, it is necessary to enable the CPU to know the specific device type connected to the current connector. To sum up, the application realizes the improvement of the flexibility of the width of the PCIE link of the server mainboard, and can flexibly configure the PCIE device connected with the CPU.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a conventional server motherboard design;
fig. 2 is a schematic structural diagram of a server motherboard according to the present invention.
Detailed Description
The core of the invention is to provide a server mainboard, which realizes the improvement of the flexibility of the PCIE link width of the server mainboard and can flexibly configure the PCIE devices connected with the CPU.
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a server motherboard according to the present invention, where the server motherboard may include:
a server motherboard body, a CPU 101;
the CPU101 is provided with N groups of PCIE interfaces, each group of PCIE interfaces is the link width of X8, and each group of PCIE interfaces is provided with a target interface which corresponds to the group of PCIE interfaces and is used for outputting information which represents the type of a device connected with the PCIE interface to the CPU 101; n is a positive integer;
the N sets of PCIE interfaces are connected to the N connectors 102, respectively;
for any one connector 102, the connector 102 is allowed to connect with BP, the connector 102 is allowed to connect with PCIE card of X8, and the connector 102 adjacent to the connector 102 are allowed to connect with PCIE card of X16.
The specific type of each connector 102 of the present application can be set and adjusted based on actual needs, for example, in a specific embodiment of the present invention, each connector 102 can be a slim line type connector 102, and the slim line connector 102 has a wide application range and high stability.
Specifically, the type of the CPU101 of the present application may be set and adjusted according to actual conditions, for example, in a specific embodiment of the present invention, the CPU101 is a 32-core CPU of a marine light 7000, and may support an 8-channel DDR4 memory, and integrate four sets of PCIE X16 controllers, so that the operation performance is greatly improved.
The server main board body indicates the components of the server main board other than the CPU101 and the connector 102, and the specific configuration of the server main board body may be set and adjusted according to actual conditions, and will not be described herein.
According to the method, PCIE of the CPU101 is divided into N groups, each group of PCIE interfaces is link width of X8, the N groups of PCIE interfaces are respectively connected with N connectors 102, namely the PCIE of the CPU101 is connected to each connector 102 according to X8 link width, and the specific value of N depends on the structural design of the CPU 101. In a specific situation, the number of connectors 102 for connecting with BP, the number of connectors 102 for connecting with PCIE card of X8, and the number of connectors 102 for connecting with PCIE card of X16 on the server motherboard can be selected according to actual needs, and can be flexibly adjusted.
Since, in the solution of the present application, it is necessary to allow the connector 102 to be connected to a BP, allow the connector 102 to be connected to a PCIE card of X8, and allow the connector 102 and the connector 102 adjacent to the connector 102 to be connected to a PCIE card of X16 together, for any connector 102, it is necessary to enable the CPU101 to know what type of device this connector 102 is currently connected to, that is, what type of device the PCIE interfaces are connected to is required to be known by the CPU 101. The application configures a target interface corresponding to each group of PCIE interfaces for each group of PCIE interfaces, and the target interface may output information indicating a device type connected to the PCIE interface to the CPU101, so that the CPU101 may perform corresponding signal configuration according to the information output by each target interface.
The specific type of the target interface may be set and adjusted according to actual needs, as long as the purpose of the present application can be achieved, in a specific embodiment of the present invention, the target interface may be achieved based on a common GPIO interface, and considering that there are 3 possible types of devices connected to the PCIE interface, that is, the PCIE interface may be connected to a BP, to a PCIE card of X8, and to a PCIE card of X16, so that the purpose of the present application may be achieved by including 2 GPIO interfaces in the target interface. The target interface may be directly connected to the CPU101, or may be placed on the corresponding connector 102 and connected to the CPU 101.
Specifically, in a specific embodiment of the present invention, each target interface includes a first GPIO interface and a second GPIO interface;
moreover, for any one target interface, when the first GPIO interface of the target interface is at the first level and the second GPIO interface is at the second level, it indicates that the PCIE interface corresponding to the target interface is connected to the PCIE card of X8 through the connector 102 and the RISER of X8;
for any target interface, when the first GPIO interface of the target interface is at the first level and the second GPIO interface is at the first level, it indicates that the PCIE interface corresponding to the target interface is connected to the PCIE card of X16 through the connector 102 and the RISER of X16, and another connector 102 connected to the RISER of X16 is adjacent to the connector 102 corresponding to the target interface;
for any target interface, when the first GPIO interface of the target interface is at the second level and the second GPIO interface is at the second level, it indicates that the PCIE interface corresponding to the target interface is connected to the BP through the connector 102.
For convenience of description and understanding, in the following embodiments, the first level is a high level, and the second level is a low level, but it should be noted that, when the first level is designed to be a low level, and the second level is designed to be a high level, implementation of the scheme can also be guaranteed, that is, the target interface can also be enabled to successfully output information indicating the type of the device connected to the PCIE interface corresponding to the target interface to the CPU 101.
In this embodiment, the motherboard end sets high levels of the 2 GPIO interfaces included in the target interface, that is, the first GPIO interface and the second GPIO interface of each target interface are both set to be high levels by default.
For convenience of description, N sets of PCIE interfaces set in the CPU101 are sequentially referred to as a 1 st set of PCIE interfaces, a 2 nd set of PCIE interfaces …, a target interface corresponding to each set of PCIE interfaces is sequentially referred to as a 1 st target interface, a 2 nd target interface … nth target interface, a connector 102 connected to each set of PCIE interfaces is sequentially referred to as a 1 st connector 102, a 2 nd connector 102 … nth connector 102, and the 1 st connector 102, the 2 nd connector 102, until the nth connector 102 is sequentially adjacent.
For example, when an X8 PCIE card is connected to the 1 st connector 102 through an X8 RISER, the first GPIO interface of the 1 st target interface is at a high level, and the second GPIO interface of the 1 st target interface is at a low level. The first GPIO interface of the 1 st target interface is at a high level, which indicates that the 1 st group of PCIE interfaces is connected to the RISER at this time, thereby connecting the PCIE card, and the second GPIO interface of the 1 st target interface is at a low level, which indicates that the PCIE card connected to the 1 st group of PCIE interfaces at this time is specifically a PCIE card of X8. Thus, when the computer is turned on, the CPU101 may detect the level states of 2 GPIOs on the 1 st target interface, and set the X8 signal on the 1 st connector 102 to be a single X8 signal, that is, the computer may be connected through the 1 st connector 102 to support a RISER of X8, that is, a PCIE card of X8.
For example, when an X16 PCIE card is connected to the 2 nd connector 102 and the 3 rd connector 102 through an X16 RISER, the first GPIO interface of the 2 nd target interface is at a high level, the second GPIO interface of the 2 nd target interface is at a high level, the first GPIO interface of the 3 rd target interface is at a high level, and the second GPIO interface of the 3 rd target interface is at a high level.
The first GPIO interface of the 2 nd target interface is at a high level, which indicates that the 2 nd group of PCIE interfaces are connected to the RISER at this time, and further connected to the PCIE card, and the second GPIO interface of the 2 nd target interface is at a high level, which indicates that the PCIE card connected to the 2 nd group of PCIE interfaces at this time is specifically a PCIE card of X16. Similarly, the first GPIO interface of the 3 rd target interface is at a high level, which indicates that the 3 rd group of PCIE interfaces are connected to the RISER at this time, and then connected to the PCIE card, and the second GPIO interface of the 3 rd target interface is at a high level, which indicates that the PCIE card connected to the 3 rd group of PCIE interfaces at this time is specifically the PCIE card of X16.
Thus, at the time of booting, the CPU101 may detect the level states of 2 GPIOs on the 2 nd target interface and the level states of 2 GPIOs on the 3 rd target interface, and combine the X8 signal of the 2 nd connector 102 and the X8 signal of the 3 rd connector 102 adjacent to the 2 nd connector 102 into an X16 signal, so as to support a RISER of X16, that is, a PCIE card of X16, through the connection between the 2 nd connector 102 and the 3 rd connector 102.
For example, if an X8 PCIE card is connected to the 4 th connector 102 through an X8 RISER, then, in the same manner as above, at the time of booting, the CPU101 may detect the level status of 2 GPIOs of the 4 th target interface, and set the X8 signal on the 4 th connector 102 to a single X8 signal, so that through the connection of the 4 th connector 102, an X8 RISER is supported, that is, a X8 PCIE card is supported.
For example, an X16 PCIE card is connected to the 5 th connector 102 and the 6 th connector 102 through an X16 RISER, and an X16 PCIE card is connected to the 7 th connector 102 and the 8 th connector 102 through an X16 RISER, so as to have the same principle as above, at the time of booting, the CPU101 may detect the level state of each GPIO of the 5 th target interface to the 8 th target interface, merge the X8 of the 5 th connector 102 and the 6 th connector 102 into an X16 signal, merge the X8 of the 7 th connector 102 and the 8 th connector 102 into an X16 signal, so that a RISER of X16 is supported through the connection of the 5 th connector 102 and the 6 th connector 102, and a RISER of X16 is supported through the connection of the 7 th connector 102 and the 8 th connector 102.
It should be emphasized that when the PCIE card of X16 or the PCIE card of X8 is connected to the connector 102, the connection cannot be directly made, but needs to be implemented through the RISER of X16 or the RISER of X8, but the RISER is not shown in the drawings of the present application for easy viewing.
For example, if the BP is connected to the 9 th connector 102, the first GPIO interface of the 9 th target interface is at low level, and the second GPIO interface of the 9 th target interface is at low level. The first GPIO interface of the 9 th target interface is at low level, which means that the 9 th set of PCIE interfaces is connected to the BP through the 9 th connector 102 at this time. Thus, when the computer is powered on, the CPU101 may detect the level states of 2 GPIOs on the 9 th target interface, and set the X8 signal on the 9 th connector 102 to 2X 4 signals, so that a 2-block X4 hard disk on BP, specifically, a 2-block X4 NVME hard disk, may be supported by the 9 th connector 102. That is, in one embodiment of the invention, for any one connector 102, when the connector 102 is connected to a BP, the connector 102 is connected to the NVME hard disk of 2 block X4 via the BP.
By applying the technical scheme provided by the embodiment of the invention, the PCIE of the CPU101 is divided into N groups of PCIE, each group of PCIE interfaces is the link width of X8, and the N groups of PCIE interfaces are respectively connected with N connectors 102; for any one connector 102, the connector 102 is allowed to connect with BP, the connector 102 is allowed to connect with PCIE card of X8, and the connector 102 adjacent to the connector 102 are allowed to connect with PCIE card of X16. Since the connector 102 is allowed to be connected with the BP, or connected with the PCIE card of X8, or connected with the PCIE card of X16, the flexibility of the PCIE link width according to the scheme of the present application is greatly improved, that is, for any group of PCIE, it is not limited that the PCIE can only be used as a specific link width to connect a specific device. Since the connector 102 is allowed to be connected to a BP, or connected to a PCIE card of X8, or connected to a PCIE card of X16, it is necessary to enable the CPU101 to know the specific device type of the current connector 102, and in the scheme of the present application, a target interface corresponding to each group of PCIE interfaces is configured for each group of PCIE interfaces, and the target interface is configured to output information indicating the device type connected to the PCIE interface to the CPU 101. To sum up, the application realizes the improvement of the flexibility of the width of the PCIE link of the server motherboard, and can flexibly configure the PCIE device connected to the CPU 101.
Corresponding to the above embodiments of the server motherboard, embodiments of the present invention further provide a server, including the server motherboard in any of the above embodiments, which can be referred to in correspondence with the above, and a description thereof is not repeated here.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The principle and the implementation of the present invention are explained in the present application by using specific examples, and the above description of the embodiments is only used to help understanding the technical solution and the core idea of the present invention. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Claims (7)
1. A server board, comprising:
a server main board body, a CPU;
the CPU is provided with N groups of PCIE interfaces, each group of PCIE interfaces is the link width of X8, and each group of PCIE interfaces is provided with a target interface which corresponds to the group of PCIE interfaces and is used for outputting information which represents the type of a device connected with the PCIE interface to the CPU; n is a positive integer;
the N groups of PCIE interfaces are respectively connected with the N connectors;
for any one connector, the connector is allowed to connect with BP, and the connector is allowed to connect with PCIE card of X8, and the connector adjacent to the connector are allowed to connect with PCIE card of X16 together.
2. The server motherboard of claim 1 wherein each of the target interfaces comprises a first GPIO interface and a second GPIO interface;
moreover, for any one target interface, when the first GPIO interface of the target interface is at the first level and the second GPIO interface is at the second level, it indicates that the PCIE interface corresponding to the target interface is connected to the PCIE card of X8 through the connector and the RISER of X8;
for any one target interface, when the first GPIO interface of the target interface is at the first level and the second GPIO interface is at the first level, it indicates that the PCIE interface corresponding to the target interface is connected to the PCIE card of X16 through a connector and a RISER of X16, and another connector connected to the RISER of X16 is adjacent to the connector corresponding to the target interface;
for any target interface, when the first GPIO interface of the target interface is at the second level and the second GPIO interface is at the second level, it indicates that the PCIE interface corresponding to the target interface is connected to the BP through the connector.
3. The server board according to claim 2, wherein the first level is a high level, and the second level is a low level.
4. Server board as claimed in claim 1, characterized in that each connector is a Slimline-type connector.
5. The server motherboard of claim 1 wherein the CPU is a 32-core CPU of marine 7000.
6. The server motherboard of claim 1 wherein for any connector, when the connector is connected to a BP, the connector is connected to the NVME hard disk of block 2X 4 via the BP.
7. A server, comprising a server board according to any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011311238.8A CN112433974A (en) | 2020-11-20 | 2020-11-20 | Server and server mainboard |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011311238.8A CN112433974A (en) | 2020-11-20 | 2020-11-20 | Server and server mainboard |
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| CN112433974A true CN112433974A (en) | 2021-03-02 |
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| CN202011311238.8A Pending CN112433974A (en) | 2020-11-20 | 2020-11-20 | Server and server mainboard |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN209895219U (en) * | 2019-05-27 | 2020-01-03 | 苏州浪潮智能科技有限公司 | Board card based on multifunctional Slimline connector |
| CN111723037A (en) * | 2020-06-19 | 2020-09-29 | 浪潮电子信息产业股份有限公司 | PCIE interface extension system and server |
| CN111752871A (en) * | 2020-05-29 | 2020-10-09 | 苏州浪潮智能科技有限公司 | PCIE equipment, device and method for realizing compatibility of same PCIE slot position with different PCIE bandwidths |
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2020
- 2020-11-20 CN CN202011311238.8A patent/CN112433974A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN209895219U (en) * | 2019-05-27 | 2020-01-03 | 苏州浪潮智能科技有限公司 | Board card based on multifunctional Slimline connector |
| CN111752871A (en) * | 2020-05-29 | 2020-10-09 | 苏州浪潮智能科技有限公司 | PCIE equipment, device and method for realizing compatibility of same PCIE slot position with different PCIE bandwidths |
| CN111723037A (en) * | 2020-06-19 | 2020-09-29 | 浪潮电子信息产业股份有限公司 | PCIE interface extension system and server |
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Application publication date: 20210302 |