CN112433555A - Voltage stabilizer and control method of voltage stabilizer - Google Patents
Voltage stabilizer and control method of voltage stabilizer Download PDFInfo
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- CN112433555A CN112433555A CN201910789186.6A CN201910789186A CN112433555A CN 112433555 A CN112433555 A CN 112433555A CN 201910789186 A CN201910789186 A CN 201910789186A CN 112433555 A CN112433555 A CN 112433555A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention provides a voltage stabilizer and a control method thereof. The voltage stabilizer comprises a voltage stabilizer and a path switch. The voltage stabilizer comprises an output end and a voltage division circuit. The output terminal is used for generating a control voltage. The voltage divider circuit generates an overshoot reference voltage according to the input voltage. The first end of the path switch is coupled with the output end, the second end of the path switch is coupled with the reference voltage end, and the control end of the path switch receives the overshoot reference voltage. When the control voltage is greater than the sum of the overshoot reference voltage and the threshold voltage of the path switch, the path switch is turned on to guide the charge of the output terminal to the reference voltage terminal.
Description
Technical Field
The invention relates to a voltage stabilizer technology, in particular to a voltage stabilizer applicable to a quick access memory and a control method of the voltage stabilizer.
Background
In the NOR (NOR) cache memory technology, a regulator mainly regulates a pumping voltage (pumping voltage) higher than an operating voltage to generate a control voltage, so as to smoothly perform corresponding operations on the cache memory, such as read/write/set/program/erase operations. Therefore, the voltage regulator is desired to be able to rapidly raise the control voltage and maintain the stability of the control voltage.
However, since the output of the conventional voltage regulator is difficult to discharge charges, it may cause erroneous determination during partial operation of the cache memory. For example, in the Post-Program (Post-PGM) operation, the control voltage generated by the voltage regulator will affect the verification result of the memory cell and cause a malfunction.
Disclosure of Invention
The invention provides a voltage stabilizing device applicable to a cache memory and a control method thereof, so that the output end of the voltage stabilizing device has better charge release efficiency under specific conditions.
The voltage stabilizing device comprises a voltage stabilizer and a path switch. The voltage stabilizer comprises an output end and a voltage division circuit. The output terminal is used for generating a control voltage. The voltage divider circuit generates an overshoot reference voltage according to the input voltage. The first end of the path switch is coupled with the output end, the second end of the path switch is coupled with the reference voltage end, and the control end of the path switch receives the overshoot reference voltage. When the control voltage is greater than the sum of the overshoot reference voltage and the threshold voltage of the path switch, the path switch is turned on to guide the charge at the output terminal to the reference voltage terminal.
The control method of the voltage stabilizing device comprises the following steps. And setting a path switch, wherein a first end of the path switch is coupled to the output end, and a second end of the path switch is coupled to the reference voltage end. The overshoot reference voltage is generated by a voltage divider circuit, wherein the control terminal of the path switch receives the overshoot reference voltage. And judging whether the control voltage is greater than the sum of the overshoot reference voltage and the critical voltage of the path switch. And when the control voltage is larger than the sum of the overshoot reference voltage and the threshold voltage of the path switch, the path switch is conducted to guide the charges at the output end to the reference voltage end.
Based on the above, the voltage regulator and the control method thereof according to the embodiments of the present invention set the path switch at the output terminal of the voltage regulator, generate the overshoot reference voltage by using the voltage divider circuit in the voltage regulator, and compare the overshoot reference voltage and the control voltage at the output terminal by using the physical characteristics of the path switch. When the control voltage is greater than the sum of the overshoot reference voltage and the threshold voltage of the path switch, indicating that the memory cell of the cache memory is in the next stage of programming operation of the cache memory and the overshoot occurs, the path switch is turned on to guide the charge at the output end to the reference voltage end, so that the output end of the voltage stabilizer has better charge release efficiency. On the other hand, when the control voltage is not greater than the sum of the overshoot reference voltage and the threshold voltage of the path switch, the path switch is turned off to maintain the charge at the output terminal. Therefore, the voltage stabilizing device can enable the output end of the voltage stabilizing device to have better charge release efficiency under specific conditions.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic diagram of a voltage stabilization device according to an embodiment of the present invention;
fig. 2 is a block diagram of a voltage stabilizer according to an embodiment of the present invention;
fig. 3 is a circuit diagram of a voltage regulator device according to an embodiment of the present invention;
fig. 4 is a flowchart of a method for controlling a voltage regulator according to an embodiment of the present invention.
The reference numbers illustrate:
100: voltage stabilizer
110: voltage stabilizer
120: voltage divider circuit
130: path switch
230: error amplifier
235: signal conversion circuit
240: voltage level shift circuit
250: output stage circuit
260: frequency compensation circuit
270: trimming circuit
280: bias circuit
310: voltage converter
DTCODE: digital pruning code
VREF: reference voltage
VREFOS: overshoot reference voltage
VCNT: control voltage
Vth1, Vth 2: critical voltage
VCNT 1: a first control voltage
VCNT 2: second control voltage
VG: comparing voltages
N1: first end of path switch
N2: second terminal of path switch
N2401: first terminal of voltage level shift circuit
N2402: second terminal of voltage level shift circuit
NC: control terminal of path switch
NOUT: output end
NFB: feedback terminal
NCOM: comparison output terminal
Rm: compensation resistor
Cm: compensation capacitor
CT 1: first holding capacitor
CT 2: second holding capacitor
VDD: operating voltage
Vin: input voltage
R1-R6: resistance (RC)
MS1 MS3, MN1, MN 2: n-type MOS
MP 1: p-type MOS
GND: ground voltage terminal
MEN: start switch
EN: enabling voltage
I: electric current
Detailed Description
Fig. 1 is a schematic diagram of a voltage stabilizer 100 according to an embodiment of the invention. The voltage stabilizer 100 can be applied to a control device of a cache memory. The cache may be a logical inverse or (NOR) type cache or a logical inverse and (NAND) type cache. The voltage stabilizer 100 mainly stabilizes the extracted voltage higher than the working voltage to generate the control voltage VCNT, so as to smoothly perform the corresponding operation on the cache memory. The voltage regulator device according to the embodiments of the present invention can be applied to other technologies, such as other types of memory devices (e.g., Resistive Random Access Memory (RRAM), ferroelectric random access memory (FeRAM), Magnetoresistive Random Access Memory (MRAM)).
The voltage regulator apparatus 100 of the present embodiment includes a voltage regulator 110 and a path switch 130. The voltage regulator 110 generates a control voltage VCNT according to the reference voltage VREF. The voltage regulator 110 mainly includes an output terminal NOUT and a voltage divider circuit 120. The output terminal NOUT is used to generate the control voltage VCNT. The voltage divider circuit 120 generates the overshoot reference voltage VREFOSs according to the input voltage. For example, the voltage value of the overshoot reference voltage VREFOSs is designed based on the overshoot condition of the memory cell in the next stage programming operation of the cache memory, so as to determine whether the memory cell overshoots by using the overshoot reference voltage VREFOSs.
The first terminal N1 of the path switch 130 is coupled to the output terminal NOUT, and the second terminal N2 of the path switch 130 is coupled to a reference voltage terminal (for example, the ground voltage terminal GND in this embodiment). The control terminal NC of the path switch 130 receives the overshoot reference voltage VREFOSs. The path switch 130 can be implemented by a Metal-Oxide-Semiconductor Field-Effect Transistor (MOS), which is mainly implemented by a P-type MOS in this embodiment. The path switch 130 implemented by the P-type MOS has a threshold voltage Vth. Thus, during the subsequent stage programming operation of the cache memory, when the control voltage VCNT is greater than the sum of the overshoot reference voltage VREFOS and the threshold voltage Vth of the path switch 130, the path switch 130 is turned on to conduct the charge at the output terminal NOUT to the reference voltage terminal (the ground voltage terminal GND). In contrast, when the control voltage VCNT is not greater than the sum of the overshoot reference voltage VREFOSs and the threshold voltage Vth, the path switch 130 is turned off to maintain the charge at the output terminal NOUT.
Fig. 2 is a block diagram of a voltage stabilizer 100 according to an embodiment of the invention. Fig. 2 mainly illustrates each element in the voltage regulator 110. The voltage regulator 110 mainly includes an error amplifier 230, a signal conversion circuit 235, a voltage level shift circuit 240, and an output stage circuit 250, in addition to the voltage divider circuit 120. The regulator 110 may also include a frequency compensation circuit 260, a trimming (trimming) circuit 270, and a bias circuit 280.
The voltage divider circuit 120 further includes a feedback terminal NFB. The inverting terminal of the error amplifier 230 is coupled to the reference voltage VREF, and the non-inverting terminal of the error amplifier 230 is coupled to the feedback terminal NFB. An input terminal of the signal conversion circuit 235 is coupled to the comparison output terminal NCOM of the error amplifier 230. The output stage circuit 250 may be coupled to the signal conversion circuit 235 through the voltage level shift circuit 240, and the output stage circuit 250 is further coupled to the output terminal NOUT of the voltage regulator 110 through an output terminal thereof. The output stage circuit 250 is also coupled to a bias circuit 280.
In terms of the operation of each element, the error amplifier 230 compares the reference voltage VREF with the voltage of the feedback terminal NFB to generate the comparison voltage VG at the comparison output terminal NCOM. The signal conversion circuit 235 converts the voltage signal into a current signal through a current mirror structure, for example, converts the comparison voltage VG into a current I flowing through the signal conversion circuit 235, the voltage level shift circuit 240 and the voltage dividing circuit 120. The voltage divider circuit 120, the voltage level shifter circuit 240 and the signal converter circuit 235 generate a first control voltage VCNT1 at the first end N2401 of the voltage level shifter circuit 240 and a second control voltage VCNT2 at the second end N2402 of the voltage level shifter circuit 240 according to the comparison voltage VG. The level shift circuit 240 is used to shift the voltage level of the first control voltage VCNT1, so that the level shift circuit 240 and the output stage circuit 250 can eliminate the offset of the control voltage VCNT caused by the process variation, and will be described in detail in the following embodiments. The output stage circuit 250 generates the control voltage VCNT according to the second control voltage VCNT2 and the bias circuit 280.
The frequency compensation circuit 260 is coupled between the comparison output end NCOM of the error amplifier 230 and the voltage division circuit 120 for compensating the noise generated by the feedback end NFB. The trimming circuit 270 is coupled to the voltage dividing circuit 120. The trimming circuit 270 is used for adjusting the voltage values of the first control voltage VCNT1 and the overshoot reference voltage VREFOSs generated by the voltage divider circuit 120 according to the digital trimming code DTCODE. Fig. 3 and the corresponding description are given for a detailed circuit diagram of the trimming circuit 270.
Fig. 3 is a circuit diagram of a voltage stabilizing device 100 according to an embodiment of the invention. The related elements of fig. 1 and 2 are shown in fig. 3 and implemented by basic circuit elements such as Metal Oxide Semiconductor (MOS), resistor, capacitor, amplifier, etc. For example, the voltage divider circuit 120 may be implemented by a resistor string formed by connecting a plurality of resistors R1 to R6 in series; the path switch 130 may be implemented by a P-type MOS MP 1; the signal conversion circuit 235 and the bias circuit 280 may be implemented by a plurality of N-type MOS and P-type MOS; the output stage circuit 250 can be realized by a source follower formed by an N-type MOS MN 1; the frequency compensation circuit 260 can be implemented by a compensation resistor Rm and a compensation capacitor Cm connected in series; the level shift circuit 240 may be implemented by an N-type MOS MN2, wherein a source terminal of the MOS MN2 serves as a first terminal N2401 of the level shift circuit 240, and a drain terminal of the MOS MN2 is coupled to a gate terminal thereof to serve as a second terminal N2402 of the level shift circuit 240. Vin is the input voltage of the regulator 100, and VDD is the operating voltage of the regulator 100.
The voltage regulator device 100 further includes an enable switch MEN. The second terminal N2 of the path switch 130 is coupled to a reference voltage terminal (e.g., the ground voltage terminal GND) via an enable switch MEN. The control terminal of the enable switch MEN receives an enable voltage EN. Therefore, when the voltage regulator 100 is turned on, the on-switch MEN is turned on, so as to avoid noise interference of the voltage regulator 100 when turned on.
The details of how the voltage level shifter 240 and the output stage 250 cancel the offset of the control voltage VCNT due to the process variation are described. Referring to fig. 3, the voltage value of the second control voltage VCNT2 is equal to the first control voltage VCNT1 plus the threshold voltage Vth2 of the N-type MOS MN2 in the voltage level shifting circuit 240, and the voltage value of the control voltage VCNT is equal to the second control voltage VCNT2 minus the threshold voltage Vth1 of the N-type MOS MN1 in the output stage 250. The threshold voltages Vth1 and Vth2 of N-type MOS MN1 and MN2 are related to the shift caused by the process variation, so under the same process, the threshold voltage Vth1 of MOS MN1 is equal to the threshold voltage Vth2 of MOS MN2, thereby eliminating the process variation.
Trimming circuit 270 is described in greater detail herein. The trimming circuit 270 is implemented by a plurality of N-type MOSs (for example, the MOSs MS1 to MS3 in fig. 3) as switches and a plurality of voltage converters (level shifters) 310 that convert digital trimming codes dtc into analog voltages. The voltage converter 310 converts the digital trimming code dtco into analog voltages, and controls whether the N-type MOS MSs 1-MS 3 are turned on or not by using the analog voltages, so as to adjust the amount of current passing through the resistor strings R1-R6, and thereby adjust the voltage values of the first control voltage CVNT1 and the overshoot reference voltage VREFOSs. For example, when the N-type MOS MS1 is turned on and the N-type MOS MS2 and MS3 are turned off, the resistors R1, R2 and R6 allow current to flow, and the rest of the resistors (e.g., resistors R3-R5) do not allow current to flow. Therefore, based on the voltage division effect, the overshoot reference voltage VREFOSs will become the following voltage value: VREFOSs ═ VCNT1 xr 6/(R1+ R2+ R6); when the N-type MOS MS 1-MS 3 are all turned off, the resistors R1-R6 all allow current to flow, so that the overshoot reference voltage VREFOSs will be the following voltage value based on the voltage division effect: VREFOSs ═ VCNT1 × (R3+ R4+ R5+ R6)/(R1+ R2+ R3+ R4+ R5+ R6).
In order to effectively maintain the charges of the control voltage VCNT and the first control voltage VCNT1, the output terminal NOUT where the control voltage VCNT is located may be provided with a first maintaining capacitor CT1, and the terminal where the first control voltage VCNT1 is located may be provided with a second maintaining capacitor CT 2.
Fig. 4 is a flowchart of a control method of the voltage stabilizer 100 according to an embodiment of the invention. The voltage stabilizer 100 to which this control method is applied is as described above with reference to fig. 1 to 3. Referring to fig. 1 and 4, in step S410, the path switch 130 is disposed, wherein the first terminal N1 of the path switch 130 is coupled to the output terminal NOUT of the regulator 100, and the second terminal N2 of the path switch 130 is coupled to the reference voltage terminal (ground voltage terminal GND). In step S420, the overshoot reference voltage VREFOSs is generated by the voltage divider circuit 120 of the voltage regulator 100, and the control terminal NC of the path switch 130 receives the overshoot reference voltage VREFOSs. In step S430, it is determined whether the control voltage VCNT at the output terminal NOUT is greater than the sum of the overshoot reference voltage VREFOSs and the threshold voltage of the path switch 130 through the path switch 130.
When the control voltage VCNT is greater than the sum of the overshoot reference voltage VREFOSs and the threshold voltage of the path switch 130, the step S430 proceeds to step S440, and the path switch 130 is turned on to conduct the charge at the output terminal NOUT to the reference voltage terminal (ground voltage terminal GND). On the other hand, when the control voltage VCNT is not greater than the sum of the overshoot reference voltage VREFOSs and the threshold voltage of the path switch 130, the step S430 proceeds to step S450, and the path switch 130 is turned off to maintain the charge at the output terminal. The detailed step flow of the operation method can also refer to the embodiments of fig. 1 to 3 and the corresponding descriptions.
In summary, the voltage regulator and the control method thereof according to the embodiments of the present invention set the path switch at the output terminal of the voltage regulator, generate the overshoot reference voltage by using the voltage divider circuit in the voltage regulator, and compare the overshoot reference voltage with the control voltage at the output terminal by using the physical characteristics of the path switch. When the control voltage is greater than the sum of the overshoot reference voltage and the threshold voltage of the path switch, indicating that the memory cell of the cache memory is in the next stage of programming operation of the cache memory and the overshoot occurs, the path switch is turned on to guide the charge at the output end to the reference voltage end, so that the output end of the voltage stabilizer has better charge release efficiency. On the other hand, when the control voltage is not greater than the sum of the overshoot reference voltage and the threshold voltage of the path switch, the path switch is turned off to maintain the charge at the output terminal. Therefore, the voltage stabilizing device can enable the output end of the voltage stabilizing device to have better charge release efficiency under specific conditions.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (11)
1. A voltage stabilizing device comprising:
a voltage regulator, the voltage regulator comprising:
an output terminal for generating a control voltage; and
the voltage division circuit generates overshoot reference voltage according to input voltage; and
a path switch, wherein a first terminal of the path switch is coupled to the output terminal, a second terminal of the path switch is coupled to a reference voltage terminal, a control terminal of the path switch receives the overshoot reference voltage,
when the control voltage is larger than the sum of the overshoot reference voltage and the threshold voltage of the path switch, the path switch is conducted to lead the charge of the output end to the reference voltage end.
2. The voltage stabilization apparatus according to claim 1, wherein the voltage stabilization apparatus is used for a control apparatus of a cache memory, and,
during the back-end program operation of the cache memory, the path switch is turned on based on the control voltage being greater than the sum of the overshoot reference voltage and the threshold voltage.
3. The voltage regulator apparatus according to claim 1, wherein the path switch is turned off when the control voltage is not more than a sum of the overshoot reference voltage and the threshold voltage.
4. The voltage stabilization device of claim 1, wherein the voltage divider circuit further comprises a feedback terminal,
the voltage regulator further includes:
the inverting receiving end of the error amplifier is coupled with a reference voltage, and the non-inverting receiving end of the error amplifier is coupled with the feedback end;
the input end of the signal conversion circuit is coupled with the comparison output end of the error amplifier;
a voltage level shift circuit and a bias circuit; and
an output stage circuit coupled to the signal conversion circuit through the voltage level shift circuit, and coupled to the output terminal and the bias circuit,
wherein the voltage divider circuit, the voltage level shifter circuit and the signal converter circuit generate a first control voltage at a first end of the voltage level shifter circuit and a second control voltage at a second end of the voltage level shifter circuit according to the comparison voltage,
the voltage level shift circuit shifts the voltage level of the first control voltage, the bias circuit provides bias voltage to make the output stage circuit operate normally,
the output stage circuit generates the control voltage according to the second control voltage and the bias circuit.
5. The voltage stabilizing apparatus according to claim 4, wherein the voltage value of the second control voltage is equal to the voltage value of the first control voltage plus a threshold voltage of a transistor in the voltage level shift circuit, and the voltage value of the control voltage is equal to the voltage value of the second control voltage minus the threshold voltage of the transistor in the output stage circuit.
6. The voltage stabilization apparatus according to claim 4, further comprising:
and the frequency compensation circuit is coupled between the comparison output end of the error amplifier and the voltage division circuit.
7. The voltage stabilization apparatus according to claim 4, further comprising:
the trimming circuit is coupled to the voltage divider circuit and used for adjusting the voltage values of the first control voltage and the overshoot reference voltage generated by the voltage divider circuit according to a digital trimming code.
8. The voltage stabilization apparatus according to claim 1, further comprising:
an enable switch, wherein a second terminal of the path switch is coupled to the reference voltage terminal through the enable switch, a control terminal of the enable switch receives an enable voltage,
when the voltage stabilizing device is started, the starting switch is conducted.
9. A control method of a voltage stabilizer includes:
setting a path switch, wherein a first terminal of the path switch is coupled to the output terminal of the voltage regulator, and a second terminal of the path switch is coupled to a reference voltage terminal;
generating an overshoot reference voltage by a voltage divider circuit, wherein a control terminal of the path switch receives the overshoot reference voltage;
determining whether the control voltage at the output terminal is greater than the sum of the overshoot reference voltage and the threshold voltage of the path switch; and
when the control voltage is greater than the sum of the overshoot reference voltage and the threshold voltage of the path switch, turning on the path switch to direct the charge of the output terminal to the reference voltage terminal.
10. The control method according to claim 9, wherein the voltage stabilization means is used for a control means of a cache memory, and,
during the back-end program operation of the cache memory, the path switch is turned on based on the control voltage being greater than the sum of the overshoot reference voltage and the threshold voltage.
11. The control method according to claim 9, further comprising:
turning off the path switch when the control voltage is greater than a sum of the overshoot reference voltage and a threshold voltage of the path switch.
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| CN107102668A (en) * | 2016-02-22 | 2017-08-29 | 联发科技（新加坡）私人有限公司 | Low pressure difference linear voltage regulator |
| CN108089627A (en) * | 2016-11-22 | 2018-05-29 | 瑞昱半导体股份有限公司 | Reference voltage buffer circuit |
| CN108227816A (en) * | 2018-01-26 | 2018-06-29 | 武汉新芯集成电路制造有限公司 | Low-voltage landing voltage-stablizer |
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