CN112422255A

CN112422255A - Detection circuit and operation method

Info

Publication number: CN112422255A
Application number: CN201910780825.2A
Authority: CN
Inventors: 王顺生; 曾达钦; 林增奎; 吴宗晟
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2019-08-22
Filing date: 2019-08-22
Publication date: 2021-02-26

Abstract

A detection circuit and an operation method are disclosed. The detection circuit comprises an operation circuit and a comparison circuit. The arithmetic circuit is used for generating a plurality of first arithmetic values according to a plurality of first arithmetic symbols of a virtual noise sequence and a plurality of second arithmetic symbols of a receiving signal, and generating a second arithmetic value according to the first arithmetic values. If a symbol of the virtual noise sequence and an adjacent symbol are identical, the symbol is one of the first operation symbols. The second operators are respectively corresponding to the first operators. The comparison circuit is used for generating a comparison result according to the second operation value and a threshold value. The comparison result is used to determine whether the detection circuit correctly receives the pseudo noise sequence.

Description

Detection circuit and operation method

Technical Field

Embodiments of the present invention relate to a circuit technology, and more particularly, to a detection circuit and an operating method thereof.

Background

In the communication technology, a transmitting device and a receiving device need to perform a synchronization procedure before signal transmission. Generally, a Pseudo-Noise Sequence (PN Sequence) is used for the synchronization process.

Disclosure of Invention

Some embodiments of the invention relate to a detection circuit. The detection circuit comprises an operation circuit and a comparison circuit. The arithmetic circuit is used for generating a plurality of first arithmetic values according to a plurality of first arithmetic symbols of a virtual noise sequence and a plurality of second arithmetic symbols of a receiving signal, and generating a second arithmetic value according to the first arithmetic values. If a symbol of the virtual noise sequence and an adjacent symbol are identical, the symbol is one of the first operation symbols. The second operators are respectively corresponding to the first operators. The comparison circuit is used for generating a comparison result according to the second operation value and a threshold value. The comparison result is used to determine whether the detection circuit correctly receives the pseudo noise sequence.

Some embodiments of the invention relate to a detection circuit. The detection circuit comprises a symbol detection circuit, an arithmetic circuit and a comparison circuit. The symbol detection circuit is used for generating a receiving signal according to a received virtual noise sequence corresponding to a virtual noise sequence. The operation circuit is used for generating a plurality of first operation values according to a plurality of first operation symbols of the virtual noise sequence and a plurality of second operation symbols of the received signal, and generating a second operation value according to the first operation values. The second operators are respectively corresponding to the first operators. The comparison circuit is used for generating a comparison result according to the second operation value and a threshold value. The comparison result is used to determine whether the detection circuit correctly receives the pseudo noise sequence.

Some embodiments of the present invention relate to a method for operating a detection circuit. The operation method comprises the following steps: generating a received signal by a symbol detection circuit according to a received virtual noise sequence corresponding to a virtual noise sequence; an arithmetic circuit generates a plurality of first arithmetic values according to a plurality of first arithmetic symbols of the virtual noise sequence and a plurality of second arithmetic symbols of the received signal, and generates a second arithmetic value according to the first arithmetic values. If a symbol of the virtual noise sequence and an adjacent symbol are identical, the symbol is one of the first operation symbols. The second arithmetic symbols respectively correspond to the first arithmetic symbols; and generating a comparison result by a comparison circuit according to the second operation value and a threshold, wherein the comparison result is used for judging whether the detection circuit correctly receives the virtual noise sequence.

In summary, the detection circuit of the present invention can reduce the circuit complexity or the operation complexity.

Drawings

In order to make the aforementioned and other objects, features, advantages and embodiments of the invention more comprehensible, the following description is given:

FIG. 1 is a circuit diagram of a detection circuit according to some embodiments of the present invention;

FIG. 2 is a schematic diagram of a pseudo noise sequence, a received pseudo noise sequence and a received signal according to some embodiments of the invention;

FIG. 3 is a circuit diagram of a detection circuit according to some embodiments of the present invention;

FIG. 4 is a circuit diagram of a detection circuit according to some embodiments of the present invention; and

fig. 5 is a flow chart of a method of operating a detection circuit according to some embodiments of the invention.

Detailed Description

As used herein, the term "coupled" can also refer to electrically coupled "and the term" connected "can also refer to electrically connected. "coupled" and "connected" can also mean that two or more elements are in cooperation or interaction with each other.

Refer to fig. 1. Fig. 1 is a circuit diagram of a detection circuit 100 according to some embodiments of the invention. In some embodiments, the detection circuit 100 is configured in a receiving device. The receiving device receives a Pseudo-Noise Sequence (PN Sequence) from the transmitting device. The virtual noise sequence is a sequence consisting of +1 and-1. The detection circuit 100 in the receiving device determines whether the pseudo noise sequence is correctly received according to the received signal, and further determines whether the synchronization procedure between the receiving device and the transmitting device is completed. After the synchronization procedure is completed, signal transmission can be performed between the transmitting device and the receiving device.

For the purpose of the example of fig. 1, the detection circuit 100 includes a symbol detection circuit 120, a storage circuit 140, an operation circuit 160, and a comparison circuit 180. The storage circuit 140 is coupled to the symbol detection circuit 120. The operation circuit 160 is coupled to the storage circuit 140. The comparison circuit 180 is coupled to the operation circuit 160. The detection circuit 100 is used to receive a virtual noise sequence (e.g., the virtual noise sequence PN [ i ] in FIG. 2) from the transmitting device.

Reference is also made to fig. 1 and 2. FIG. 2 is a diagram illustrating a PN [ i ] sequence, a PNR [ i ] sequence and a received signal r [ i ] according to some embodiments of the invention. For the example of fig. 2, the virtual noise sequence PN [ i ] from the transmitting device contains eight symbols. The symbol PN 0 is +1, the symbol PN 1 is +1, the symbol PN 2 is +1, the symbol PN 3 is +1, the symbol PN 4 is-1, the symbol PN 5 is +1, the symbol PN 6 is +1, the symbol PN 7 is-1. In some other embodiments, the pseudo noise sequence PN [ i ] may include more symbols (e.g., 255 symbols).

The pseudo noise sequence PN [ i ] from the transmitting device is transmitted via the transmission channel to generate a pseudo noise sequence PNR [ i ], and the pseudo noise sequence PNR [ i ] is received by the symbol detection circuit 120 of the detection circuit 100. The symbol detection circuit 120 converts the received pseudo noise sequence PNR [ i ] into a received signal r [ i ]. In some embodiments, the symbol detection circuit 120 may be implemented using a symbol function circuit. When the nth symbol of the received pseudo noise sequence PNR [ i ] is equal to or greater than 0, the symbol detection circuit 120 sets the nth symbol of the received signal r [ i ] to + 1. When the nth symbol of the received pseudo noise sequence PNR [ i ] is less than 0, the symbol detection circuit 120 sets the nth symbol of the received signal r [ i ] to-1. The implementation of the symbol detection circuit 120 described above is merely an example, and various implementations that can be used to implement the symbol detection circuit 120 are within the scope of the present invention.

For the example of fig. 2, the received signal r [ i ] converted by the symbol detection circuit 120 also includes 8 symbols. Based on the above operation, under the condition that each symbol of the received PN sequence PNR [ i ] is identical to each symbol of the PN [ i ] (i.e. the ideal situation without being affected by inter-symbol interference and channel quality), the symbol r [0] is +1, the symbol r [1] is +1, the symbol r [2] is +1, the symbol r [3] is +1, the symbol r [4] is-1, the symbol r [5] is +1, the symbol r [6] is +1, and the symbol r [7] is-1.

If a symbol of the PN [ i ] sequence is signed with an adjacent symbol, the symbol is selected as the first operand. In some embodiments, the adjacent symbol may be a symbol subsequent to the symbol. For example, since the symbol PN [0] and the symbol PN [1] are both +1, the symbol PN [0] is selected as the first operand. Similarly, since the symbol PN [1] and the symbol PN [2] are both +1, the symbol PN [1] is selected as the first operation symbol. And so on. Accordingly, the first operand includes symbols PN [0], PN [1], PN [2], PN [5] (indicated by the thick dashed line in FIG. 2). In some other embodiments, the adjacent symbol may be a symbol preceding the symbol.

Accordingly, a plurality of symbols corresponding to the first operation symbols are selected from the received signal r [ i ] as second operation symbols. Accordingly, the second operand includes the symbols r [0], r [1], r [2], r [5] (marked by the thick dotted line in FIG. 2).

Since the first operand has 4 bits, the storage circuit 140 is designed to include 3 delayers D [0] to D [2], 4 registers 142[0] to 142[3], and 4 registers 144[0] to 144[3 ].

In some embodiments, 3 delayers D [0] to D [2] may each have a different delay time. As with the above embodiment, the delay time of delay D [0] is the same as that of delay D [1], but different from that of delay D [2 ].

The 4 registers 142[0] to 142[3] are used to store the four first operand bits PN [0], PN [1], PN [2], PN [5], respectively. The 4 registers 144[0] to 144[3] are used to store the four second operand symbols r [0], r [1], r [2], r [5], respectively.

For the example of fig. 1, the operation circuit 160 includes a multiplication circuit 162 and an addition circuit 164. The multiplication circuit 162 includes 4 multipliers. The adder circuit 164 includes 3 adders. The first multiplier multiplies the first operator PN [0] (value +1) with the second operator r [0] (value +1) to generate an operator value (value + 1). The second multiplier multiplies the first operator PN 1 (value +1) by the second operator r 1 (value +1) to generate an operator value (value + 1). The first adder adds the operation value from the first multiplier and the operation value from the second multiplier. And so on. The calculated value Y (value 4) will be generated. Based on the above operation, when one of the symbols of the PN [ i ] sequence is correctly received, the operation value Y is increased. On the contrary, when one of the symbols of the PN [ i ] is incorrectly received, the computed value Y is decreased. For example, in the case where the first operand is +1, the second operand may be-1 when incorrectly received. Accordingly, the operation value generated by the corresponding multiplier is-1. The operation value is such that the operation value Y is reduced. Accordingly, the operation value Y reflects the accuracy of the received pseudo noise sequence PNR [ i ].

In some other embodiments, the symbol detection circuit 120 may be implemented with a slicer (slicer), and the multipliers in the multiplication circuit 162 may be replaced by a plurality of exclusive nor gates (XNOR gates), respectively. In these embodiments, when the nth symbol of the received pseudo noise sequence PNR [ i ] is equal to or greater than 0, the symbol detection circuit 120 sets the nth symbol of the received signal r [ i ] to + 1. When the nth symbol of the received pseudo noise sequence PNR [ i ] is smaller than 0, the symbol detection circuit 120 sets the nth symbol of the received signal r [ i ] to 0. In these embodiments, the nth symbol of the virtual noise sequence PN [ i ] is transmitted to one of the inputs of one of the exclusive-or gates, and the nth symbol of the received signal r [ i ] is transmitted to the other input of the exclusive-or gate, and when PN [ i ] is +1, the value output to one of the inputs of the exclusive-or gate is 1, whereas when PN [ i ] is-1, the value output to one of the inputs of the exclusive-or gate is 0.

Accordingly, when the nth symbol of the PN [ i ] and the nth symbol of the received signal r [ i ] both correspond to +1 or-1, the output value of the XNOR gate is + 1. When one of the n-th symbol of the PN [ i ] and the n-th symbol of the received signal r [ i ] corresponds to +1 and the other corresponds to-1, the output value of the XNOR gate is 0. Based on the above operation, when one of the symbols of the PN [ i ] sequence is correctly received, the operation value Y is increased. On the contrary, when one of the symbols of the PN [ i ] is incorrectly received, the operation value Y is not changed. Accordingly, the operation value Y reflects the accuracy of the received pseudo noise sequence PNR [ i ].

Then, the comparison circuit 180 compares the operation value Y with the threshold TS to generate the comparison result CR. In some embodiments, the comparison circuit 180 may be implemented using a comparator. The processing circuit (not shown) of the receiving apparatus can determine whether the detection circuit 100 of the receiving apparatus correctly receives the pseudo noise sequence PN [ i ] according to the comparison result CR. For example, when the comparison result CR is that the operation value Y is equal to or less than the threshold TS, the processing circuit determines that the detection circuit 100 has not correctly received the pseudo noise sequence PN [ i ]. Conversely, when the comparison result CR is that the operation value Y is greater than the threshold TS, the processing circuit judges that the detection circuit 100 correctly receives the virtual noise sequence PN [ i ]. At this time, the processing circuit determines that the synchronization procedure between the transmitting device and the receiving device is completed. Then, signal transmission can be started between the transmitting device and the receiving device.

In some further embodiments, the detection circuit 100 is configured in both the transmitting device and the receiving device. In operation, the transmitting device transmits the pseudo noise sequence PN [ i ] to the detecting circuit 100 of the receiving device, and the detecting circuit 100 of the receiving device determines whether the receiving device correctly receives the pseudo noise sequence PN [ i ]. Similarly, the receiving device will also transmit the pseudo noise sequence PN [ i ] to the detection circuit 100 of the transmitting device, and the detection circuit 100 of the transmitting device will determine whether the receiving device correctly receives the pseudo noise sequence PN [ i ]. When the receiving device and the transmitting device both correctly receive the pseudo noise sequence PN [ i ], the synchronization procedure between the transmitting device and the receiving device is completed.

The selection mechanism of the first operand symbol can be generalized to more adjacent symbols. In some other embodiments, if the ith symbol, the (i +1) th symbol and the (i-1) th symbol of the PN [ i ] sequence are the same sign, the ith symbol is selected as the first operand symbol. In some other embodiments, if the ith symbol and the (i +2) th symbol, the (i +1) th symbol, the (i-1) th symbol and the (i-2) th symbol of the PN [ i ] sequence are the same, the ith symbol is selected as the first operand.

In some related art, the detection circuit operates on all the symbols. However, when two adjacent symbols in the PN [ i ] sequence are different symbols (e.g., +1 for one symbol and-1 for another symbol), the two corresponding symbols in the received PN [ i ] sequence are easily misjudged due to inter-symbol interference (ISI), so that the system accuracy is reduced. Conversely, when a plurality of symbols in the PN [ i ] sequence are all of the same sign, the corresponding symbol of the received PN [ i ] sequence is less prone to error. Accordingly, the detection circuit 100 selects one symbol from a plurality of consecutive identical symbols of the pseudo noise sequence PN [ i ] as a first operator, and performs an operation using the first operator and a corresponding second operator. The number of the first operator (or the second operator) selected is less than the number of the virtual noise sequence PN [ i ]. Thus, the number of multipliers in the operation circuit 160 and the number of adders in the operation circuit 160 can be reduced without losing accuracy, so that the circuit complexity and the operation complexity of the detection circuit 100 can be reduced.

In addition, in some related arts, a received pseudo noise sequence PNR [ i ] is converted by using an analog-to-digital converter with multiple symbols. The symbol detection circuit 120 is less complex than a multi-symbol adc. Thus, the complexity of the detection circuit 100 is reduced.

In addition, in some related arts, the second operand element is a floating point number (floating number). In contrast to these related techniques, each symbol in the received signal r [ i ] converted by the symbol detection circuit 120 is either-1 or + 1. Thus, the second operator selected from the received signal r [ i ] is not a floating point number. That is, the first operand elements and the second operand elements stored in the storage circuit 140 are not floating point numbers. Thus, the cost of the storage circuit 140 can be reduced, and the operation complexity and cost of the operation circuit 160 can also be reduced.

Refer to fig. 3. Fig. 3 is a circuit diagram of a detection circuit 300 according to some embodiments of the invention. For ease of understanding, similar components to those of FIG. 3 will be given the same reference numerals as in FIG. 1. Only the differences between fig. 3 and fig. 1 are described below.

When the PN [ i ] comprises N symbols, the storage circuit 340 comprises (N-1) delayers D [0] to D [ N-2], N registers 142[0] to 142[ N-1] and N registers 144[0] to 144[ N-1], the multiplication circuit 362 comprises N multipliers, and the addition circuit 364 comprises (N-1) adders. The symbols of the PN [ i ] are stored in registers 142[0] to 142[ N-1], respectively. The symbols of the received signal r [ i ] are stored in registers 144[0] to 144[ N-1], respectively. As previously described, the symbols PN [0], PN [1], PN [2], PN [3], PN [5], PN [6] of the virtual noise sequence PN [ i ] are +1 and the symbols r [0], r [1], r [2], r [3], r [5], r [6] of the received signal r [ i ] are + 1. The remaining symbols of the pseudo noise sequence PN [ i ] are-1 and the remaining symbols of the received signal r [ i ] are-1. Thus, the operation value of all multipliers is + 1. The addition circuit 364 adds the operation values of all the multipliers to generate an operation value Y. Other relevant contents of the detection circuit 300 are similar to the detection circuit 100 of fig. 1, and therefore are not described herein again.

Refer to fig. 4. Fig. 4 is a circuit diagram of a detection circuit 400 according to some embodiments of the invention. For ease of understanding, similar components to those of FIG. 4 will be numbered identically to those of FIG. 3. Only the differences between fig. 4 and fig. 3 are described below.

For the example of FIG. 4, the detection circuit 400 further includes N switches S [0] to S [ N-1 ]. The switches S0 to S N-1 are coupled to the multipliers, respectively. As previously described, since the symbols PN [0], PN [1], PN [2], PN [5] of the virtual noise sequence PN [ i ] are selected as the first operator symbols, the switches S [0], S [1], S [2], S [5] corresponding to these first operator symbols PN [0], PN [1], PN [2], PN [5] are controlled to be on, while the remaining switches are controlled to be off. Thus, the operation circuit 160 will operate on only the first operator symbols PN [0], PN [1], PN [2], PN [5] and the second operator symbols r [0], r [1], r [2], r [5] (not all symbols) to generate the operation value Y. Other relevant contents of the detection circuit 400 are similar to those of the detection circuit 300 in fig. 3, and therefore are not described herein again.

Refer to fig. 5. Fig. 5 is a flow chart of a method 500 for operating a detection circuit according to some embodiments of the invention. The operation method 500 includes operations S502, S504, and S506. In some embodiments, the operation method 500 is applied to the detection circuit 100 of fig. 1, but the invention is not limited thereto. For ease of understanding, the method 500 of operation will be discussed in conjunction with FIG. 1.

In operation S502, a received signal r [ i ] is generated by the symbol detection circuit 120 from a received pseudo noise sequence PNR [ i ], wherein the received pseudo noise sequence PNR [ i ] corresponds to the pseudo noise sequence PN [ i ]. In some embodiments, the pseudo noise sequence PN [ i ] from the transmitting device is transmitted over the transmission channel to generate the pseudo noise sequence PNR [ i ], and the pseudo noise sequence PNR [ i ] is received by the symbol detection circuit 120 of the detection circuit 100. When the nth symbol of the received pseudo noise sequence PNR [ i ] is equal to or greater than 0, the symbol detection circuit 120 sets the nth symbol of the received signal r [ i ] to + 1. When the nth symbol of the received pseudo noise sequence PNR [ i ] is smaller than 0, the symbol detection circuit 120 sets the nth symbol of the received signal r [ i ] to-1 or 0.

In operation S504, a plurality of first operation values are generated by the operation circuit 160 according to a plurality of first operation symbols of the PN [ i ] sequence and a plurality of second operation symbols of the received signal r [ i ], and a second operation value is generated according to the first operation values. In some embodiments, a symbol of the PN [ i ] sequence is selected as the first operand if the symbol is signed with an adjacent symbol. The corresponding symbol in the received signal r [ i ] is the second operation symbol. In some embodiments, the multiplication circuit 162 of the operation circuit 160 multiplies one of the first operator symbols and a corresponding one of the second operator symbols to generate the first operation value. The adder circuit 164 of the arithmetic circuit 160 adds these first arithmetic values to generate the arithmetic value Y.

In operation S506, the comparison circuit 180 generates a comparison result CR according to the operation value Y and the threshold TS. In some embodiments, when the comparison result CR is that the operation value Y is greater than the threshold TS, the processing circuit determines that the detection circuit 100 correctly receives the virtual noise sequence PN [ i ]. Conversely, when the comparison result CR is that the operation value Y is equal to or smaller than the threshold TS, the processing circuit determines that the detection circuit 100 has not correctly received the virtual noise sequence PN [ i ].

While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

[ notation ] to show

100. 300, 400: detection circuit

120: symbol detection circuit

140. 340, and (3): storage circuit

160: arithmetic circuit

162. 362, 462: multiplication circuit

164. 364: adder circuit

180: comparison circuit

500: operation method

S502, S504, S506: operation of

PN [ i ], PNR [ i ]: virtual noise sequence

r [ i ]: receiving a signal

D [0] to D [ N-2 ]: delay device

142[0] to 142[ N-1], 144[0] to 144[ N ]: buffer memory

PN [0] to PN [ N-1], r [0] to r [ N-1 ]: symbol element

S [0] to S [ N-1 ]: switch with a switch body

Y: calculated value

TS: threshold value

CR: and comparing the results.

Claims

1. A detection circuit, comprising:

an arithmetic circuit for generating a plurality of first arithmetic values according to a plurality of first arithmetic symbols of a virtual noise sequence and a plurality of second arithmetic symbols of a received signal, and generating a second arithmetic value according to the first arithmetic values, wherein if a symbol of the virtual noise sequence and an adjacent symbol are identical, the symbol is one of the first arithmetic symbols, and the second arithmetic symbols respectively correspond to the first arithmetic symbols; and

a comparison circuit for generating a comparison result according to the second operation value and a threshold, wherein the comparison result is used for judging whether the detection circuit correctly receives the virtual noise sequence.

2. The detection circuit of claim 1, wherein the arithmetic circuit comprises a multiplication circuit, and the multiplication circuit comprises:

and a plurality of multipliers, each of which is used for multiplying one of the first arithmetic symbols with a corresponding symbol of the second arithmetic symbols to generate the first arithmetic values, wherein the virtual noise sequence comprises N symbols, and the number of the multipliers is less than N.

3. The detection circuit of claim 2, wherein the operational circuit further comprises an adder circuit, and the adder circuit comprises:

a plurality of adders for adding the first operation values to generate the second operation values.

4. The detection circuit of claim 1, wherein the arithmetic circuit comprises a multiplication circuit, and the multiplication circuit comprises:

the multipliers are respectively coupled to the switches, wherein the switches corresponding to the first operation symbols are turned on to generate the first operation value.

5. A detection circuit, comprising:

a symbol detection circuit for generating a received signal according to a received virtual noise sequence corresponding to a virtual noise sequence;

an arithmetic circuit for generating a plurality of first arithmetic values according to a plurality of first arithmetic symbols of the pseudo noise sequence and a plurality of second arithmetic symbols of the received signal, and generating a second arithmetic value according to the first arithmetic values, wherein the second arithmetic symbols respectively correspond to the first arithmetic symbols; and

6. The detection circuit of claim 5, wherein when the nth symbol of the received pseudo noise sequence is equal to or greater than 0, the nth symbol of the received signal is + 1.

7. The detection circuit of claim 5, wherein when the nth symbol of the received pseudo noise sequence is smaller than 0, the nth symbol of the received signal is-1 or 0.

8. An operation method of a detection circuit comprises the following steps:

generating a received signal by a symbol detection circuit according to a received virtual noise sequence corresponding to a virtual noise sequence;

generating a plurality of first operation values according to a plurality of first operation symbols of the virtual noise sequence and a plurality of second operation symbols of the received signal through an operation circuit, and generating a second operation value according to the first operation values, wherein if one symbol of the virtual noise sequence and an adjacent symbol are the same, the symbol is one of the first operation symbols, and the second operation symbols respectively correspond to the first operation symbols; and

and generating a comparison result by a comparison circuit according to the second operation value and a threshold, wherein the comparison result is used for judging whether the detection circuit correctly receives the virtual noise sequence.

9. The method of claim 8, wherein generating the received signal by the symbol detection circuit according to the received virtual noise sequence comprises:

when the nth symbol of the received virtual noise sequence is equal to or greater than 0, the nth symbol of the received signal is generated by the symbol detection circuit and is + 1.

10. The method of claim 8, wherein generating the received signal by the symbol detection circuit according to the received virtual noise sequence comprises:

when the nth symbol of the received virtual noise sequence is smaller than 0, the nth symbol of the received signal is generated by the symbol detection circuit and is-1 or 0.