CN112422207A - Radio frequency test circuit system based on zero-frequency direct conversion - Google Patents
Radio frequency test circuit system based on zero-frequency direct conversion Download PDFInfo
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- CN112422207A CN112422207A CN202011388890.XA CN202011388890A CN112422207A CN 112422207 A CN112422207 A CN 112422207A CN 202011388890 A CN202011388890 A CN 202011388890A CN 112422207 A CN112422207 A CN 112422207A
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Abstract
The invention discloses a radio frequency test circuit system based on zero frequency direct conversion, which comprises a radio frequency front end module, an IQ demodulator, a two-channel low-pass filter, a two-channel analog-to-digital converter, a sampling clock, a two-channel parallel interface digital signal processor, and a frequency synthesizer, wherein the IQ demodulator is connected with the two-channel parallel interface digital signal processor through the two-channel analog-to-digital converter; the radio frequency front-end module down-regulates a single-channel radio frequency signal into a double-channel fundamental frequency signal through an IQ demodulator and transmits the double-channel fundamental frequency signal to a double-channel low-pass filter; the two-channel low-pass filter filters the two-channel fundamental frequency signals, transmits the two-channel fundamental frequency signals to the two-channel analog-to-digital converter, and transmits digital signals to the two-channel parallel port digital signal processor; the sampling clock controls the sampling frequency of the double-channel analog-to-digital converter in real time; the frequency synthesizer controls the center frequency of the IQ demodulator. The invention aims to provide the radio frequency test circuit system based on zero-frequency direct conversion, which has the advantages of good balance, strong accuracy, high reliability and multiple functions, solves the problems of direct current offset and image signals, and is applied to the radio frequency test circuit system.
Description
Technical Field
The invention relates to the technical field of radio frequency circuits, in particular to a radio frequency test circuit system based on zero-frequency direct conversion.
Background
All devices that use radio frequency, microwave and millimeter wave radio signals for communication and detection purposes require conversion of the high frequency signals to a lower frequency "intermediate frequency" (IF) so that the analog-to-digital converter can digitally sample and convert them and then perform digital signal processing.
A conventional frequency conversion circuit is called a Super Heterodyne Receiver (Super Heterodyne Receiver). The working principle is as follows: the incoming signal of frequency F1 is mixed by a mixer (mixer) with a locally generated signal of frequency F2 (the so-called local oscillator signal) of a receiver to produce signals of frequencies F1-F2 and F1+ F2. By filtering, if F1-F2 is selected, we achieve the effect of reducing the F1 frequency to F1-F2.
All high-end broadband spectrum analyzers on the market use such a multistage superheterodyne receiver, which converts the high-frequency signal to the intermediate frequency one stage at a time. Each stage of conversion requires a fine filtering design to shield various image signals and local oscillator signal leakage, etc. The design of a frequency spectrograph with ultra-wide band, continuously adjustable frequency, high signal-to-noise ratio and low stray signals always has the investment of high cost and large volume.
Another method of frequency conversion is a zero-IF direct conversion receiver (zero-IF direct conversion receiver). The principle is to split the incoming signal of center frequency F1 into two (one pair of) signals. The pair of signals passes through a pair of mixers. The local oscillator frequencies of the pair of mixers are the same (which may be the same as the frequency F1 of the incoming signal), but the phases are 90 degrees apart. Mathematically, it can be understood that: if one local oscillator signal is a cosine signal, the other local oscillator signal is a negative sine signal. The zero frequency conversion is the perfect mathematical conversion, and converts the high frequency band-pass signal into a pair of fundamental frequency complex signals at one time, thereby greatly reducing the design difficulty, cost and volume of the radio frequency circuit and the like. In many consumer communication devices, this zero frequency transition is almost the only option.
However, there is no free lunch in the world. Any method has its advantages and its disadvantages. Such zero frequency conversion requires that the pair of signal paths maintain strict amplitude and phase equality equalization. The pair of local oscillator signals must also maintain a strict 90 degree phase difference. In practice, however, any practical chip or circuit cannot guarantee strict equalization. The consequence of these imbalance problems is the generation of image signals, with signals above the center frequency being mapped below the center frequency and signals below the center frequency being mapped above the center frequency. This signal distortion is unacceptable for high-end spectrum analyzers. In addition, the zero-frequency dc component in the converted baseband signal corresponds to the center frequency in the original rf signal, which is useful information, but all high-speed analog-to-digital converters have the problem of dc conversion offset, and the converted digital signal cannot accurately express the center frequency component in the original rf signal. Therefore, the zero-frequency direct conversion method has not been applied to the design of the high-end spectrometer.
Chinese patent application No. 201210530318.1, application date: 12/10/2012, open day: year 2014, 18/06/18, with patent names: the invention relates to the field of detection, in particular to a spectrum analyzer with a zero frequency suppression function. Wherein, the frequency conversion device is arranged; the frequency conversion device comprises: the device comprises a local oscillation signal generating circuit, a mixing circuit, a phase shifting circuit and an intermediate frequency amplifying and filtering circuit; the frequency mixing circuit is used for mixing the local oscillation signal generated by the local oscillation signal generating circuit with the radio frequency signal and outputting the mixed signal to the intermediate frequency output end; the phase shift circuit includes: a phase shifter, a first directional coupler, and a second directional coupler; the first directional coupler couples the local oscillator signal to the phase shifter, and after the phase shifter outputs the reverse local oscillator signal, the second directional coupler couples the reverse local oscillator signal to the intermediate frequency output end. The spectrum analyzer provided by the embodiment of the invention can eliminate or reduce local oscillator leakage signals, thereby reducing local oscillator leakage and improving background noise near zero frequency. The intermediate frequency amplifier in the subsequent intermediate frequency amplifying and filtering circuit can not generate compression, and an Analog Digital Collector (ADC) positioned at the rear stage can not overflow.
Although the above patent document discloses a spectrum analyzer having a zero-frequency suppression function, the spectrum analyzer lacks a zero-frequency conversion circuit, has poor circuit balance, and cannot solve the dc conversion offset problem.
Disclosure of Invention
In view of this, the present invention provides a radio frequency test circuit system based on zero frequency direct conversion, which has good equalization, solves the problems of dc offset and image signal, and has strong accuracy, high reliability and multiple functions.
In order to realize the purpose of the invention, the following technical scheme can be adopted:
a radio frequency test circuit system based on zero frequency direct conversion comprises a radio frequency front end module, an IQ demodulator, a two-channel low-pass filter, a two-channel analog-to-digital converter, a sampling clock, a two-channel parallel interface digital signal processor and a frequency synthesizer;
the radio frequency front end module is used for receiving radio frequency signals; the IQ demodulator is used for down-regulating the single-channel radio frequency signal into a double-channel fundamental frequency signal; the two-channel low-pass filter is used for filtering a high-frequency image signal; the two-channel analog-to-digital converter is used for converting an analog signal into a digital signal for the IQ fundamental frequency signal; the sampling clock is used for adjusting the sampling frequency of the double-channel analog-to-digital conversion in real time; the digital signal processor of the double-channel parallel interface digital signal processor is used for processing digital signals; the frequency synthesizer is used for adjusting the center frequency of the IQ demodulator;
the radio frequency front-end module down-regulates a single-channel radio frequency signal into a double-channel fundamental frequency signal through an IQ demodulator and transmits the double-channel fundamental frequency signal to the double-channel low-pass filter; the two-channel low-pass filter filters the two-channel base frequency signals after down regulation, transmits the two-channel base frequency signals to the two-channel analog-to-digital converter for analog-to-digital conversion, and directly outputs the converted digital signals to the signal processor through the two-channel parallel interface digital signal processor; the sampling clock controls the sampling frequency of the double-channel analog-to-digital converter in real time; the frequency synthesizer controls the center frequency of the IQ demodulator.
The radio frequency front-end module down-regulates a single-channel radio frequency signal into a double-channel fundamental frequency signal through an IQ demodulator and transmits the double-channel fundamental frequency signal to the double-channel low-pass filter; the two-channel low-pass filter filters the two-channel base frequency signals after down regulation, transmits the two-channel base frequency signals to the two-channel analog-to-digital converter for analog-to-digital conversion, and transmits the converted digital signals to the digital signal processor of the two-channel parallel interface digital signal processor; the sampling clock controls the sampling frequency of the double-channel analog-to-digital converter in real time; the frequency synthesizer controls the center frequency of the IQ demodulator.
The IQ demodulator is a high-linearity ultra-wideband IQ demodulator.
The dual-channel low-pass filter is a dual-channel low-pass numerical control filter.
The double-channel analog-to-digital converter is a double-channel numerical control analog-to-digital converter.
The sampling clock is a variable digital-to-analog conversion sampling clock.
The dual channel parallel interface digital signal processor includes a multi-core floating point digital signal processor having a dual channel parallel interface digital signal processor.
And the digital signal processor of the dual-channel parallel interface digital signal processor transmits the real-time processing result to the PC or the cloud network through the Ethernet.
The sampling clock comprises a reference clock source circuit which is also a reference clock of the frequency synthesizer.
The invention has the beneficial effects that: 1) the invention successfully uses the most effective zero-frequency direct conversion method to the design of a high-precision radio frequency test instrument; 2) in the design of a hardware signal flow, the invention keeps the balance and the synchronism of the optimal IQ signal and perfectly solves the problem of the inherent mirror image signal of an unbalanced instrument in the zero-frequency direct conversion; 3) various clock synchronicity adopted by the invention enables a software algorithm to cleanly eliminate the problems of mirror image signals and direct current offset; 4) the invention creates a design model of the most portable and effective high-end test instrument.
Drawings
FIG. 1 is a block diagram of a radio frequency test circuit system based on zero frequency direct conversion according to an embodiment of the present invention;
fig. 2 is a block diagram of a circuit of a radio frequency test circuit system based on zero frequency direct conversion according to another embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and embodiments thereof.
Example 1
Referring to fig. 1 and 2, the radio frequency test circuit system based on zero frequency direct conversion includes a radio frequency front end module 1, an IQ demodulator 2, a dual-channel low pass filter 3, a dual-channel analog-to-digital converter 4, a sampling clock 6, a dual-channel parallel interface digital signal processor 7, wherein the IQ demodulator 2 further includes a frequency synthesizer 5;
the radio frequency front end module 1 is used for receiving radio frequency signals; the IQ demodulator 2 is used for down-regulating a single-channel radio frequency signal into a dual-channel fundamental frequency signal; the dual-channel low-pass filter 3 is used for filtering high-frequency image signals; the two-channel analog-to-digital converter 4 is used for converting an analog signal into a digital signal for the IQ fundamental frequency signal; the sampling clock 6 is used for adjusting the sampling frequency of the double-channel analog-to-digital conversion in real time; the dual-channel parallel interface digital signal processor 7 is used for digital signal processing; the frequency synthesizer 5 is used for adjusting the center frequency of the IQ demodulator 2;
the radio frequency front-end module 1 down-regulates a single-channel radio frequency signal into a double-channel fundamental frequency signal through an IQ demodulator 2 and transmits the double-channel fundamental frequency signal to the double-channel low-pass filter 3; the two-channel low-pass filter 3 filters the two-channel base frequency signals after down regulation, transmits the two-channel base frequency signals to the two-channel analog-to-digital converter 4 for analog-to-digital conversion, and transmits digital signals to the two-channel parallel interface digital signal processor 7 for digital signal processing; the sampling clock 6 controls the sampling frequency of the dual-channel analog-to-digital converter 4 in real time; the frequency synthesizer 5 controls the center frequency of the IQ demodulator 2.
Referring to fig. 2, in the present embodiment, the rf front-end module 1 preferably includes an rf signal input circuit 11, an overload protection circuit 12, a preamplifier circuit 13, and a pre-selection filter 14; the radio frequency signal input circuit 11 amplifies the radio frequency signal through the overload protection circuit 12 and the pre-amplification circuit 13, and inputs the amplified signal to the pre-selection filter 14; the pre-selection filter 14 filters the amplified signal and inputs the filtered signal to the rf front-end module 1.
In this embodiment, preferably, the IQ demodulator 2 is a high-linearity ultra-wideband IQ demodulator. The IQ demodulator 2 is a core part of zero-frequency conversion, and further preferably, the IQ demodulator 2 is a chip of type LTC 5594.
The IQ-demodulator 2 further comprises a frequency synthesizer 5; the frequency synthesizer 5 provides the local oscillator signal to the IQ demodulator 2, the frequency synthesizer 5 is a fractional frequency synthesizer (fractional frequency synthesizer) with fine tuning frequency; preferably, the frequency synthesizer 5 is a chip with model number ADF4355-3(ver-A) or LMX 2592 (ver-B); the fine adjustment of the output frequency of the frequency synthesizer 5 is a necessary condition for eliminating the problems of image signals and direct current offset by a subsequent software algorithm.
In this embodiment, the dual-channel digital control low-pass filter 3 is designed to ensure IQ signal equalization to the maximum extent, and the dual-channel filter is optimally designed, and the dual-channel analog-to-digital converter 4 ensures optimal IQ equalization when performing analog-to-digital conversion on an IQ fundamental frequency signal; the two-channel low-pass filter 3 can be an ADRF6516 chip or an HMC900LP5E chip. The dual-channel low-pass filter 3 provides a basis for the adjustability of the filter bandwidth for variations in the back-end sampling frequency.
In this embodiment, preferably, the dual-channel low-pass filter 3 is a dual-channel low-pass digitally controlled filter.
In this embodiment, preferably, the dual-channel analog-to-digital converter 4 is a dual-channel digitally-controlled analog-to-digital converter.
In order to further ensure the equalization of the IQ signals in terms of amplitude and phase, the dual-channel analog-to-digital converter 4 in this embodiment employs a dual-channel analog-to-digital converter. The design of the invention ensures the absolute synchronization and the balance of two signals on a sampling clock and a data output interface.
In this embodiment, the dual-channel analog-to-digital converter 4 adopts a chip with parallel port output, 16-bit, high linearity and instrument level, and a chip with model number of LTC 2183/4/5.
The dual-channel analog-to-digital converter 4 ensures optimal IQ balance when performing analog-to-digital conversion on IQ base frequency signals.
In this embodiment, preferably, the dual-channel analog-to-digital converter 4 is a dual-channel digitally-controlled analog-to-digital converter.
In this embodiment, the sampling clock 6 is a variable digital-to-analog conversion sampling clock.
In this embodiment, the sampling clock 6 may drive the sampling clock signal of the dual channel analog-to-digital converter 4, which is a variable clock generator or clock divider.
In this embodiment, preferably, the sampling clock 6 includes a reference clock source circuit 9, and the reference clock source circuit 9 is used to provide a reference standard for adjusting the clock frequency of the sampling clock.
The sampling clock generator 6 and the frequency synthesizer 5 are both based on a unified reference clock source. The clock synchronism is also a precondition for correcting the IQ signal imbalance algorithm and eliminating the DC offset; the sampling clock 6 and the frequency synthesizer 5 adopt the same reference clock source circuit to ensure more accurate image signal and DC offset elimination in the subsequent digital field.
The sampling clock frequency can be changed along with the change of application scenes in real time, but the output of the analog-to-digital converter and the clock are never closed after the instrument is started, so that the absolute synchronism of the IQ signal in time can be ensured in any application scene. The sampling frequency is variable, and the bandwidth of a variable filter is matched, so that the frequency spectrograph can process the requirements of large resolution, high speed and fine resolution.
The speed of a conventional scanning spectrometer is proportional to the inverse of the square of the resolution, for example, when the resolution is adjusted from 10KHz to 1KHz, the speed is reduced by a factor of 100. The spectrometer of the invention has the speed only related to the physical sampling time of the original data, and the fine resolution does not increase the additional processing burden. From the user perspective, the spectral analysis speed is hardly affected by the resolution.
In this embodiment, the analog-to-digital conversion uses a dual-channel analog-to-digital converter 4, and a sampling clock 6 provides a real-time variable sampling frequency.
In this embodiment, preferably, the dual-channel parallel interface digital signal processor 7 may select to have an ADC parallel port output.
In this embodiment, the dual-channel parallel interface digital signal processor 7 of the ADC does not need to be externally connected with an FPGA or DDC; the two-channel low-pass filter 3 filters the two-channel base frequency signals after down regulation, and transmits the two-channel base frequency signals to the two-channel analog-to-digital converter 4 for analog-to-digital conversion, and the converted two-channel digital signals can be directly connected with the digital signal processor through the two-channel parallel interface digital signal processor 7;
further, preferably, the two-channel parallel interface digital signal processor 7 comprises a multi-core floating point digital signal processor 71 having a two-channel parallel interface.
The dual-channel parallel interface digital signal processor 7 transmits the real-time processing result to the PC or the cloud network 73 through the ethernet 72.
The dual-channel parallel interface digital signal processor 7 comprises a multi-core floating point digital signal processor 71; the multi-core floating-point signal processor 71 has a dual-channel parallel port, and can be directly connected to the output of the dual-channel analog-to-digital converter 4 without an additional FPGA or DDC component. The structure keeps the precision of the original signal as much as possible, and the IQ signal imbalance correction and DC offset elimination are realized by adding a 64-bit floating-point complex operation function. The direct data interface also ensures the real-time performance and the broadband processing capacity of the instrument to the maximum extent. In the data driving software based on the dual-channel parallel port DMA, a permanent and uninterrupted design method is also adopted to ensure the absolute synchronism of the IQ digital signal when the sampling frequency and the application scene are changed.
The used dual-channel parallel interface digital signal processor 7 is provided with an EMAC (enhanced Media Access controller) and is convenient to directly contact with a back-end PC (personal computer), a single board computer or a cloud network through an Ethernet interface. The framework enables the instrument to be suitable for both short-range portable instrument design and cloud network control distributed instrument design. The embedded multi-core signal processor ensures the real-time and powerful function of the instrument and enables the core testing function not to depend on the uncertainty of a back-end PC or a network and the like.
The present invention can achieve the following effects: the one-time analysis bandwidth is as high as 100MHz, the capture rate of microsecond-level transient signals is 100%, the scanning frequency of 280GHz/s can be reached during broadband scanning, and the mirror frequency spectrum and the direct current offset are eliminated to the bottom of noise cleanly. The simplicity of the radio frequency part makes our invention a design paradigm for high-end real-time wideband FFT spectrum analyzers.
The invention also provides a precise vector analysis function for the frequency spectrograph. The invention not only has high-performance spectrum analysis function, but also has decoding analysis function of various communication signals (3G-WCDMA,4G-LTE, NB-IoT, 5G-NR and the like).
The frequency conversion (converting the rf signal to a lower frequency) described in the present invention is an essential part of the rf circuit design. Zero frequency direct conversion is the simplest and elegant method for frequency conversion, and is widely used in wireless communication equipment, but has not been used in high-end test instruments, because zero frequency conversion has two fatal problems: IQ signal imbalance problems and dc offset problems.
The IQ signal imbalance can cause the problem of signal spectrum mirror image, and the problem of direct current offset influences the test of the corresponding central frequency point of the original radio frequency signal. The invention provides an optimal hardware design for reducing IQ imbalance effect, and realizes a high-performance broadband real-time FFT spectrum analyzer design based on zero frequency conversion by matching with a unique IQ imbalance and direct current offset correction method.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
Claims (8)
1. A radio frequency test circuit system based on zero frequency direct conversion is characterized in that: the system comprises a radio frequency front end module, an IQ demodulator, a two-channel low-pass filter, a two-channel analog-to-digital converter, a sampling clock, a two-channel parallel interface digital signal processor, and a frequency synthesizer;
the radio frequency front end module is used for receiving radio frequency signals; the IQ demodulator is used for down-regulating the single-channel radio frequency signal into a double-channel fundamental frequency signal; the two-channel low-pass filter is used for filtering a high-frequency image signal; the two-channel analog-to-digital converter is used for converting an analog signal into a digital signal for the IQ fundamental frequency signal; the sampling clock is used for adjusting the sampling frequency of the double-channel analog-to-digital conversion in real time; the digital signal processor of the double-channel parallel interface digital signal processor is used for processing digital signals; the frequency synthesizer is used for adjusting the center frequency of the IQ demodulator;
the radio frequency front-end module down-regulates a single-channel radio frequency signal into a double-channel fundamental frequency signal through an IQ demodulator and transmits the double-channel fundamental frequency signal to the double-channel low-pass filter; the two-channel low-pass filter filters the two-channel base frequency signals after down regulation, transmits the two-channel base frequency signals to the two-channel analog-to-digital converter for analog-to-digital conversion, and transmits the converted digital signals to the digital signal processor of the two-channel parallel interface digital signal processor; the sampling clock controls the sampling frequency of the double-channel analog-to-digital converter in real time; the frequency synthesizer controls the center frequency of the IQ demodulator.
2. The zero-frequency direct conversion based radio frequency test circuitry of claim 1, wherein: the radio frequency front end module comprises a radio frequency signal input circuit, an overload protection circuit, a pre-amplification circuit and a pre-selection filter; the radio frequency signal input circuit amplifies a radio frequency signal through the overload protection circuit and a pre-amplification circuit and then inputs the amplified signal to the pre-selection filter; the front-end filter filters the amplified signal and inputs the filtered signal to the radio frequency front-end module.
3. The zero-frequency direct conversion based radio frequency test circuitry of claim 1 or 2, wherein: the IQ demodulator is a high-linearity ultra-wideband IQ demodulator.
4. The zero-frequency direct conversion based radio frequency test circuitry of claim 1 or 2, wherein: the dual-channel low-pass filter is a dual-channel low-pass numerical control filter.
5. The zero-frequency direct conversion based radio frequency test circuitry of claim 1 or 2, wherein: the sampling clock is a variable digital-to-analog conversion sampling clock.
6. The zero-frequency direct conversion based radio frequency test circuitry of claim 1 or 2, wherein: the dual channel parallel interface digital signal processor includes a multi-core floating point digital signal processor having a dual channel parallel interface digital signal processor.
7. The zero-frequency direct conversion based radio frequency test circuitry of claim 7, wherein: and the two-channel parallel interface digital signal processor transmits the real-time processing result to the PC or the cloud network through the Ethernet.
8. The zero-frequency direct conversion based radio frequency test circuitry of claim 1, wherein: the sampling clock comprises a reference clock source circuit which is used for providing a reference standard for adjusting the clock frequency of the sampling clock.
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