CN112422122A

CN112422122A - Feedback regulation type oscillator

Info

Publication number: CN112422122A
Application number: CN202011219344.3A
Authority: CN
Inventors: 胡毅; 唐晓柯; 肖衍; 马永旺; 甘杰; 李振国; 金鑫; 张帆
Original assignee: State Grid Corp of China SGCC; State Grid Information and Telecommunication Co Ltd; State Grid Zhejiang Electric Power Co Ltd; Beijing Smartchip Microelectronics Technology Co Ltd
Current assignee: State Grid Corp of China SGCC; State Grid Information and Telecommunication Co Ltd; State Grid Zhejiang Electric Power Co Ltd; Beijing Smartchip Microelectronics Technology Co Ltd
Priority date: 2020-11-04
Filing date: 2020-11-04
Publication date: 2021-02-26
Anticipated expiration: 2040-11-04
Also published as: CN112422122B

Abstract

The invention provides a feedback regulation type oscillator, and belongs to the technical field of integrated circuits. The oscillator includes: the current source circuit is used for outputting three paths of bias currents; the charge and discharge circuit is used for charging and discharging according to the first path of bias current, and converting a correspondingly generated frequency signal into a voltage signal and outputting the voltage signal; the operational amplifier circuit is used for responding to the second path of bias current to start working so as to amplify and output the voltage signal; the current control oscillator is used for converting the amplified voltage signal into a current signal according to the third path of bias current, converting the current signal into a clock signal in a frequency form and outputting the clock signal; and the digital logic circuit is used for converting the clock signal into a clock control signal and outputting the clock control signal and feeding the clock control signal back to the charge and discharge circuit and the current source circuit. The invention can meet the requirements of any one or more of low voltage, low power consumption and high precision.

Description

Feedback regulation type oscillator

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a feedback regulation type oscillator.

Background

Oscillators (OSCs) are a major part of many electronic systems and are widely used in communications and various electronic devices, and their application ranges include clock generation in microprocessors, carrier synthesis in cellular phones, and the like. However, the inventor of the present application finds that the conventional OSC circuit has the following two problems in implementing the present invention:

in the first aspect, with the development of integrated circuits, electronic systems have increasingly high requirements for low voltage, low power consumption, high precision characteristics, and the like of oscillator circuits, and existing oscillators either fail to take into account the characteristics, or need to add large-scale peripheral circuits, or have poor detail problem handling, and cannot solve the problems of frequency deviation and the like caused by current source imbalance and limited loop regulation capability, and therefore cannot completely meet the design requirements of OSC circuits.

In the second aspect, because the period of the OSC circuit is related to delay, and the delay time is greatly affected by process, temperature, bias signals, etc., the circuit accuracy is greatly reduced, and the accuracy becomes worse as the output frequency increases. For example, in the simulation of the full process, the full temperature region and the full voltage region, the OSC output frequency deviation is difficult to be controlled within ± 10%, or more specifically within ± 5%.

Therefore, the current OSC circuit structure cannot satisfy the requirements of low voltage, low power consumption and/or high precision.

Disclosure of Invention

It is an object of embodiments of the present invention to provide a feedback-regulated oscillator that at least partially solves the above mentioned technical problem.

In order to achieve the above object, an embodiment of the present invention provides a feedback adjustment type oscillator, including: the current source circuit is used for outputting three paths of bias currents through three output ends respectively; the charging and discharging circuit is connected with the first path of bias current output by the current source circuit, is used for charging and discharging according to the first path of bias current, and converts frequency signals generated correspondingly by charging and discharging into voltage signals and outputs the voltage signals; the operational amplifier circuit is connected with a second path of bias current output by the current source circuit and a voltage signal output by the charge and discharge circuit, and is used for responding to the second path of bias current to start working so as to amplify and output the voltage signal; the current control oscillator is connected with a third path of bias current output by the current source circuit and an amplified voltage signal output by the operational amplifier circuit, and is used for converting the amplified voltage signal into a current signal according to the third path of bias current, converting the current signal into a clock signal in a frequency form and outputting the clock signal; and the digital logic circuit is connected with a clock signal output by the current control oscillator, is used for converting the clock signal into a clock control signal and outputting the clock control signal for application, and feeds the clock control signal back to the charging and discharging circuit and the current source circuit so as to respectively control the charging and discharging speed of the charging and discharging circuit and the bias current output by the current source circuit.

Further, the feedback adjustment type oscillator further includes: the counter is arranged between the output end of the digital logic circuit and the current source circuit and is used for counting the clock control signals and controlling the current source circuit to output bias current according to a counting result; and/or the switch circuit is arranged between the output end of the digital logic circuit and the charging and discharging circuit, and comprises a plurality of MOS tubes, and the switch circuit is used for controlling the conduction or the disconnection of different MOS tubes according to a time sequence control signal which is configured in advance and aims at each MOS tube so as to control the charging and discharging speed of the charging and discharging circuit by transmitting the clock control signal.

Further, the counter for controlling the current source circuit to output the bias current according to the counting result includes: and when the number of the clock control signals counted by the counter exceeds a first preset clock number, controlling the current source circuit to reduce the output second path of bias current, wherein the first preset clock number is the number of the clock control signals correspondingly output when the feedback regulation type oscillator works stably.

Further, the first output end of the current source circuit comprises a first sub-output end and a second sub-output end, and the charge and discharge circuit comprises a capacitor C branch for realizing charge and discharge and a resistor R branch used as a charge and discharge reference. Further, the feedback adjustment type oscillator further includes: a first selection switch SW1 provided at a first sub-output terminal of the current source circuit; and a second selection switch SW2 provided at a second sub-output terminal of the current source circuit; wherein the first selection switch SW1, the second selection switch SW2, the input terminal of the resistor Rbranch and the input terminal of the capacitor Cbranch are connected in an interleaving manner, so that the current source circuit can provide bias current to the corresponding resistor Rbranch or the capacitor Cbranch through the first sub-output end or the second sub-output end in two different time periods in an exchanging manner; the control ends of the first selection switch SW1 and the second selection switch SW2 are connected to the clock control signal output by the digital logic circuit, so as to operate under the control of the clock control signal.

Further, the counter is further configured to: when the number of clock control signals counted by the counter is less than a second preset number of clocks, controlling the first selection switch SW1 and the second selection switch SW2 based on the clock control signals so that the current source circuit does not perform the switching between the first sub-output terminal and the second sub-output terminal when outputting the first path of bias current to the charge and discharge circuit, wherein the second preset number of clocks is the number of clock control signals correspondingly output when the feedback regulation type oscillator has not yet reached the working voltage.

Further, the switch circuit is a bootstrap switch circuit, and the bootstrap switch circuit includes: a fifth capacitor C5, having one end connected to a first timing control signal outp, and the other end connected to the drain of the first MOS transistor M1, where the first timing control signal outp is the clock control signal output by the digital logic circuit; a source electrode of the first MOS transistor M1 is connected to a working power supply, a gate electrode of the first MOS transistor M1 is connected to the first timing control signal outp, and a drain electrode of the first MOS transistor M2 is connected to a drain electrode of the second MOS transistor M2; a drain of the second MOS transistor M2 is connected to the drain of the first MOS transistor M1, a gate of the second MOS transistor M2 is connected to the second timing control signal outn, and a source of the second MOS transistor M2 is connected to the drain of the third MOS transistor M3; a drain of the third MOS transistor M3 is connected to the source of the second MOS transistor M2, a gate of the third MOS transistor M3 is connected to the third timing control signal outn _ d, and a source of the third MOS transistor M3 is grounded; a fourth MOS transistor M4 connected in parallel to the capacitor C branch, wherein a source and a drain are respectively connected to two ends of the capacitor C branch, and a gate is connected to a second timing control signal outn; a fifth MOS transistor M5, which is connected in series with the capacitor C branch, and has a source and a drain connected in series with the capacitor C branch, and a gate connected to the source of the second MOS transistor M2; the first timing control signal outp, the second timing control signal outn and the third timing control signal outn _ d are configured to control the respective corresponding MOS transistors such that the fourth MOS transistor M4 and the fifth MOS transistor M5 are not turned on simultaneously.

Further, the current controlled oscillator includes: the input end of the current conversion module is the input end of the current control oscillator, and the current conversion module is used for converting the voltage signal output by the operational amplifier circuit into a current signal and outputting the current signal in combination with the third path of bias current output by the current source circuit; and the input end of the clock conversion module is connected with the current conversion module and is used for converting the current signal output by the current conversion module into a clock signal in a frequency form and outputting the clock signal.

Further, the current transition module includes: a sixth MOS transistor M6, a drain and a gate of which are used as input terminals of the current conversion module to respectively access the third bias current output by the current source circuit and the voltage signal output by the operational amplifier circuit, and a source of which is grounded; the gates of the seventh MOS transistor M7 and the eighth MOS transistor M8 are connected to the drain of the sixth MOS transistor M6, the sources are both connected to a working power supply, the drain of the seventh MOS transistor M7 is connected to the gate thereof, and the drain of the eighth MOS transistor M8 is connected to the drain of the ninth MOS transistor M9; the gates of the ninth MOS transistor M9 and the tenth MOS transistor M10 are connected to the drain of the eighth MOS transistor M8, the sources are grounded, the drain of the ninth MOS transistor M9 is connected to the gate thereof, and the drain of the tenth MOS transistor M10 is used as the output terminal of the current conversion module.

Further, the clock transition module includes: the gates of the eleventh MOS transistor M11 and the twelfth MOS transistor M12 are connected and serve as the input end of the clock transition module, the sources are both connected to a working power supply, the drain of the eleventh MOS transistor M11 is connected to the gate thereof, and the drain of the twelfth MOS transistor M12 is connected to the first control end of an inverter unit; the gates of the thirteenth MOS transistor M13 and the fourteenth MOS transistor M14 are connected, the sources are grounded, the drain of the thirteenth MOS transistor M13 is connected to the second control end of the inverter unit, and the drain of the fourteenth MOS transistor is connected to the drain of the fifteenth MOS transistor M15; the inverter unit is also provided with an input end and an output end A which are connected, and the output end A of the inverter unit is connected to the grid electrode of a seventeenth MOS tube M17; the gates of the fifteenth MOS transistor M15 and the sixteenth MOS transistor M16 are connected, the sources are both connected to the working power supply, the drain of the fifteenth MOS transistor M15 is connected to the gate thereof, and the drain of the sixteenth MOS transistor M16 is connected to the drain of the seventeenth MOS transistor M17 and serves as the output end of the clock conversion module; and a seventeenth MOS transistor M17 having a gate connected to the output terminal a of the inverter unit, a drain serving as the output terminal of the clock transition module, and a source connected to ground.

Further, the sizes of the twelfth MOS transistor M12 and the thirteenth MOS transistor M13 are different.

Further, the width of the thirteenth MOS transistor M13 is greater than the width of the twelfth MOS transistor M12.

Further, the clock transition module further includes: a seventh capacitor C7, having one end connected to the gates of the fifteenth MOS transistor M15 and the sixteenth MOS transistor M16, and the other end connected between the gate of the seventeenth MOS transistor M17 and the output terminal a of the inverter unit.

Through the technical scheme, the current-controlled current control oscillator is designed, so that the output frequency range of the oscillator can be widened, the accuracy of the oscillator is improved, the power consumption of the oscillator can be reduced, and the oscillator can work under lower power supply voltage. In addition, the invention also introduces a counter to control the work of the current source circuit and the charge-discharge circuit, improves the precision of the oscillator, reduces the power consumption of the oscillator, greatly improves the precision of the oscillator, reduces the power consumption of the oscillator and enables the oscillator to work under lower power voltage by designing a switch circuit controlled by a special time sequence and a current controlled digital logic circuit.

Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:

fig. 1 is a schematic structural diagram of a feedback regulation type oscillator of an embodiment of the present invention;

FIG. 2 is a signal transfer schematic of the feedback-regulated oscillator of FIG. 1;

fig. 3 is a schematic diagram of a feedback-regulated oscillator in a preferred embodiment of the invention;

FIG. 4 is an exemplary overall circuit layout of a feedback-regulated oscillator of an embodiment of the present invention;

FIG. 5 is a timing diagram of control signals of a bootstrapped switch circuit in an example of an embodiment of the invention; and

fig. 6 is a circuit schematic of a current controlled oscillator in an example of an embodiment of the present invention.

Description of the reference numerals

100. A current source circuit; 200. a charge and discharge circuit; 300. an operational amplifier circuit; 400. a current controlled oscillator; 500. a digital logic circuit; 600. a counter; 700. a switching circuit;

410. a current transformation module; 420. a clock transition module.

Detailed Description

The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.

Fig. 1 is a schematic structural diagram of a feedback adjustment type oscillator according to an embodiment of the present invention. It should be noted that the short term "oscillator" mentioned hereinafter refers to the feedback regulation type oscillator herein, and it can also refer to the whole circuit related to the oscillator, and the current control oscillator, the voltage control oscillator and the related sub-circuit will be described in full terms.

As shown in fig. 1, the feedback adjustment type oscillator may include the following parts:

1) the current source circuit 100 is used for outputting three bias currents, namely IBIAS1, IBIAS2 and IBIAS3, through three output ends respectively.

2) The charging and discharging circuit 200 is connected to the first bias current IBIAS1 output by the current source circuit 100, and is configured to perform charging and discharging according to the first bias current IBIAS1, and convert a frequency signal generated by the charging and discharging into a voltage signal and output the voltage signal. For example, the charging and discharging circuit 200 is, for example, an RC circuit, and the RC circuit includes a capacitor C branch (abbreviated as C branch) for realizing charging and discharging and a resistor R branch (abbreviated as R branch) used as a charging and discharging reference, where the R branch provides a reference voltage VR for the lower-stage operational amplifier circuit 300, and the C branch can alternately complete charging and discharging processes under the control of, for example, a common switch, and use the voltage thereon as the input VC at the other end of the operational amplifier circuit 300.

3) And the operational amplifier circuit 300 is connected with the second bias current IBIAS2 output by the current source circuit and the voltage signal output by the charging and discharging circuit, and is used for starting to work in response to the second bias current to amplify and output the voltage signal. For example, the operational amplifier circuit 300, which receives the upper RC circuit, is a comparator, which performs difference amplification on the voltages VR and VC to obtain a voltage V0.

4) And a current controlled oscillator (hereinafter also referred to as ICO)400, which is connected to the third bias current IBIAS3 output by the current source circuit 100 and the amplified voltage signal V0 output by the operational amplifier circuit, and is configured to convert the amplified voltage signal V0 into a current signal according to the third bias current IBIAS3, and convert the current signal into a clock signal in a frequency form and output the clock signal. It should be noted that the structure, principle and advantages of the current controlled oscillator 400 will be described with reference to specific circuit diagrams, and will not be described herein again.

For the charging and discharging circuit 200, the operational amplifier circuit 300, and the current controlled oscillator 400, taking an RC circuit as an example, the specific working process can be described as follows: when VR is larger than VC, the electric charge obtained by the capacitor C through the current source circuit is smaller than the electric charge discharged by the oscillator through the branch of the capacitor C, the output voltage of the operational amplifier circuit 300 is reduced, the current value obtained by ICO is reduced, the charging time of the ICO circuit is prolonged, the output clock frequency is reduced, after the electric charge is fed back to the RC circuit through the circuit, more electric charge can be charged on the capacitor C, so that VC is increased, and the negative feedback effect is realized; when VR is less than VC, the electric charge obtained by the capacitor C through the current source circuit is larger than the electric charge discharged by the oscillator through the branch of the capacitor C, the output voltage of the operational amplifier circuit is increased, the current value obtained by ICO is increased, the charging time of the ICO circuit is shortened, the frequency of the output clock signal is increased, and after the electric charge is fed back to the RC circuit, the electric charge charged on the capacitor C is reduced, so that VC is reduced, and the negative feedback effect is realized. Accordingly, the RC circuit does not transition between the two states, which helps to ultimately form a continuous and frequency stable clock signal.

5) A digital logic circuit 500, which is connected to the clock signal output by the current controlled oscillator 400, and is used to convert the clock signal into a clock control signal CLKOUT and output the clock control signal for application, and feed back the clock control signal to the charge and discharge circuit 200 to control the charge and discharge speed of the charge and discharge circuit, and feed back the clock control signal to the current source circuit 100 to control the bias current output by the current source circuit. Such applications are, for example, clock generation in microprocessors, carrier synthesis in cellular telephones, etc.; in addition, the clock control signal CLKOUT is fed back through, for example, a normal switch to control the operation of the RC circuit, thereby implementing circuit feedback control. It should be noted that feedback control based on the clock control signal CLKOUT will be described below with reference to examples, and will not be described herein again. In addition, the digital logic circuit 500 for generating the control signal may be, for example, a combinational logic circuit or a sequential logic circuit, which is obvious to those skilled in the art and thus will not be described below.

In other embodiments, it may be proposed to use a voltage controlled oscillator (hereinafter also referred to as VCO) instead of the current controlled oscillator 400. However, in the VCO, when the voltage of the current source circuit 100 is low, the output range of the operational amplifier circuit 300 is narrow, and thus the control voltage range supplied to the VCO is narrow, so that the control voltage range in the VCO is too small, resulting in too small an output frequency range of the entire circuit, which will seriously deteriorate the accuracy of the feedback regulation type oscillator. Therefore, the current-controlled oscillator 400 is preferably adopted in the embodiment of the present invention, so that even if the output range of the operational amplifier circuit is narrow, the controllable current range is still wide, and therefore, the control current range supplied to the ICO circuit can still be wide, thereby expanding the output frequency range of the whole circuit and contributing to improving the accuracy of the oscillator.

Fig. 2 is a signal transfer schematic diagram of the feedback-regulated oscillator of fig. 1. Referring to fig. 2, in the whole circuit operation process, the charge and discharge circuit 200, the operational amplifier circuit 300, the current controlled oscillator 400, and the digital logic circuit 500 form a loop. Firstly, a frequency signal corresponding to the charge and discharge circuit 200 is changed into a voltage signal, the voltage signal is further changed into a current signal by the current control oscillator 400 after being amplified by the operational amplifier circuit 300, so that the conversion from voltage to current is realized, and then the current signal is changed into a frequency signal through the ICO, wherein the frequency signal is a required clock signal; the digital logic circuit 500 then converts the clock signal to a clock control signal to obtain CLKOUT. The clock control signal CLKOUT is directly output on one hand and is fed back to the charge/discharge control circuit 200 to control the charge/discharge speed of the charge/discharge circuit 200 on the other hand. It is understood that the clock control signal CLKOUT is controlled in frequency.

Further, in conjunction with fig. 1 and 2, although the embodiment of the present invention improves the accuracy of the oscillator by using an ICO instead of a VCO, it may have the following two drawbacks.

In a first aspect, for a current source circuit: when the oscillator is started, the bias current needs to be increased to meet the requirement of a feedback loop for searching and adjusting the working point of the current source circuit on the large bias current, but after the oscillator works normally, the requirement of the whole circuit on the large bias current is weakened. At this time, if the bias current requirement conditions during the start-up and normal operation of the oscillator are not treated differently, a large amount of power consumption will be consumed. In addition, mismatch and difference exist between the current source circuits IBIAS1a and IBIAS1b, and if special processing is not carried out, the precision of the whole circuit is reduced; and because the current source circuit provides bias for the RC circuit and the operational amplifier circuit at the same time, and the power-on speed of the operational amplifier circuit is often slower than the charging speed of the RC circuit, if special processing is not performed, the cooperative work among the current source circuit, the RC circuit and the operational amplifier circuit cannot be normally completed, so that the working state of the whole circuit is influenced, and even vibration is stopped.

In the second aspect, the common switch and the digital logic circuit have the risk of electric leakage, which greatly reduces the precision of the whole circuit and improves the power consumption of the whole circuit, especially when the output frequency is high. In addition, errors are also introduced in the on-off process of the ordinary switch, and the accuracy of the whole circuit is affected.

In view of the above, in either or both aspects, a feedback-regulated oscillator is proposed, which is more preferable than the one shown in fig. 1, and is shown in fig. 3. Fig. 3 is a schematic diagram of a feedback-regulated oscillator in a preferred embodiment of the present invention. As shown in fig. 3, the feedback-regulated oscillator may further include the following counter 600 and/or switching circuit 700:

and a counter 600, disposed between the output terminal of the digital logic circuit 500 and the current source circuit 100, for counting the clock control signal and controlling the current source circuit 100 to output a bias current according to a counting result. The control of IBIAS1 and IBIAS2 by counter 600 will be described below with reference to examples, and will not be described herein again.

The switching circuit 700 is disposed between the output terminal of the digital logic circuit 500 and the charging and discharging circuit 200, and includes a plurality of MOS transistors, and is configured to control the conduction or the disconnection of different MOS transistors according to a pre-configured timing control signal for each MOS transistor, so as to control the charging and discharging speed of the charging and discharging circuit by transmitting the clock control signal. In the embodiment of the present invention, the MOS transistors in each circuit are all exemplified by MOS transistors, but the embodiment of the present invention is not limited to use of other types of MOS transistors.

The circuit structures and functions of the counter, the switch circuit, and the ICO will be described one by one in conjunction with the example of fig. 4.

Fig. 4 is a diagram of the overall circuit design of an example of the feedback-regulated oscillator according to the embodiment of the present invention, and for the convenience of the following description of the counter, the switching circuit, and the ICO, the circuit design of the charge and discharge circuit 200 will be described first. In this example, for purposes of clarity of the drawing, reference numbers for the charge and discharge circuit 200 are not in fig. 4, but they may be described as an RC circuit as follows: the circuit comprises a resistance branch formed by connecting a first resistor R1 and a first capacitor C1 in parallel and a capacitance branch formed by connecting a second capacitor C2 and a third capacitor C3 in parallel; one end of the first resistor R1 and one end of the first capacitor C1 are both grounded, the other ends are both connected to the first input end VR of the operational amplifier circuit 300, and the other ends are input ends of the resistor branches; one end of the second capacitor C2 and one end of the third capacitor C3 are both grounded, the other ends are both connected to the second input end VC of the operational amplifier circuit 300, and the other ends are input ends of the capacitor branches.

The circuit structures and functions of the counter, the bootstrap switch circuit, and the ICO are continuously described one by one below.

First, a counter 600 is described.

As can be seen from the foregoing, if the oscillator always operates at a large bias current, the power consumption of the oscillator is increased, so in the embodiment of the present invention, the counter is used for counting, so that the output current value IBIAS2 of the current source circuit is reduced after the operation of the oscillator is stabilized. Specifically, in an example of the embodiment of the present invention, the controlling the current source circuit 100 to output the bias current according to the counting result by the counter 600 may include: and when the number of the clock control signals counted by the counter exceeds a first preset clock number, controlling the current source circuit 100 to reduce the output second path bias current IBIAS2, where the first preset clock number is the number of the clock control signals correspondingly output when the feedback regulation type oscillator is stable in operation.

For example, in this example, the current source circuit is controlled by a counter to reduce power consumption and speed up loop stability establishment, namely: an extra large current IBIAS2 is provided for the operational amplifier circuit at the beginning of the electrification of the oscillator so as to accelerate the establishment speed of the operational amplifier circuit and reduce the difference of electrification speed between the operational amplifier circuit and the charging and discharging circuit, thereby enabling the loop to be faster and more stable and improving the precision of the oscillator; and after the oscillator works stably, the output value of the current source circuit is reduced, so that the power consumption is reduced.

Further, the first output terminal IBIAS1 of the current source circuit may include a first sub-output terminal IBIAS1a and a second sub-output terminal IBIAS1b, and the feedback-regulated oscillator may further include: a first selection switch SW1 provided at a first sub-output terminal IBIAS1a of the current source circuit; and a second selection switch SW2 provided at a second sub-output terminal IBIAS1b of the current source circuit. Wherein the first selection switch SW1, the second selection switch SW2, the input terminal of the R branch, and the input terminal of the C branch are connected in an interleaved manner, so that the current source circuit can provide bias current to the corresponding R branch or C branch through the first sub-output terminal IBIAS1a or the second sub-output terminal IBIAS1a in two different time periods in an exchange manner. Here, the "cross-connect" can be understood in conjunction with fig. 4, which is obvious to those skilled in the art and thus will not be described in detail.

Furthermore, the control terminals of the first selection switch SW1 and the second selection switch SW2 are connected to the clock control signal outputted by the digital logic circuit 500, so as to operate under the control of the clock control signal. For example, when the number of clock control signals counted by the counter is less than a second preset number of clock control signals, the first selection switch SW1 and the second selection switch SW2 are controlled based on the clock control signals, so that the current source circuit does not perform the switching between the first sub-output terminal and the second sub-output terminal when outputting the first path of bias current to the charge and discharge circuit, where the second preset number of clock control signals is the number of clock control signals that are correspondingly output when the oscillator has not reached a stable operating point.

That is, in the normal circuit, under the control of the switch SW1 and the switch SW2, in the first half period, the bias current source circuit IBIAS1a supplies current to the R branch where R1 is located, and the bias current source circuit IBIAS1b supplies current to the C branch where C2 and C3 are located; in the second half period, the power supplies of the current source circuits start to be exchanged, the bias current source circuit IBIAS1b supplies current to the R branch where R1 is located, and the bias current source circuit IBIAS1a supplies current to the capacitor branches where C2 and C3 are located. The power supply switching of the current source circuit is to eliminate the influence of the difference between the current source circuits IBIAS1a and IBIAS1b on the output frequency of the resistor and the capacitor, and can effectively inhibit the influence of offset voltage and flicker noise on the circuit. However, when the capacitor charging is not complete, IBIAS1a and IBIAS1b are swapped, which introduces a power-up error in the capacitor branch into the resistor branch, reducing oscillator accuracy. This is because, before the input voltage VC at one end of the operational amplifier circuit is not stabilized, the current in the branch where the resistor R1 is located is different from the current in the branch where the capacitors C2 and C3 are located, and the current source circuits supplying power to the branches C2 and C3 may operate in a non-saturation region, at this time, the current in the branches C2 and C3 may be 0, and the current in the branch R1 is still IBIAS1, at this time, if the current source circuits in the two branches are switched, a transition period may occur, which causes the voltage VR across the resistor to be unstable, and VR is used as a reference voltage of the entire circuit, and if an unstable condition occurs, the entire loop may be unstable, which seriously affects the setup time, power consumption, and accuracy of the oscillator. Therefore, in the example of the embodiment of the present invention, the working conditions of the switch SW1 and the switch SW2 are controlled by the counter, so that the oscillator does not perform the exchange of the charging current source circuit until the oscillator does not reach the working voltage, thereby preventing the power-on errors of each branch of the circuit, especially the capacitor branch and the operational amplifier circuit, from being introduced into the oscillator, causing an influence on the working state of the whole circuit, and then ensuring the normal operation of the oscillator and the accuracy of the oscillator.

Second, it relates to the switch circuit.

Referring to fig. 4, the switch circuit according to the embodiment of the present invention may be a bootstrap switch circuit, and the bootstrap switch circuit may include: a fifth capacitor C5, having one end connected to a first timing control signal outp, and the other end connected to the drain of the first MOS transistor M1, where the first timing control signal outp is the clock control signal output by the digital logic circuit; a source electrode of the first MOS transistor M1 is connected to a working power supply, a gate electrode of the first MOS transistor M1 is connected to the first timing control signal outp, and a drain electrode of the first MOS transistor M2 is connected to a drain electrode of the second MOS transistor M2; a drain of the second MOS transistor M2 is connected to the drain of the first MOS transistor M1, a gate of the second MOS transistor M2 is connected to the second timing control signal outn, and a source of the second MOS transistor M2 is connected to the drain of the third MOS transistor M3; a drain of the third MOS transistor M3 is connected to the source of the second MOS transistor M2, a gate of the third MOS transistor M3 is connected to the third timing control signal outn _ d, and a source of the third MOS transistor M3 is grounded; a fourth MOS transistor M4 connected in parallel with the C branch, wherein a source and a drain are respectively connected to two ends of the C branch, and a gate is connected to a second timing control signal outn; and the fifth MOS tube M5 is connected in series with the C branch, the source and the drain of the fifth MOS tube M5 are connected in series with the C branch, and the gate of the fifth MOS tube M5 is connected with the source of the second MOS tube M2.

The first timing control signal outp, the second timing control signal outn and the third timing control signal outn _ d are configured to control the respective corresponding MOS transistors such that the fourth MOS transistor M4 and the fifth MOS transistor M5 are not turned on simultaneously. The coordination of these three timing control signals and the control of the corresponding MOS transistors will be further described with reference to fig. 5.

Fig. 5 is a timing diagram of control signals of a bootstrapped switch circuit in an example of an embodiment of the present invention, which includes the three timing control signals outn _ d, outn, and outp, and the timing situation is as shown in fig. 5, so as to construct a plurality of complementary overlapped clocks. The MOS tube is controlled based on the complementary overlapped clock, and errors introduced to the oscillator by the MOS tube in the process of switching on and off are eliminated.

Further, the bootstrap switch circuit is a voltage boost circuit, so that the following functions can be realized by utilizing the characteristic that the capacitor stores charge: the voltage on the capacitor outp + the supply voltage vdd equals the output voltage VOUT. That is, the maximum value Vg of the gate voltage of the MOS transistor M5 is vdd + outp 2 × vdd.

As a core sub-circuit of the oscillator, the branches R1, C2 and C3 in FIG. 4 are sensitive to leakage, so that controlling the conductivity and the leakage of the MOS transistor will greatly help to improve the accuracy of the oscillator and reduce the power consumption of the oscillator. The embodiment of the invention designs the special time sequence control signal to assist the operation of the bootstrap switch circuit, can improve the conductivity of the switch to the greatest extent, reduce electric leakage, improve the precision of the oscillator, reduce the power consumption of the oscillator, and can also enable the oscillator to work under lower power voltage. With reference to fig. 4 and 5, the specific operation process of the switching circuit is as follows: in the first half period, when outp is 0, outn is 1, and outn _ d is 1, the transistor M1 may be turned on, the transistor M2 is turned off, the transistor M3 is turned on, the transistor M4 is turned on, the gate voltage of the transistor M5 is discharged to 0, the voltage value at the other end of the capacitor C5 is vdd, and the transistor M5 is turned off; in the latter half period, when outp is 1, outn is 0, and outn _ d is 0, the M1 tube is turned off, the M2 tube is turned on, the M3 tube is turned off, the M4 tube is turned off, the gate voltage of the M5 tube is equal to the voltage value at the other end of the capacitor C5, and is vdd + outp, so that the conductivity of the M5 tube is improved.

Accordingly, the special timing diagram designed as fig. 5 and using a plurality of complementary overlapping clocks is used to cooperate with the operation of the bootstrap switch circuit, so that not only can the overshoot be reduced, but also the M4 tube and the M5 tube are ensured not to be simultaneously conducted, thereby reducing unnecessary electric leakage, improving the precision, reducing the power consumption, and further reducing the frequency deviation caused by the extra discharged charges due to the electric leakage. In addition, the control voltage of the MOS tube is raised through the bootstrap switch circuit, the conductivity of the switch can be improved to the greatest extent, the electric leakage is reduced, the precision of the oscillator is improved, the power consumption of the oscillator is reduced, and the whole circuit can work under a lower power supply voltage.

Third, regarding the current controlled oscillator ICO.

Referring to the signaling diagram shown in fig. 2, the current controlled oscillator 400 may include two parts, namely: a current conversion module 410 (not shown in fig. 4, shown in fig. 6), an input terminal of which is an input terminal of the current controlled oscillator, for combining the third bias current IBIAS3 output by the current source circuit, and converting the voltage signal V0 output by the operational amplifier circuit into a current signal and outputting the current signal; and a clock transition module 420 (not shown in fig. 4, shown in fig. 6), an input end of which is connected to the current transition module 410, and is configured to convert the current signal output by the current transition module into a clock signal in a frequency form and output the clock signal. It should be noted that the current controlled oscillator 400 in fig. 4 is a schematic diagram, and a specific circuit structure of the current controlled oscillator 400 can refer to fig. 6.

Fig. 6 is a circuit schematic of a current controlled oscillator in an example of an embodiment of the present invention. Referring to fig. 6, the current transition module 410 includes: a sixth MOS transistor M6, a drain and a gate of which are used as input terminals of the current conversion module to respectively access the third bias current IBIAS3 output by the current source circuit and the voltage signal VIN output by the operational amplifier circuit, and a source of which is grounded; the gates of the seventh MOS transistor M7 and the eighth MOS transistor M8 are connected to the drain of the sixth MOS transistor M6, the sources are both connected to a working power supply, the drain of the seventh MOS transistor M7 is connected to the gate thereof, and the drain of the eighth MOS transistor M8 is connected to the drain of the ninth MOS transistor M9; the gates of the ninth MOS transistor M9 and the tenth MOS transistor M10 are connected to the drain of the eighth MOS transistor M8, the sources are grounded, the drain of the ninth MOS transistor M9 is connected to the gate thereof, and the drain of the tenth MOS transistor M10 is used as the output terminal of the current conversion module.

Where VIN is the output voltage of the prior op-amp circuit 300, under the control of which a current I is formed in the M6 tube_M6And finally forms the current I in the M9 tube by the current mirror of the M7 tube and the M8 tube and the bias current IBIAS3_M9＝I_M6IBIAS 3. Further, a fourth capacitor C4 may be further disposed between the VIN terminal and ground for implementing filtering.

The invention uses the current control oscillator, the voltage of the output end of the operational amplifier circuit is converted into the current through M6, M7, M8, M9 and M10 tubes and the bias current IBIAS3 and is input into the ICO circuit, on one hand, the circuit outputs the clock signal CLKOUT under the control of the current, because the output range of the operational amplifier circuit is narrower, but the controllable current range is wider, the control current range supplied to the current control oscillator circuit can still be very wide, thereby widening the output frequency range of the whole circuit and matching the corresponding frequency range of the front RC circuit, which not only greatly improves the accuracy of the oscillator, but also reduces the power consumption thereof and creates the condition for the application of the oscillator in the low voltage domain; on the other hand, the current of the whole circuit is limited and the power consumption is controllable due to the introduction of the current source circuit, and the current source circuit is used as a module with the largest power consumption except the digital logic circuit in the whole circuit, so that the power consumption of the oscillator is greatly reduced.

With continued reference to fig. 6, the clock transition module 420 may include: the gates of the eleventh MOS transistor M11 and the twelfth MOS transistor M12 are connected and serve as the input end of the clock transition module, the sources are both connected to a working power supply, the drain of the eleventh MOS transistor M11 is connected to the gate thereof, and the drain of the twelfth MOS transistor M12 is connected to the first control end of an inverter unit; the gates of the thirteenth MOS transistor M13 and the fourteenth MOS transistor M14 are connected, the sources are grounded, the drain of the thirteenth MOS transistor M13 is connected to the second control end of the inverter unit, and the drain of the fourteenth MOS transistor is connected to the drain of the fifteenth MOS transistor M15; the inverter unit is also provided with an input end and an output end A which are connected, and the output end A of the inverter unit is connected to the grid electrode of a seventeenth MOS tube M17; the gates of the fifteenth MOS transistor M15 and the sixteenth MOS transistor M16 are connected, the sources are both connected to the working power supply, the drain of the fifteenth MOS transistor M15 is connected to the gate thereof, and the drain of the sixteenth MOS transistor M16 is connected to the drain of the seventeenth MOS transistor M17 and serves as the output end of the clock conversion module; and a seventeenth MOS transistor M17 having a gate connected to the output a of the inverter unit, a drain serving as the output of the clock transition module, and a source grounded. In addition, the sources of M10, M13, and M14 are connected.

Wherein the inverter unit is a ring oscillator formed by cascading three-phase inverters, as shown in fig. 6. When the frequency is high, the voltage value of the output terminal A of the ring oscillator is not from the power supply VDD to the ground VSS, but is between VDD and VSS at a value of V1-V2. Ideally, when the M12 and M13 tubes are the same size and operation, i.e., are fully symmetrical, there is V1-VSS-VDD-V2. However, in practical design, a small offset voltage (e.g. 3mv) between the M11 transistor and the M12 transistor and between the M10 transistor and the M13 transistor causes a current mismatch between the M12 transistor and the M13 transistor, which in turn causes a voltage range of an output terminal a of the inverter to shift, thereby causing a load circuit at a point a to be inoperative, the inverter to be not inverted, and even causing a vibration stop, i.e. the circuit is very sensitive to offset (mismatch) of devices.

In order to solve this problem, in the embodiment of the present invention, the twelfth MOS transistor M12 and the thirteenth MOS transistor M13 are configured to have different sizes. Preferably, the width of the thirteenth MOS transistor M13 is configured to be greater than the width of the twelfth MOS transistor M12, for example, the width (W value) of the M13 transistor is 2 times that of the M12 transistor, that is, the effect of the offset (mismatch) of the device on the circuit is made negligible by intentionally and greatly biasing the operating state, so as to eliminate the effect of the offset on the circuit, where the output voltage range of the a terminal shifts toward VSS. In addition, because the circuit is no longer sensitive to mismatches, the dimensions of the tubes in the module can be made relatively small to reduce circuit parasitics, thereby further improving oscillator accuracy.

In addition, a sixth capacitor C6 may be connected to the inverter unit, and the other end of the sixth capacitor C6 is grounded, so as to implement voltage stabilization filtering on the inverter output.

Further, the clock transition module 420 may further include: a seventh capacitor C7, having one end connected to the gates of the fifteenth MOS transistor M15 and the sixteenth MOS transistor M16, and the other end connected between the gate of the seventeenth MOS transistor M17 and the output terminal a of the inverter unit.

The capacitor C7 is used for isolation, so that the jitter of the CLKOUT terminal can be prevented from being coupled to the gate of the M16 transistor, and the gate voltages between the M16 transistor and the M17 transistor can be relatively independent; on the other hand, the charge moving is completed, so that the conductivity of the M16 tube is improved on the premise of ensuring the circuit oscillation, the conductivity between the M16 tube and the M17 tube is similar, the design difficulty of the sizes of the M16 tube and the M17 tube is reduced, and the oscillator can work under a lower power supply voltage. And, for the group of inverters composed of M16 tubes and M17 tubes, the current value is limited by the current mirror composed of M9, M14, M15 and M16 tubes, i.e., the M16 tube and the M17 tube are current-limited inverters, thereby further reducing the power consumption of the circuit.

Therefore, with the aid of the capacitor C7, although the output voltage range of the a terminal is shifted toward VSS, the similar conduction between the M16 transistor and the M17 transistor can be ensured, so that the accuracy of the oscillator is improved and the oscillator is ensured to operate normally on the premise of reducing power consumption and power supply voltage, and the finally obtained output signal CLKOUT is a clock signal with the voltage range restored to VDD-VSS.

In summary, in the example of the embodiment of the present invention, the counter is introduced to control the operation of the current source circuit and the charge and discharge circuit, so as to improve the accuracy of the oscillator and reduce the power consumption of the oscillator; the precision of the oscillator is greatly improved, the power consumption of the oscillator is reduced and the oscillator can work under lower power supply voltage by designing and adopting a bootstrap switch circuit controlled by a special time sequence and a current-controlled digital logic circuit; in addition, the output frequency range of the oscillator is widened and the accuracy of the oscillator is improved on the one hand, and the power consumption of the oscillator is reduced on the other hand by designing the current-controlled current control oscillator (ICO), so that the oscillator can work under lower power supply voltage. That is, the feedback adjustment oscillator according to the embodiment of the present invention can satisfy any one or more of low voltage, low power consumption, and high accuracy characteristics.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.

The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A feedback-regulated oscillator, comprising:

the current source circuit is used for outputting three paths of bias currents through three output ends respectively;

the charging and discharging circuit is connected with the first path of bias current output by the current source circuit, is used for charging and discharging according to the first path of bias current, and converts frequency signals generated correspondingly by charging and discharging into voltage signals and outputs the voltage signals;

the operational amplifier circuit is connected with a second path of bias current output by the current source circuit and a voltage signal output by the charge and discharge circuit, and is used for responding to the second path of bias current to start working so as to amplify and output the voltage signal;

the current control oscillator is connected with a third path of bias current output by the current source circuit and an amplified voltage signal output by the operational amplifier circuit, and is used for converting the amplified voltage signal into a current signal according to the third path of bias current, converting the current signal into a clock signal in a frequency form and outputting the clock signal; and

and the digital logic circuit is accessed to a clock signal output by the current control oscillator, is used for converting the clock signal into a clock control signal and outputting the clock control signal for application, and feeds the clock control signal back to the charging and discharging circuit and the current source circuit so as to respectively control the charging and discharging speed of the charging and discharging circuit and the bias current output by the current source circuit.

2. The feedback-regulated oscillator according to claim 1, further comprising:

the counter is arranged between the output end of the digital logic circuit and the current source circuit and is used for counting the clock control signals and controlling the current source circuit to output bias current according to a counting result; and/or

The switch circuit is arranged between the output end of the digital logic circuit and the charging and discharging circuit, and comprises a plurality of MOS tubes, and the switch circuit is used for controlling the conduction or the disconnection of different MOS tubes according to a time sequence control signal which is configured in advance and aims at each MOS tube so as to control the charging and discharging speed of the charging and discharging circuit by transmitting the clock control signal.

3. The feedback-regulated oscillator according to claim 2, wherein the counter for controlling the current source circuit to output the bias current according to the count result comprises:

and when the number of the clock control signals counted by the counter exceeds a first preset clock number, controlling the current source circuit to reduce the output second path of bias current, wherein the first preset clock number is the number of the clock control signals correspondingly output when the feedback regulation type oscillator works stably.

4. The feedback-regulated oscillator according to claim 2, wherein the first output terminal of the current source circuit comprises a first sub-output terminal and a second sub-output terminal, and the charging and discharging circuit comprises a capacitor C branch for charging and discharging and a resistor R branch serving as a charging and discharging reference;

further, the feedback adjustment type oscillator further includes:

a first selection switch SW1 provided at a first sub-output terminal of the current source circuit; and

a second selection switch SW2 provided at a second sub-output terminal of the current source circuit;

wherein the first selection switch SW1, the second selection switch SW2, the input terminal of the resistor Rbranch and the input terminal of the capacitor Cbranch are connected in an interleaving manner, so that the current source circuit can provide bias current to the corresponding resistor Rbranch or the capacitor Cbranch through the first sub-output end or the second sub-output end in two different time periods in an exchanging manner;

the control ends of the first selection switch SW1 and the second selection switch SW2 are connected to the clock control signal output by the digital logic circuit, so as to operate under the control of the clock control signal.

5. The feedback-regulated oscillator of claim 4, wherein the counter is further configured to:

when the number of clock control signals counted by the counter is less than a second preset number of clocks, controlling the first selection switch SW1 and the second selection switch SW2 based on the clock control signals so that the current source circuit does not perform the switching between the first sub-output terminal and the second sub-output terminal when outputting the first path of bias current to the charge and discharge circuit, wherein the second preset number of clocks is the number of clock control signals correspondingly output when the feedback regulation type oscillator has not yet reached the working voltage.

6. The feedback-regulated oscillator according to claim 2, wherein the switching circuit is a bootstrap switching circuit, and the bootstrap switching circuit comprises:

a fifth capacitor C5, having one end connected to a first timing control signal outp, and the other end connected to the drain of the first MOS transistor M1, where the first timing control signal outp is the clock control signal output by the digital logic circuit;

a source electrode of the first MOS transistor M1 is connected to a working power supply, a gate electrode of the first MOS transistor M1 is connected to the first timing control signal outp, and a drain electrode of the first MOS transistor M2 is connected to a drain electrode of the second MOS transistor M2;

a drain of the second MOS transistor M2 is connected to the drain of the first MOS transistor M1, a gate of the second MOS transistor M2 is connected to the second timing control signal outn, and a source of the second MOS transistor M2 is connected to the drain of the third MOS transistor M3;

a drain of the third MOS transistor M3 is connected to the source of the second MOS transistor M2, a gate of the third MOS transistor M3 is connected to the third timing control signal outn _ d, and a source of the third MOS transistor M3 is grounded;

a fourth MOS transistor M4 connected in parallel to the capacitor C branch, wherein a source and a drain are respectively connected to two ends of the capacitor C branch, and a gate is connected to a second timing control signal outn; and

a fifth MOS transistor M5, which is connected in series with the capacitor C branch, and has a source and a drain connected in series with the capacitor C branch, and a gate connected to the source of the second MOS transistor M2;

the first timing control signal outp, the second timing control signal outn and the third timing control signal outn _ d are configured to control the respective corresponding MOS transistors such that the fourth MOS transistor M4 and the fifth MOS transistor M5 are not turned on simultaneously.

7. The feedback-regulated oscillator according to claim 1, wherein the current-controlled oscillator comprises:

the input end of the current conversion module is the input end of the current control oscillator, and the current conversion module is used for converting the voltage signal output by the operational amplifier circuit into a current signal and outputting the current signal in combination with the third path of bias current output by the current source circuit; and

and the input end of the clock transition module is connected with the current transition module and is used for converting the current signal output by the current transition module into a clock signal in a frequency form and outputting the clock signal.

8. The feedback-regulated oscillator according to claim 7, wherein the current transition module comprises:

a sixth MOS transistor M6, a drain and a gate of which are used as input terminals of the current conversion module to respectively access the third bias current output by the current source circuit and the voltage signal output by the operational amplifier circuit, and a source of which is grounded;

the gates of the seventh MOS transistor M7 and the eighth MOS transistor M8 are connected to the drain of the sixth MOS transistor M6, the sources are both connected to a working power supply, the drain of the seventh MOS transistor M7 is connected to the gate thereof, and the drain of the eighth MOS transistor M8 is connected to the drain of the ninth MOS transistor M9;

the gates of the ninth MOS transistor M9 and the tenth MOS transistor M10 are connected to the drain of the eighth MOS transistor M8, the sources are grounded, the drain of the ninth MOS transistor M9 is connected to the gate thereof, and the drain of the tenth MOS transistor M10 is used as the output terminal of the current conversion module.

9. The feedback-regulated oscillator of claim 7, wherein the clock transition module comprises:

the gates of the eleventh MOS transistor M11 and the twelfth MOS transistor M12 are connected and serve as the input end of the clock transition module, the sources are both connected to a working power supply, the drain of the eleventh MOS transistor M11 is connected to the gate thereof, and the drain of the twelfth MOS transistor M12 is connected to the first control end of an inverter unit;

the gates of the thirteenth MOS transistor M13 and the fourteenth MOS transistor M14 are connected, the sources are grounded, the drain of the thirteenth MOS transistor M13 is connected to the second control end of the inverter unit, and the drain of the fourteenth MOS transistor is connected to the drain of the fifteenth MOS transistor M15;

the inverter unit is also provided with an input end and an output end A which are connected, and the output end A of the inverter unit is connected to the grid electrode of a seventeenth MOS tube M17;

the gates of the fifteenth MOS transistor M15 and the sixteenth MOS transistor M16 are connected, the sources are both connected to the working power supply, the drain of the fifteenth MOS transistor M15 is connected to the gate thereof, and the drain of the sixteenth MOS transistor M16 is connected to the drain of the seventeenth MOS transistor M17 and serves as the output end of the clock conversion module; and

and a seventeenth MOS transistor M17 having a gate connected to the output a of the inverter unit, a drain serving as the output of the clock transition module, and a source grounded.

10. The feedback-regulated oscillator according to claim 9, wherein the twelfth MOS transistor M12 and the thirteenth MOS transistor M13 are different in size.

11. The feedback-regulated oscillator according to claim 10, wherein the thirteenth MOS transistor M13 has a width greater than a width of the twelfth MOS transistor M12.

12. The feedback-regulated oscillator of claim 9, wherein the clock transition module further comprises:

a seventh capacitor C7, having one end connected to the gates of the fifteenth MOS transistor M15 and the sixteenth MOS transistor M16, and the other end connected between the gate of the seventeenth MOS transistor M17 and the output terminal a of the inverter unit.